JPS5844492A - Display system for electronic equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display system in electronic devices such as electronic calculators, and more particularly to a new display system for controlling and operating the display of computers and the like.

Conventionally, in the display system of electronic calculators, if it is desired to display more digits than the number of digits of the display, the data to be displayed must be separated and switched twice or more.

However, such a switching method has the drawback that the relationship (connection) between the previously displayed display content and the currently displayed display content is not clear, and there is a risk of misreading. The present invention is to overcome the aforementioned drawbacks.

The purpose of the present invention is to provide a display method for electronic devices such as electronic calculators that can display display information that exceeds the display content that can be displayed on a display body by displaying character contents such as numbers, letters, and symbols in a running manner on a display body. By this, the above-mentioned difficulty can be overcome by continuously moving the display contents, and there is no need to change the display, and the operator can read it very naturally. Providing a display method? Yes, one feature of the present invention is to cycle the display contents so that after some display contents are displayed running and disappear completely from the edge of the display section, the beginning of the same display contents is displayed again. To obtain a display system in which two display contents are displayed running, and the beginning of the same display contents is not displayed until they are all disappeared from the edge of a display part, and the divisions of the display are clear and there is no misreading.

Another feature is that by providing a display method that can distinguish between normal display (so-called static display) and running display depending on the type of display content, for example, data such as calculation results can be displayed normally (static display). The display of instructions such as calculation procedures should be displayed in a running manner at predetermined intervals so that the meaning of the display can be differentiated depending on the state of display, even if the content is the same. It is.

This method is particularly effective when used in scientific calculators and the like.

Another feature is that the display contents can be displayed in units of one digit, and the computer can enter the Hart state (
If a so-called state occurs during the execution of a program (in the step where data is input from the outside), the calculation is temporarily stopped until the data is input, the data running is displayed to display instructions for the next data to be input, Furthermore, it is an object of the present invention to provide a display system for a computer, etc., which is capable of changing the display contents by -, and which is equipped with various functions capable of displaying the calculation results for a certain period of time immediately before the display state.

Further objects and advantages of the present invention will become apparent from the following description and the accompanying drawings.

FIG. 1 is an external view showing an embodiment of a program computer equipped with the display system of the present invention, and FIG. 2 is a state diagram showing an example of the display state of the computer.

In Fig. 1, 1 indicates the display section, 2 indicates the key input section, and Figs. 2 (a) to (i) show the functions of a scientific calculator, etc., especially during calculation.
An example of a case in which the next data to be input is instructed when the system enters the Hart state will be explained.

Here, (a) is a normal display, (b) to (g) are display states at the time of display based on the display method of the present invention,
(b) is a table of the first characters of the instructions for the next data to be input.

In this state, after a certain period of time (for example, 0.5 seconds), the state shown in (c) is reached, and after the next 0.5 seconds, the state shown in (d) is obtained. In this way, the display contents are displayed running, (b) → (c) → (d
)→・・・(e)→(f)→・・・(g)→(h)→(
After the state becomes i) and all the displays disappear, the state becomes the state of (b), and thereafter the display is repeated in the same way.

FIG. 3 is a block diagram of an embodiment of a computer equipped with the display system of the present invention. In the figure, 8 is a key human power device, 4
is the central processing unit r (Cent-ral-Pr), which will be described later.
ocessor (lnit) hereinafter referred to as CPIJ. ”
It is a device that decodes and executes instructions. 5 is register SA
, a character generator (CRG) for decoding output signals from the SX, 6 a 5×7 8-digit dot matrix type display, 7 a digit selection signal, and 8 a segment signal.

Figure 4 shows the CPTJ of a computer that executes the display method of the present invention.
FIG. 4 is a logic circuit diagram of an embodiment of the device;
- Contains 4D diagrams. FIG. 5 is a diagram illustrating a circuit equivalent to the CPtJ device of FIG. 4.

The specific logic circuit configuration of the CPU will be described below.

(Circuit configuration of CPU) RAM is random access memory, input/output is 4
This is done bit by bit, and desired digit content can be input and output by specifying a digit address and file address. BL is the digit address counter of the memory RAM, Del is the digit address decoder of the memory RAM, BM is the file address counter of the memory RAM, DC2 is the file address decoder of the memory RAM, ADI is the adder, and when control instruction 0 is given. operates as a subtracter, and when ■ is not provided, it operates as an adder. AD2 is an adder, Gl is an adder/subtracter ADI
This is a gate for giving either the numerical value 1 or the operand IA to one input of the control command, and outputs I when the control command [phase] is given, and outputs IA when it is [phase]. G2 is the input gate of the memory digit address counter BL, [
When the phase is 1, the output of the adder/subtractor AD is output, when the phase is 2, the operand IA is output, and when the phase is 2, the operand IB is output. G3 is a gate for supplying either the numerical value 1 or the operand IA to one input of the adder/subtractor AD2; when ■, the numerical value 1 is given; when ■, the operand! Output A.

G4 is the input gate of memory file address BM,
When (2), the output of the adder AD2 is output, when (2), the operand IA is output, and when (2), the contents of the accumulator ACC are output. G
5 is a file selection gate of the memory RAM, and DC3 is an operand IA decoder that decodes operand IA.
A signal specifying a desired memory bit is input to gate G6. G6 is the input gate of the memory IJ-RAM, and when the control command ■ is given, it inputs the binary number l to the desired bit of the memory specified by the operand decoder DC3, and
At the time of , a circuit is built in to manually input a binary number Ot- to the desired bit of the memory specified by DC3, and the contents of the accumulator ACC are outputted at . ROM is read-only memory, PL is a program counter, and read-only memory.
Specify the desired step of the only memory ROM.

nc4 is a read-only memory ROM step access decoder, C7 is a read-only memory ROM output gate, and a judge flip-flop (F
/F) When J is set, the ROM output is transmitted to the instruction decoder DC5.
It decodes the instruction code from R.
OM instruction code is opcode part IQ
and operand part IA.

The IB is divided into IBs, the operation code is decoded, and one of the control commands ① to [phase] is generated in accordance with the operation code. It also has a built-in circuit that determines that the opcode is accompanied by an operand and outputs the operand IA or IB as is at that time. ADq is an adder that adds the value 1 to the contents of the program counter PL to count up.

C8 is the input gate of the program counter PL, [phase]
When , the operand IA is output, and when it is [phase], the contents of the program stack register SP are transmitted.

When processing 0, [phase] and when processing 0 for G39, the output of adder AD3 is not transmitted. 0. ■, @ transmits the AD3 output and automatically outputs the program counter PL.
Add 1 to the contents of. FC is flag F/FSG9 is input gate of flag F/FFc, when it is 0, it is binary 1,
When [phase], binary 0 is flag F/F F
oGIo, which is for input to C, is a key signal generation gate, and the flag '/FFC or reset state (0)
When , the desired output of the memory digit address decoder Del is output as is, and when the flag F/FFC is set at 10, it is output as 11 regardless of the DCI output.
It has a built-in circuit that sets the outputs of ~I to 1 all at once. A.C.C.
is an accumulator consisting of 4 bits, X is a tempo 2-lead (temporary memory) register consisting of 4 bits, G1
1 is an input gate of the temporary register X, which transmits the contents of the accumulator ACC when it is [phase], and transmits the contents of the stack register Sx when it is 0.

AD4 is an adder, which sets the C4 output to 1 if a carry occurs in the addition of the fourth bit during binary addition used to add the contents of the accumulator ACC and other data in binary. C is carry F/F.

G12 is Kiya! J-F/F input gate, a circuit that inputs 1 to the carry F/F C if the fourth bit carry C4 is 1 when the control command ■ is generated, and inputs 0 to C if C4 is 0. Built-in. For [phase], set 1 to C,
In the case of (2), 0 should not be input to C. Cta is a carry C manual gate for performing binary addition including carry in the adder AD4.
The output of /FC is transmitted to adder AD4. GI4 is the input gate of adder AD4, and when it is [phase], memory R
The output of AM is transmitted, and when it is [phase], the operand IA is transmitted. F is a 4-bit output buffer register, G
15 is the input gate of the output buffer register F, [phase]
O19, which transmits the contents of the accumulator ACC and inputs it to F, is an output decoder that decodes the contents of the output buffer register F and outputs the display segment signal SSI ~
Also for converting to SSn. W is an output buffer register, and SHC is for shifting all bit contents of the output buffer register W by 1 bit to the right at once, and operates when [phase] or [phase] occurs. G16, which is a shift circuit of the output buffer register W, is an input gate of the output buffer register W. When it is [phase], l is input to the first bit of W, and when it is [phase], 0 is input to the first bit of W. It is assumed that the output buffer shift circuit SHC is operated immediately before inputting 1 or 0 to the first bit of W, and the output buffer is input after shifting.

Np is the output control flag F/p 5G17 is the input gate of the output control flag F/FNP, ■
Enter 1 for , and enter 0 for [phase].

This is the output control gate of the 618-h7 register W, and is used to output the outputs of each bit of W at the same time only when the flag F/PNP is set (1). J is a judge F/F, IVI to IV4 are inverter circuits, and GI9 is an input gate of the judge F/FJ, which is used to transmit the state of the input KNI to 1 at the time of [phase]. However, since it is passed through the inverter IVI, when KNI=0, KJ=1. G20 is an input gate of the judge F/FJ, and transmits the state of the input KN2 to J at the time of ■.

However, inverter Iv2. Since KN2=
At 00:00, J=1. G2+ is the input gate of judge F/FJ, and is used to transmit the state of input KFI to J during [phase]. However, inverter IV3G22 is the input gate of judge F/FJ, and when it is [phase], input KF2
Something that can't be used to convey the status of to J. Tashiinhata I
Since it is via V4, J=1 at KF2. G2
+3 is the input gate of judge F/F J, which is used to transmit the state of input AK to J when it is 0. When λ=1, J=1. G24 is a judge, an input gate of F/FJ, and is for transmitting the state of the input TAB to 1 in the case of 2. When OTAB=1, J=1. G25 is a gate for setting judge F/F J, and is for inputting 1 to J when it is @. ■L is a comparison circuit that compares the contents of the memory digit address counter BL with predetermined data and generates an output of 1 if they match.
@The circuit operates when Fio is generated. The comparison data is output from gate G26. G26
is the comparison value input gate to the comparison circuit v1, and the comparison value n1
corresponds to a specific address value on the high side that is often used for RAM control.

When ■, nl is output to use as a comparison value, and when ■, n" is output as a comparison value. 0G27 is the input gate of judge F/F J, and when @, ca! j −F
/FC When the content of C is 1, input 1 to J.

DC6 is a decoder for operand IA, which decodes operand IA and is used to judge whether the content of a desired bit in memory RAM is 1. o G28 is a memo IJ-RA'M.
This gate transmits the bit contents specified by the operand decoder DC6 to the judge F/F, and operates in [phase]. When the designated bit of RAM is 1, J=1. V2 is a comparison circuit that judges whether the contents of the accumulator ACC and the contents of the operand mA are equal.
When they are equal, an output l is generated. ■It works when. v8 is a comparator circuit, which is a counter BL that addresses memory digits.
It judges whether the contents of operand IA are equal to the contents of operand IA, and when they are equal, output 1 is generated. It operates at 0 [phase]. A comparison circuit v4 judges whether the contents of the accumulator ACC and the contents of the memory RAM are equal, and generates an output 1 when they are equal. G29 is a transmission gate for the addition fourth pit carry C4 to judge F/F J, and transmits C4 to F/F J when [stock]. At C4, J=1. FA is a flag flip-flop, C8
1 is the input gate of the flag F/FFA; when it is 0, it outputs l; when it is 0, it outputs 0. C82 is the input gate of judge F/FJ, and when flag F/FFA is 1, F/F
Set J (1). FB is flag F/F, G
ss is the input gate of flag F/FFB, and when ■, l
Outputs , and outputs 0 when it is 0. C84 is Judge F/v
F/F the contents of flag F/FFB at the input gate of J.
J) something to communicate. It operates when ■. C85 is an input gate of judge F/F J, which transmits the contents of input B and operates according to [phase]. When B=1, J=1.

C86 is the input gate of accumulator ACC, [phase]
When , the input/output of the adder AJ)4 is transmitted, and when it is [phase], the contents of the achievator ACC are inverted and transmitted by the inverter Iv5. When it is [phase], the contents of the memory RAM are transmitted, and when it is [phase], the contents of operand I are transmitted. ■
When , the contents of 4 bits 1 to 4 are transmitted to the input. [
Stock], the contents of the stack register SA are transmitted/reached.

IV5 is an inverter circuit, and SA is a stack register whose output is led out of the system. Sx is a stack register whose output is led out of the system. G87 is an input gate of the stack register SA, which transmits the contents of the accumulator ACC in [phase]. G88 is an input gate of the stack register Sx, which transmits the contents of the temporary register X when in [phase]. SP is program stack register, G39 is program stack register S
This is an input gate of P, and when it is 0, it is used to introduce the contents of the program counter PL plus l by the adder AD3 into the program stack register.

Next, the instruction code stored in the storage unit ROM of the CPU device, the instruction name, operation content, and an example of the control command generated based on the instruction code are shown in the table below.0 In the table, A: instruction code; B: Instruction a, C: Content, D: CPU 1st
Explanation of Table (C) I 5KIP Does not execute the instruction of the next program step, increments only the program counter PL, and essentially skips it.

AD Performs binary addition of the contents of the accumulator ACC and the contents of the memory RAM, and inputs the addition result to the accumulator ACC.

ADC Accumulator ACC, memory RAM.

Binary addition is performed on the contents of carry F/FC, and the addition result is input to accumulator ACC.

4 ADC8K Accumulator ACC, memory RAM.

Kiya! The contents of J-F/FC are subjected to binary addition, and the addition result is input to the achievator ACC, and if the fourth pit carry C4 occurs as a result of this addition, the next program step is skipped.

The contents of the accumulator ACC and the operand IA are added in binary, the addition result is input to the accumulator ACC, and if the fourth bit carry C4 occurs as a result of this addition, the next program step is skipped.

DC Operand IA is set to 1010 (decimal number 10), and A
Similar to the DI instruction, by performing binary addition of the contents of the accumulator ACC and this operand IA, a decimal number 10 is essentially added to the contents of the accumulator ACC, and the result is input to ACC.

9C Set carry F/FC.

(Enter 1 in C.) 　　RC Reset carry F/F C.

(Input 0 to C.) 8M Deciphers the contents of operand IA and sets the desired bit in the memory specified by the operand. (0 to input l) 0RM Decodes the contents of operand IA and resets the desired bit in the memory specified by the operand. (Input 0.) +l COMA Inverts the contents of each bit of accumulator ACC and sets 15
Take the complement of and input it to the accumulator ACC. 0 2LDI Introduce the operand mA to the accumulator ACC.

+3 L Introduces the contents of the memory RAM into the accumulator ACC, and inputs the operand IA into the file address counter BM. 0 4Ll Introduces the contents of the memory RAM into the accumulator ACC, and inputs the operand IA into the memory file address counter BM. Furthermore, the memory digit address counter BL is increased 0 However, when the contents of BL are equal to the predetermined value n1, the next program step is skipped 0 5LD The contents of the memory RAM are introduced into the accumulator ACC, and the operand IA is File address counter BM - manually input 0 and memory digit at.

The response counter BL' is decreased. However, when the content of BL is equal to the predetermined value n2, the next program step is skipped.

6X Exchanges the contents of the memory RAM with the contents of the achievator ACC, and inputs the operand IA to the memory file address counter BM.

17XI Exchanges the contents of the memory RAM and the contents of the accumulator ACC, and inputs the operand IAT to the memory file address counter BM. Furthermore, the memory digit address counter BL is increased.

However, when the content of BL is equal to the predetermined value n1, the next program step is skipped.

+8XD Exchanges the contents of the memory RAM and the contents of the accumulator ACC, and inputs the operand IA to the memory file address counter BM. Furthermore, the memory digit address counter BL is decreased.

However, when the content of BL is equal to the predetermined value n2, the next program step is skipped.

+9LBLI Input operand IA and memory digit address counter BL 0 0LB Input operand mA to memory file address counter B
At the same time, it is input to the operand fBt memory digit address counter BL.

1ABLI Performs binary addition of the contents of memory digit address counter BL and operand 1A, and stores the addition result in BL. However, when the content of BL is equal to the predetermined value n1, the next program is skipped.

2ABMI Performs binary addition of the contents of memory file address counter BM and operand IA, and stores the addition result in BM.

B T Input operand IA to program step counter PL 0 45KC Skip the next program step if carry F/FC is 1 0 55KM Decipher the contents of operand IA and set the desired bit of the memory specified by the operand to 1 If so, skip the next program step.

The contents of the 65KBI memory digit address counter BL and the operand IA are compared, and if they are equal, the next program step is skipped.

75KAl Compares the contents of accumulator ACC with operand IA, and if they are equal, skips the next program step 0 8SKAM Compares the contents of accumulator ACC with the contents of memory RAM, and if they are equal, skips the next program step 0 95KNI KNI When the input is 0, skip the next program step 0 05KN2 When the KN2 manual power is 0, skip the next program step.

15KFI KF1F1 Skips the next program step when using manual power.

-828KF2 When KF2 manual power is 00, skip the next program step.

138sKAK When the AK large input is 1, skip the next program step. 0 848KTAB When the TAB input is 1, skip the next program step.

55KFA When flag F/FFA is 1, skip the next program step.

65KFB When flag F/FFB is 1, skip the next program step.

37 W I S Shifts the contents of the output buffer register W one pit to the right and inputs 1 to the first bit (most significant pit).

88 W I R Shifts the contents of the output buffer register W to the right by 1 pit, and inputs 0 to the first bit (most significant pit).

9NFS Set buffer register W output control F/FNp. (Input 1.) 0NPR Reset buffer register W output control F/FNp. (Input 0.) 1ATF Transfer to register F.

2LXA The contents of accumulator ACC are transferred to temporary register
to be introduced.

3XAX Contents of accumulator ACC and temporary register X
Exchange the contents of 0 4SFA Set flag F/FFA. (Input l.) 5RFA Reset flag F/FFB. (Enter 0.

) 65FB Set flag F/p, Fnt. (Input l.), 7RFB Reset flag F/FFB. (Enter 0.

) 85FC Input test flag F/FF (! Set. (
Enter l. ) 9RFC Reset the input test flag F/F Fc.

(Enter 0.) 05KB When input β is 1, skip the next program step.

1KTA Introduce the contents of 4 to the input kl= into the accumulator ACC.

2STPO The contents of the achiemulator ACC are transferred to the stack register SA, and the contents of the temporary register X are transferred to the stack register SA.
Introduce it to Sx.

8EXPO Exchange the contents of accumulator ACC and stack register SA, and exchange the contents of temporary register X and stack register Sx. 0 4TML Add 1 to the contents of program counter PL and transfer it to program stack register SP. do. Furthermore, introduce the operand tA into the program counter PL O 5RIT Transfer the contents of the program stack register SP to the program counter PL 0 Next, the operation code ° stored in the ROM (read-on 1) -〇 memory) in the CPυ device The relationship between and operand is shown in Table 2.

Table 2 IO ↓ o DC6 However, IQ, operation, de IA IB: Taking the example where the output of the operand ROM is 10 bits, the instruction AD or COMA (see Table 1) is set to lθ pit in the instruction decoder DCs. Nocote is 0001011000 or 00010+11 each
It is determined by decoding that it is 11, and the control commands [phase], [
phase] or [phase]. The 5 KBI is determined based on the fact that the upper 6 bits are 000110, and at this time, the lower 4 bits 0010 are treated as operand IA. Furthermore, LB is determined by the upper 2 bits being 01,
At this time, the 3rd to 8th bits oo+oto are operand I
The 9th and 1st θ bits, 11, are treated as operand IB. operand
is a constituent part of an instruction word, and is a part that indicates data, the address where the next instruction is stored, etc., and can be called the address part of the instruction.

Next, an example of the main processing operations of the above-mentioned CPLI device (hereinafter referred to as a processing list) will be explained.
.

(Processing List) (1) Introduce the same numerical value N to the desired area of the memory RAM. (NNN-+X) (2) Introduce a plurality of predetermined different numerical values into a desired area of the memory. (Nl, N2, N9...→
X) (3) Transfer the contents of the desired area of memory to another desired area of memory. (x-+y) (4) Exchange the contents of the desired area of memory with the contents of another desired area of memory. (X←Y) (5) Add or subtract a predetermined numerical value N to or from a desired area of the memory. (X±N) (6) Add the contents of another area to the contents of the desired area of the memory in 10 base. (X±Y)- (7) Shift the contents of the memory in the desired area by one digit. (X right, X left) (8) Set or reset the 1-bit conditional F/F in the desired area of the memory. (Faet.

(9) Judge the contents of the 1-pit conditional F/F in the desired area of memory, and change the next program address based on the judgment result.

αQ Judges whether the digit content in the desired area of the memory is a predetermined value, and changes the next program step based on the judgment result.

aη Judge whether the contents of multiple digits in a desired area of the memory are all equal to a predetermined value,
Changing the program step based on the judgment result -0 (2) Judge whether the contents of the desired area of the memory are smaller than a predetermined value, and change the next program step based on the judgment result.

(To) Judge whether the contents of the desired area of memory are larger than a predetermined value, and change the next program step based on the judgment result.

α→ Display the contents of the desired area of memory.

(c) Determine the type of key switch that was pressed.

Next, a specific example of executing the processes (1) to (c) above based on the instruction code will be described below according to the process list.

(Specific example of processing list) (1) Introduce the same numerical value N to a desired area of memory.

(NNN-+X) IP=Nistep Pl...The first digit to be processed in the memory is specified by the file address mA and digit address nH.

P2... Introduce the number N into the ACC O12... Introduce the number N into the proposed area of the memory by exchanging the contents of the memory and the ACC. Since the memory file address does not change, mA is specified and the digit address is down to determine the next digit to be introduced. By predetermining the final digit nAO value to be introduced as n2, the desired total value of the numerical value N is saved, the next P4 is skipped, and the Type I processing is completed.

P4...Specify the program address to P2 and BL=
Repeat LDI and XD processing until V is reached.

Pl... Digits to be processed in memory are file address mB and digit address n.

Specify with.

P2... Introduce the numerical value N to ACC.

P8...Introduce the number N into the specified area of memory by exchanging the contents of memory and ACC.

In this way, the Type 2 processing is completed. The operand part of XD is necessary for the subsequent processing and is not relevant to this processing. 0 (Type 8) Pl... The first file address m (and digit address n) to be processed in memory.

Specify with.

P2... Introduce the numerical value N to ACC.

P8...Introduce the number N into the specified area of memory by exchanging the contents of memory and ACC. Since the file address in memory does not change, m is specified, and the digit address is down to determine the next digit to be introduced.

P4...The digits processed in P3 are the final dip)
When checking whether it was nB, when it was nB, the digit address was down to nA, so by setting the operand part of the SKl instruction to nA, the number N was introduced to the final digit, and P4 When proceeding to , the condition is satisfied and the next address P5 f, skip and end Type 8 0 If the condition is not satisfied, proceed to P5 O 20... Specify the program address to P2, BL=
Processes P2 to P4 can be repeated until nA is reached.

→X) (Type) 4-digit number N4 N3 N2 Nm
0 (the same applies to the introduction of arbitrary digits) Pl...The first digit to be processed in the memory is specified by the file address mA and the digit address nE.

P2... O12 to introduce the first constant N into ACC
...Introduces the number N1 into the specified area of memory by exchanging the contents of memory and ACC. Since the memory file address does not change, mA is specified, and the digit address is updated to determine the next digit to be introduced.

P4...Introduce a second constant N2 to ACC.

Since the memory is designated as the second digit in the processing of P5...P8, the second constant N2 is introduced into the second digit of the memory by exchanging the contents of the memory and ACC.

P6...-P9...Process in the same way as above.

(T)'pe2) When introducing any numerical value from 0 to 15 into a predetermined register.

Pl...Introduce a numerical value N to ACC.

P2...Introduce the numerical value N contained in ACC into register X.

Transfer to desired area. (X-+Y) (Type 1) ■ Pl... Specify the file address of the first memory to be processed in mA, and specify the first digit address to be processed in nH.

P2...The content of the desired digit in the first memory is A.
In addition to introducing it into the CC, in preparation for the transfer process at P8, the 7-isle address of the second memory as the transfer destination is specified in mB.

P3...The contents of the first memory introduced into the ACC are P3.
The contents of the same digit in the second memory specified in step 2 are exchanged to essentially transfer the contents of the first memory to the second memory. In order to repeat this process simultaneously, the original file address of the first memory is specified in mA. By predetermining the value of the final digit nA to be transferred as the old value, B in the state where all the contents of the first memory have been transferred to the second memory.
Since L == n 1 , the next P4 is skipped and the Type 1 processing ends. The digit address is increased sequentially until BL=V (last digit), and the file address returns to P2 via P4 in mA.
12...Specify the program address in step P2, repeat the commands P2 and P3 until B L=nl, and proceed with the transfer process for each digit. go.

pV: Memory area to be processed is specified by file address mA and digit address n. Specify with.

P2... ACC the contents of the memory area specified by Pl.
At the same time, in preparation for the transfer process at P4, the file address of the transfer destination memory is specified by m(.

P8...Specify the digit address of the transfer destination memory. The transfer destination memory area is specified in the processes P2 and P8.

P4...The contents of ACC are changed to P2. The operand of OX, which exchanges and essentially transfers the memory area specified in P8, is not directly related to this process.0 Pl... Specify the memory area to be processed with file address m and digit address n. .

P2... ACC the contents of the memory area specified by P.
to be introduced.

P3...Introduces the contents of memory 2 introduced into ACC into register X, and executes the desired T7pe 3 transfer process.

Pl,...The first memory file address to be processed is specified by m, and the first digit address to be processed is specified by nH.

P2...The content of the desired digit in the first memory is A.
In addition to introducing it into the CC, the file address of the second memory is specified in mB in preparation for the exchange process with the second memory in step P8.

P8...The content of the desired digit in the first memory stored in the ACC is exchanged with the content of the same digit in the second memory specified in P2, and the content of the second digit transferred to the ACC in this process is exchanged. In order to introduce the contents of one memory into the first memory, the file address of the first memory is specified in mA.

P4...The contents of the second memory introduced into the ACC,
The contents of the first memory of the same digit are exchanged, and the second
Transfer the contents of the memory to the first memory. P2~P4
In this process, contents are exchanged between desired digits in the memory. The designation of the first memory is continued by designating the file address mA, the digit address is increased, the next digit address is designated, and the exchange is performed for each digit in sequence. The final digit n to be exchanged
By predetermining the AO value as nl, the state becomes BL"nl after the contents of the first memory and the second memory have been exchanged for all digits, so the next P5 is skipped and Type Finish processing.

P5...Specify the program address to P2, B, =
The commands P2 to P4 are repeated until n1 is reached, and the exchange process continues for each digit.

Pl...Specify the file address of the first memory to be processed in mA, and specify the digit address to be processed in n.
(Specify O P2...The contents of the desired digit in the first memory are A
CC and the file address m of the second memory. Specify and prepare for content conversion.

P3... Digit address n of the second memory of the transfer destination. Specify the memory address of the replacement destination. O P4...The contents of the first memory contained in the ACC,
Converting the contents of the second memory. At this time, in order to transfer the contents of the second memory transferred to the ACC to the first memory, specify the file address of the first memory in mB again.OP5... Specify the digit address nc of the first memory, and transfer the file address to the first memory. Determine the first memory address of.

P6...The contents of the second memory in ACC and (
Type 8) PV: The file address in the first memory to be processed is specified by mA, and the digit address to be processed is specified by n(.

p2 , , Introduces the contents of the first memory into the ACC, and specifies the file address m (of the second memory) as the exchange destination.

P3...Exchanges the contents of the first memory of ACC and the contents of the second memory designated by p2, and introduces the contents of the first memory into the second memory.

In preparation for processing at P4, the first memory is designated again with the file address mB.

P4: Exchange the contents of the first memory and the second memory by exchanging the contents of the second memory introduced into the ACC with the contents of the first memory.

("S'f124) Pl...Specify the memory area to be processed using the 71 file address m and digit address nc.

P2...Introduces the contents of the memory specified by Pl into ACC. Maintain the file address mB in preparation for exchanging the contents of register X.OP3...Exchange the contents of the memory stored in ACC with the contents of register

P4...By exchanging the contents of register X contained in ACC with memory, the contents of register X are essentially transferred to memory and "1"ype4 is executed.

(Type) Ml 10N → M P1... Specify the area of memory to be processed using file address mB and digit address nc.

P2...Introduces the contents of the memory specified by Pl into ACC. Specify mB as the memory file address in order to return to the same memory later.

P3... Specify the numerical value N to be added with the operand, and
Add the contents of the memory introduced into the CC and the numerical value N, and obtain the result in the ACC.

P4...Exchanges the sum found in ACC with the original memory content specified in P2, and executes Type 1.

(Type 2) X+N-x Pl...O exchanges the contents of register
Add the contents of register X introduced in CC and the number N,
The results will be requested from ACC.

P3... By exchanging the sum found in ACC and the contents of register X, Ty, e which becomes essentially X+N→X
Execute 2.

(Typ68) M 1 + N → M2P1...The area to be processed in the first memory is the file address mB and the digit address n. Specify with.

P2...Introduces the contents of the memory specified by Pl into ACC. The memory file address is specified as the file address m of the second memory in order to return the addition result to the second memory. Specify.

P3... Specify the numerical value N to be added with the operand, and
The contents of the memory introduced into the CC are added to the numerical value N, and the result is obtained from the ACC.

P4...The second value specified by P2 is the sum obtained for ACC.
Convert the contents of the memory of , and execute Ty and e3.

(Type 4) Ml-N→MIP engineering 00. Processing memory file address m
and digit address nC.

P2...Subtraction is a method of adding the complement of the subtracted number to the minuend,
Since there is no lower digit, there is no borrow and F/FC is set.

P3...Introduce a subtractive number N to ACC.

P4: In the process of taking the 15's complement of the subtracted number, the complement is found in ACC.

P5...If there is no borrow from the lower digits, the subtraction is replaced by the process of adding the six's complement of the subtracted number and the subtracted number. Assuming that C=1 when there is no borrow, ACC+C+M-ACC
Pure binary subtraction is performed at .

P6: Exchange the ACC and memory in order to return the difference found in P5 to the same memory.

('Type5) MIN-+M2P6...
・In order to introduce the difference found in 'P5 into the second memory,
File address mc and digit address n of the second memory. Op7. ,, Transfer the difference data determined by ACC to the second memory specified in P.6 by exchange.

(Type, 6) PI...Specify the temporary save memory address in P5 using file address mB and digit address n (.

P2...Subtraction is a method of adding the complement of the subtracted number to the minuend,
Since there is no lower digit, there is no borrow and F/Fc is set.

P3...Introduce a subtractive number N to ACC.

P4...Processing for taking the subtractive number (7) 15's complement,
Find the complement of ACC.

P5: In preparation for operation with the contents of register X, the contents of ACC are introduced into the memory specified by Pl.

P6: Transfer the contents of register X in exchange with ACC. When this process is completed, the memory contains the 15's complement of the subtracted number, and the ACC contains the contents of X.

Pl...ACC+M+C is 2 in the process equivalent to X-N
The actual subtraction result of the decimal is found in ACC.

P8...Exchanges the contents of ACC and the contents of X, transfers the value of X-N to address mB
and digit address nc.

P2... Since this is a subtraction of 1 digits, and the complement of the subtrahend is added to the minuend, F/FC is set.

P3: Introduce minuend to ACC.

P4...Exchange memory contents (subtraction) and ACC,
Also, in preparation for P7 processing, the memory file address is mB.
Leave it as is.

P5...The complement of ACC is determined by the process of taking the 15's complement of the subtracted number of ACC.

P6...If there is no borrow from the lower digits, subtraction is replaced by a process of adding the 16's complement of the subtrahend and the minuend. Assuming that C=1 is a state in which there is no borrow, N-M is essentially performed with ACC+C+M, and the difference is found in ACc.

Pl... Since the memory file address remains in mB at P4, the difference in ACC is stored in the original memory and Type 7 is completed.

(Type 8) N Ml→M2PI...File address mB and digit address n of the memory to be processed. Specify.

P2... ACC the content corresponding to the subtraction specified by PI
to be introduced. The file address mC of the second memory is specified in preparation for the process of P5.

P3...The complement of ACC is determined by the process of taking the 15's complement of the subtracted number of ACC.

P4...The contents of the operand are the minuend plus 1,
Set it to . This subtraction is for one digit, and is replaced by the process of adding the complement of the subtracted number and the minuend. The general complement addition in the absence of borrows is T
As in y p 67 (ACC 1C 1M, C=1,
and processed. Since there is no C in the ADI instruction, ACC+1 is performed in advance for processing. This allows N-
The result of subtracting T from M and pe8 is found in ACC.

P5...Transfers the difference data obtained in P4 to the second memory specified in P2.

Pcm (when y is 11) Binary number 0001 (=
1) will be introduced. - p', - (when M -1) Binary number 1111 (=
15) will be introduced.

P2... Processing memory file address m,
and digit address n. Specify.

P3: Adds the contents of the memory specified in P2 and the contents introduced in ACC by Pl or pH, and introduces the sum into ACC. In the case of PI, it becomes ACC+1, and in the case of pfl, it becomes essentially ACC-1.

P4...The result obtained by ACC is transferred to the original memory and Type 69 is completed.

(Type 1) X+W-,
, specified by .

P2: When adding the first digit, there is no carry processing from the lower digits, so the carry F/FC is reset.

P3...AC the contents of the desired digit in the first memory.
In addition to introducing mB of the second memory into the file address in preparation for addition with the contents of the second memory in P4.
Please specify.

P4...Add 6 to the contents of the desired digit in the first memory introduced into ACC, and add 1 to the next digit when adding in P5.
Used to determine the presence or absence of a 0-decimal digit.

P5...The AC is what is corrected by 6 in the first memory at P4.
The contents of this ACC and the contents of the same digit in the second memory designated by P3 are added by pure binary addition, and the result is reintroduced into the ACC. If a carry occurs in the addition of the 4th bit of this pure binary addition, P6 is skipped and Pl
Proceed to. The fact that the addition of the 4th bit results in a carry is lO
It means that progress was made.

When a decimal digit is obtained by adding P6...P5, '
The 6 added in P4 is subtracted in this step to return it to the original value. Addition of 1o is the same as subtraction of 6.

Pl...When the sum of one digit in decimal 10 found in ACC is transferred to the second memory by exchange, the digit address is increased in preparation for the addition of the next digit of the common number, and the first memory is transferred to the file address mA. Specify with . By predetermining the final digit to be added as nl, BL:nl is obtained when all digits in the first and second memories have been added, so the next P8 is skipped and "ype" Finish the process b P8... Specify program address P3, BL=
The commands from R to P7 are repeated until n1 is reached, and decimal addition is performed for each summer digit.

(Type 2) x-W-4x ÷ Pl...The first digit of the first memory to be processed is specified by the file address mA and digit address rH.

P2 --- Subtraction is a method of adding the subtrahend M number to the minuend,
In the subtraction of the first digit, there is no polling process from the lower digits, so F/FC is set.

P3...Introduces the contents of the desired digit subtraction in the first memory into the ACC, and specifies the second memory file address mB in preparation for processing with the second memory at P5°Pl.

P4: Processing for taking the 15's complement of the subtracted number.

The 15's complement is found in ACC.

P5...If there is no pollo from the lower digits, subtraction is replaced by adding the 16's complement of the subtrahend and the minuend, and if there is a boloni from the lower digits, it is replaced by adding the 15's complement of the subtrahend and the minuend. Replaced. Let C = 1 for the state without pollo, and A
Pure binary subtraction is executed at CC+C+M→ACC.

The occurrence of a carry as a result of the instruction execution of ADC9K means that no pollo was produced in the subtraction, so P6 is skipped and the process proceeds to Pl. Note that since the addition here is performed with the second memory designated by P3, it is essentially the second memory minus the first memory.

If a carry does not occur in the ADC8K instruction of P6...P5, the result is obtained in hexadecimal, so it is returned to a decimal number by subtracting 6 (equivalent to adding io).

Pl...The difference between the second memory and the first memory found in ACC is transferred by exchanging it with the contents of the second memory. In preparation for subtracting the next digit, erase one digit address, and then specify the first memory as the file address mA!.Prepare the final digit to be subtracted.
By determining it as ``y'', BL-nl is obtained when the subtraction between the second memory and the first memory is completed for all digits, so the next P8 is skipped and "y
Finish the processing of pe2.

P8...Specify program address P3 and set BL=n
The commands P3 to P7 are repeated until the value becomes 1, and the decimal subtraction is incremented by 1 every l digit.

1'J Shifts the contents of the desired area memory by 1 digit.

(Type 1) Right shift φ Pl...Memory file address mA to be processed
and digit address nA.

Introduce P2...0 to ACC and prepare to insert O in the most significant digit when shifted to the right.

P3...Exchanges the contents of the memory with ACC, lowers the digit address, and specifies one lower digit. The memory file address does not change in mA.

It returns to P3 again via the next P4, which means repeating XD. The 0 entered in ACC at P2 is the first ACC-M
Enters the most significant digit of the memory at , the address is down to the original most significant digit, and when you return to P3 via P4 and execute XD, the l digit lower than the 1 most significant digit is specified. , the contents of the original most significant digit in ACC are transferred one digit lower.

At this time, the contents of one digit lower than the most significant one are transferred to ACC. By predetermining the least significant digit as n2, when the above transfer is repeated up to the least significant digit, BL-n2 is satisfied, and P4 is skipped and the process ends. That is, the contents of each digit are transferred to the lower digit, and Type 1 is executed.

P4...Return to P3 to repeat XD of P3 until BL=V.

(Type 2) Left shift☆ Pl...Memory file address mA to be processed
and the lowest disk) nH.

Introduce P2...0 to ACC and prepare to put 0 in the least significant digit when shifted to the left.

P3...Exchanging the contents of memory with ACC,
Upgrade the digit address and specify the upper digit. The memory file address does not change in mA. Since it returns to P3 again via the next P4, it means a repetition of XI. The 0 you put in ACC at P2 is the first ACC-
M enters the lowest digit of the memory, and the contents of the original lowest digit are stored in ACC. When the digit address is updated in P3, and when you return to P3 via P4 and execute XI, the content of the original lowest digit in ACC is It is transferred one digit higher. At this time, the contents of one digit higher than the lowest order are transferred to ACC. By predetermining the most significant digit as nl, if the above transfer is repeated up to the most significant digit, BL=nl is satisfied, and P4 is skipped and the process ends. That is, one content per digit is transferred to the upper deshift and Type 2 is executed.

P4...Return to P3 to repeat XI of P3 until BL=V.

(Type 1) Pl... The digits of the memory area to be processed are the file address mB and the digit address n. Specify with.

Pl...Introduce 1 to the desired bit N in the memory digit specified by Pl and execute Type.

(Type 2) Pl: Specify the digits of the memory area to be processed using file address mB and digit address nc.

Pl...- of the memory digit specified by Pl
”Execute ype2.

I can do it.

(Type 1) Pl...File address mB and digit address n where 1 pit of desired conditional F/F exists
. Specify.

Pl...Bit specified by N in the memory area specified by Pl (corresponds to the desired conditional F/F)
If the content is months, skip P3 and proceed to P4 to execute operation OPI. If the content of the desired bit is 0, the process advances to the next step P3.

P3...Conditional F/F by Pl judge
When is O, in order to execute operation OP2, specify the program step as Pn.OPl...The memory area containing the content to be judged is specified by file address mB, digit address n,
Specify with.

Pl...Introduces the memory contents specified by PI into ACC.

P3...ACC contents and predetermined numerical value N
If they are equal, skip P4 and proceed to P5 to execute operation OPI. If the contents of Acc and N are not equal to Φ, proceed to P4.

P4: Specifies program address (step) Pn and jumps to Pn. Operation O at P'n
Execute P2. ′ Pi...The area of memory to be judged is file 1
The address is specified by mB, and the first digit address is specified by nE.

P2...Introduce the numerical value N to be compared into ACC.

P3: Compare the contents of the comparison value N of ACC with the desired digit in the desired area of the memory, and if they match, skip P4 to compare the following digits and proceed to P5.
Proceed to. If it does not match, proceed to P4. P4...If there is a mismatch in P3, specify the program address (step) to Pn and jump to execute the operation immediately. P5-... Add 1 to the digit address. to update the digit address.

This process is for sequentially judging multiple digits in memory. By predetermining the last digit address of the memory to be judged as a leap, the above comparison is repeated for a desired number of digits. If a mismatch occurs during the process, go through P4 and proceed to operation O.
P2 is executed, but if the matches continue until BL=V, P6 is skipped and the process proceeds to P1, where operation OPI is executed.

Pl...When a match continues at P5, return to P3 and repeat the judgment.

change.

Pl...Specifies the file address mB and digit address nC of the memory to be judged.

P2...Introduces the contents of memory 1 specified by Pl into ACC. 5 P3...If the numerical value to be compared with the memory contents is N, specify the numerical value 16-N by the operand, add the contents and the memoria contents of ACC, and obtain ACC. In this addition, the 4th bit carry comes out, which means 2
This means that the base addition result exceeds 16.

In other words, M+(16-N)>16, so 1. This is M-N, so proceed to P4.

P4...When it is not MΣN, specify the program address to Pn in this step, jump, and execute operation OP2 at Pn.

Pl...Specifies the file address mB and digit address n (of the memory to be judged).

P2...Introduces the memory contents specified by Pl into ACC.

P3... Let N be the numerical value to be compared with the contents of the memory.

Specify the numerical value 15-N in yelp and its contents and A
Add the memory contents of CC and obtain ACC. The fact that a carry appears in the fourth bit in this addition means that the binary addition result exceeds 16. In other words, M0(15-
N)Σ16, which means MΣN+1. That is, M>N. In this case, this instruction skips P4 and proceeds to P5 to execute operation OPI.

If there is no carry, it means that M>N does not occur and the process proceeds to P4.

P4...When M>N is not specified, specify the program address (step) to PH in this step and jump,
Execute operation OP2 with Pn.

(Type 1) Pl...: The number of pits in W, 10, is input to ACC in order to reset the entire contents of buffer register W that generates a digit selection signal for time-divisionally displaying the display.

P2...After shifting the entire contents of register W to the right by l bits,
Input 0 to the first bit. By repeating this through P4 until C4=1 at P3, the entire contents of W are reset.

P3... By setting the operand IA to 1111, AC+1111 is performed, essentially performing ACC-1. Since 01 is put in ACC in Pl, by repeating this number of times, the 4th bit carry C4 becomes 0 only when adding with the next 1111 when ACC=O, so only in this case proceed to P4, otherwise Skip to P5.

P4...AC+11 t When the fourth bit carry C4=0 at t, the entire contents of W have been set to 0, so the preprocessing is completed and the first address P6 of the display step of the memory is set.
jump.

P5-...4th bit carry C at ACC+1111
When 4=1, the process of setting all contents of W to 0 has not yet been completed, so the process returns to P2 and repeats the process of zeroing W.

P6: Specify the first digit of the memory area containing the content to be displayed using the file address mA and digit address nA.

P7: After shifting the contents of the register W that generates the display digit selection signal by one pit to the right, 1 is placed in the first pit. This prepares for supplying a digit selection signal to the first digit display.

Ps...AC the contents of the desired area of the specified memory
Enter in C. Memory file address does not change mA
It is. Also, in preparation for processing the next digit, the digit address is down.

Ps...Transfers the contents of the memory stored in ACC to the output buffer register F. The contents of register F are input to segment decoder SD, which generates a segment display signal.

PIO...In order to output the contents of register W to the outside as a display signal, put 1 in Fundisilonal F/PNP,
Set state. With this, the memory contents processed at f9 are displayed on the first digit display.

pH: Input the count initial value n2 for determining the display time for one digit into ACC.

cormorant. When the ACC becomes 0, the process is skipped to Pi3, and when the content of ACC is not 0 (c4-1), the process is skipped to Pi4 and this process is repeated.

Pi3...desired display time. is processed by the content count of ACC of Pi2, and when the count is completed, it jumps to I"ts via Pi3. This count time becomes the month digit display time.

Pi4...Until the desired display time elapses, Pi2 skips Pi3, proceeds to Pi4, then jumps to Pi2 again, and repeats this process.

Pi5...Resets NP and stops supplying the digit selection signal to the display. Next, until NP is set again in PIG, it is applied to prevent overlapping display by adjacent digit signals of display.

1'ia...In preparation for displaying the next digit, shift the register W by 1 bit to the right, put 0 in the first pit, essentially shift the 1 input in P7 to the 1-bit lower digit, and then Prepare for digit selection.

PIT: Checks whether the last digit of the memory to be displayed has been completed.Since BL-1 has been performed in the Ps processing, it is checked whether the value nH of the last digit -1 has been reached.

Pi8...Ps when the final digit has not arrived
Returns to 0 and displays the next digit.0 P19...For example, if the flag F/FF A is used as the condition for ending the display, FA=1, skipping P2O and completing the series of display processing.

If FA=0 in P2O...Pi9, the process jumps to Ps to repeat the display process again from the first digit.

~7 (Type 2) Pi... In order to reset the entire contents of the buffer register W that generates the digit 4 selection signal for time-divisionally displaying the display, the number of bits n1 of W is input to ACC.

P2...After shifting the entire contents of Lujistar W by 1 bit to the right,
Enter 0 in the first pit. By repeating this through P4 until C4-1 is reached at Ps, the entire contents of W are reset.

P3... By setting the operand mA to 1111, AC+1111 is made, and nl is put in ACC in P1, which essentially performs ACC-1, so by repeating this number of times, the next 1111 becomes ACC=0. Since the fourth bit carry C4 becomes 0 only when adding
Only in this case, proceed to P4, otherwise skip to P5.

P4...4th bit carry C at ACC+1111
When it is 4-0, it means that all contents of W have been set to 0, so the preprocessing is finished, and the first address P6 of the display step of the memory is
Hejyump.

P5-...4th bit carry C at ACC+1111
When 4=1, the process of setting all contents of W to 0 has not yet been completed, so the process returns to P2 and repeats the process of setting W to 0. - P6: Specify the upper 4 bits of the first digit of the memory area containing the content to be displayed using file address m and digit address nA.

P7...AC the contents of the desired area of the specified memory
The 0 memory file address input to C remains mA.
It is. Also, lower the digit address and specify the lower 4 bits.

P8: Transfers the contents of ACC, ie, the upper 4 bits, to temporary register X.

P9...AC the contents of the desired area of the specified memory
CK input 0 memory file address is unchanged mA
It is. Also, lower the digit address and specify the upper 4 bits of the -next digit.

PIO...The contents of ACC are stored in stack register SAK.

Transfer the contents of temporary register X to stack register SX
to be introduced.

pH: After shifting the contents of the register W that generates the display digit selection signal by 1 bit to the right, 1 is put into the 11th bit.0 This prepares for supplying the 1st digit selection signal.

PI3... Conditional F/FNpH? for outputting the contents of register W as a display signal to the outside? : Insert 1 to set state. With this, pl in the display type of the first digit
Display the memory contents processed in o.

Pts...Input to the count initial value n2t-Acc for determining the display time for one digit.

PI3: Performs ACC-1 substantially in the same way as P3. When ACC becomes 0, skip to Pts, and when ACC\0 (when C4=1), skip to Pts and repeat this process.

pts... Desired display time k P Processes by counting the contents of ACC in 14, and when the counting is completed, jumps to P17 via PI3. This count time becomes the one-digit display time.

PI3...Until the desired display time elapses, skip from PI3 to Pls', proceed to PI3, and return to PI3.
Jump to and repeat this.

PI3...Npt! J is set and the supply of the digit selection signal to the display is stopped.Until Np is set again in the 0th PIO, the adjacent digit signal of the display is applied to prevent overlapping display.

PI3...In preparation for displaying the next digit, shift the register Wll bit to the right and put 0 in the first bit, effectively setting it to 1.
Shift the 1 input in P7 to the lower bit bit.

PI3... Checks whether the final digit of the memory to be displayed has been completed. Since Bt 1 has been done in the processing of P9, check whether the final digit has reached the value nE of -1. 0p2o... Final If no digit has arrived, the process returns to P7 to display the next digit. 006J Determine the type of suppressed key switch.

↓ oP3z Pl9... After displaying the contents of all digits of register W - Set flag F/F F Ck, key signal 11~
IK all In.

P2O... If any of the keys connected to the key KN1 is pressed, jumps to P3'0.

P22-P27...For each of the keys KN2-KF2, it is judged whether any of the connected keys has been pressed, and if it has not been pressed, the next step is skipped.

- If pressed, jump to P30.

P2O...When no key is pressed, F
/FF Reset Ct↑ and finish key press check.

P2O...P6 jump and continue displaying again.

P2O... At the step that comes when a key is pressed - First key strobe signal 1. For generation, the memory digit address is placed in the first state nlK.

P31...Judges whether the key input KNIKgl key strobe signal II is input, and if it is not input, skips to P33.

P32...The first key strobe signal 11 is input to the key KNI, and at 9 o'clock, the type of key is determined and the PAK
Jump and perform the following control corresponding to this determined key.

After completing the key control, the display jumps directly to Pl to start displaying. (Example of steps for Pz to jump to P1) P33~pas...First key strobe signal! The keys connected to the IK are sequentially determined, and if a desired key is pressed, the program jumps to PR%PD and performs control corresponding to that key.

P39: When the key connected to the first key strobe signal ItK is not pressed, the memory digit address is activated to generate the second key strobe signal.

P41~... Generates a desired key strobe signal, judges KNI~KF2i in sequence, determines the type of pressed key, and jumps to a desired step to control the pressed key.

PA~... Control step px for the first key...
- After the first key control is completed, return to Pl and resume display.

The above is an explanation of the main processing operations of the CPU device.

Next, an example of the display operation of a computer capable of implementing the display method of the present invention will be explained based on the flowchart of FIG.

In the figure, nl is a step in which all operations programmed by the operator are executed. n2 is a step for determining whether the state is in the Hart state, and if the state is not in the Hart state, the nt;:n2e repetitive operation is executed. Here, the normal state is a state in which calculations are temporarily stopped until data is input at a step during program execution where data is input from an external source. If it becomes a Hart state, n2
→n3, and input a certain value to the Nlk counter CO. Counter CO is constituted by a part of RAM.

Then, in step n4, the content MX2i of the calculation result (intermediate result) at that time is displayed. The contents of counter CO is 0 at n5.
If it is CoI2, step n
Proceed to step 6 and subtract 1 from the contents of counter CO. That is,
Repeat n4→n5→n6→n4→n5→... for Nl+1 times and display MXf for a certain period of time. (e.g. 5 seconds)
After that, when the contents of the counter CO become 0, the process proceeds from n5 to n7, and the counter RK1 is added. Counter R is constituted by a part of RAM.

It is assumed that the counter R has been reset to "0" in advance. R stores the default state recovery. Next, at n8, the suppress code C8 is input into the character memory MC. Character memory MC is a register in one area of RAM, and -horn characters are stored as 8-bit codes. Also, the suppress code Cζ is a code for not displaying anything on the display, for example, “111
11111". At step n9, the code "DE" is stored in the first digit of the character memory MC. At 6" IO, the contents of the program counter PL in the ROM plus 1 are stored in the program stack register SP. (
(See instruction code A54) This is a return instruction RIT (instruction code shop 55) which will be described later.
This is for specifying the return destination in ``Refer to ``. Next, proceed to step "10" 26 and set a constant value N2 'kRO
The contents of the character memory MC are displayed at 0n27 when the counter COK in M is input. At step n28, it is determined whether the contents of the counter Co have become 0 or not. If it is CoI2, the process advances to step n29, where 1 is subtracted from the contents of the counter CO. At n30, it is determined whether or not there is key power, and if the key is not operated, proceed as n3(1"n27. That is, "27→"28-n2'J'n3(1'n27t'N
Repeat 2+1 times and display for a certain period of time. After displaying for a certain period of time, n
2B→n31 (!: Proceeds, and the contents of the character memory MC are shifted to the left by one digit on the display. At step n3□, it is determined whether the conditional F/FA (part of RAM (2)) is in the set state or reset state. F/F A is 1 after all instruction data is stored in character memory MC.
It is set by cn35, and it is determined whether the display of - data (FIG. 2(b) to (f)) has been completed.

In this case, since F/F A is in the reset state, n32
→ Proceed to n33 and return command (RIT) K! Proceed to restep nll. The nil step is nl. This is the step corresponding to the contents of the program counter Pt in the ROM stored by the TML instruction.
z6″n279n2B″nz7″n30→n27→n2
8...→nat→n32→n33 to finish displaying "de" as shown in Figure 2), and nil→n12→n26→n2
7 n28 ″”29 n-1130-+2127″n
2g=n31 n3□→n33, "day" is displayed as shown in FIG. 2(c).

From then on, %n15°n 16″n 26″n27n
28 n29″n30″”27″”28″131″n3
2"Display "data" with na3O. After that, proceed from n33 to n17, store the step to return by RIT (return instruction), proceed by n17→n38, and determine the contents of counter R.

When R=1, that is, when R=1 at n7 in the initial default state, the process proceeds from n38 to n44, and the code of rAJ is stored in the first digit of the character memory MC. Then, proceed as n44 → n45 → n18 and return with a return command at nts Step n19 After storing "t", Step n2
Proceed to step 6. Therefore, similarly n44→n45→nts″n
26″n27″n28″n2g″n30°n27°n2
Display of "data A" is executed in steps B→n3 and →n32→n33.

As described above, by shifting the display content stored in the character memory, storing the newly displayed character in the first digit, and displaying the content of the character memory, it is possible to move from Figure 2 (b) to (f ) is displayed. Then, as shown in FIG. 2(f), after finishing the display, the process proceeds to step n35 by the return command in n33. In n35, the conditional F/F A 75" is set, and in n36, it is set to the first digit of the character memory MC. A suppress code C5 is stored. This suppress code CS is used to distinguish between display contents and display contents. In step n37, all digits of character memory MC are set to suppress code C3'.
(+- Determine whether it is remembered. (MC=Cs
) This is so that when the display cycles and a certain display is shifted and disappears completely from the edge of the display, the beginning of the same display content begins to be displayed. In this case, all digits are not suppressed codes, so proceed from n37 to n26 and proceed to Figure 2 (
(b))). After that, the content of the character memory is shifted with nat, and the suppress code is stored with n36, so the displayed content disappears from the left end of the display section, and as shown in Figure 2 (i), all digits of the character memory are filled with the suppress code. If so, the display advances in the order of n36→n37→n and is repeated. In other words, the instruction "Data A fillet" is repeated.

Here, since the operator has programmed the calculation to be performed in step n1, he inputs the numerical value corresponding to data A using the keys. Therefore, it is determined in step n30 that there is a key input, the process returns to n3o→nl, and the calculation is restarted at nl based on the numerical value of the input key input.

After that, when it becomes Hart state again, it progresses from n2 to n3,
As in the case of the first Hart state, n4 is displayed for a certain period of time, and 151: is added to the counter R at n7. In this case, R=2. From then on, the process proceeds in the same way as the first Halt state until n17, but since R=2, n17→na
Proceed as s → n39 → n43, and the next data to be input is B.
In order to indicate this, the code of B is stored in the character memory MC1 at n43. Therefore, in the second Halt state, the display will be "r7" - 139 IREYO". Similarly, when the third HART state is reached, "Data C fillet" is displayed, and when the fourth HART state is entered, "Data D fillet" is displayed.

Ru. Conditional F/F B (RA
A part of M) is reset, and at nb, the closest part of the character memory MC is shifted to the left by 4 bits. At nc, a judgment of 7 rip 70 tug B is made and the process proceeds to nd. F/FB is set at nd, character memory MC is again shifted to the left by 4 bits at nb, and this subroutine ends with the determination of the next F/FB.

Since the code for one character in the character memory MC is stored in 8 bits, the shift for one character is performed by performing two 4-bit shifts. Each process in the flowcharts of FIGS. 6 and 7 is described above. The process can be executed based on the contents of each process list of the friend CPU device.

Here, Table 8 is a table showing the relationship between the processing contents of the CPU device and each step for executing the flowchart shown in FIG. It corresponds to each.

As shown in Table 8 and above, each step in the flowchart of FIG. 6 is achieved by executing the processing content corresponding to the processing list number of the CPU device shown in Table 3. Note that step n1. n 101 n12 + n14In1
6-11B1 n20'l n221 n24+ n3
31 n45 can be easily understood from the above description of the CPU device.

Next, the relationship between each step and the processing list number of the CPU device when performing the left shift operation of the memory character MC in FIG. 7 is shown in the table below.

Table 4 By processing each step as described above, M(left shift operation 't-) can be executed.

According to the present invention, display control of an electronic calculator or the like can be performed using the CPU 1, which is a device that decodes and executes instruction commands.

As explained above, according to the display method of the electronic device of the present invention, the display character contents are cycled, and after a certain display content is displayed running and disappears from the edge of the display, the beginning of the display content is displayed again. Because of this, the beginning of the next display content is not displayed until one display content disappears from the end, making it possible to obtain a display system in which the display divisions are clear and there is no misreading.

[Brief explanation of drawings]

Fig. 1 is an external view illustrating an example of a program computer equipped with the display method of the present invention, Fig. 2 is a diagram for explaining the display state of the computer, and Fig. 3 is an example showing the main parts of the computer. The block diagram of FIG. 4 is a logic circuit diagram of an example of the CPU device of the same computer, and includes FIGS. 4A to 4D. Fifth
The figure is a diagram illustrating a circuit equivalent to the CPU device in Figure 4,
FIG. 6 is a flowchart for explaining the display method of the computer, and FIG. 7 is a 70-chart for explaining the left shift operation of the MC. In the figure, l: display section, 2: display section, 8: key human power device, 4
: Central processing unit (CPU), 5: Character generator (CRG), 6: Display body, 7: Digit selection signal, 8: Segment signal, RAM: Random access memory, ROM: Read-only Φ memory, ACC: accumulator. Agent Patent attorney Aihiko Fuku (and 2 others) 5

Claims (1)

[Claims] 1. In an electronic device having a display body capable of displaying a plurality of characters, and in which character content is displayed running on the display body, the predetermined character content is displayed running. 1. A display method for an electronic device, comprising circulation means for circulating the character content so that the beginning of the character content is displayed on the display body again after the character content has completely disappeared from the edge of the display body.