JPS5890259A - Voice information processor - Google Patents

Abstract

PURPOSE:To facilitate the hearing of a series of words which are produced with operation of keys, by producing the keys operated precedently in voices and in response to the operation of a specific key when a prescribed key is operated. CONSTITUTION:A memory M1 is incorporated into a microprocessor CPU of a computer, and key input device KEY is connected to the terminals KF1 and KF2 of the CPU. A voice synthesizing circuit VCC is connected to the outputs of stack registers SA and SX of the CPU as well as to the output FB of a flag FF. At the same time, the electrode of a display matter DSP is connected to the terminals SD and W of the CPU. Thus a voice information processor is obtained to be incorporated into the computer. When the key V of the device KEY is operated, the contents of the keys operated precedently are delivered out of the circuit VCC. When the generation of the output of the circuit VCC is over, the confirming signal S2 is fed to the CPU from the circuit VCC. Then the key input information are produced with discrimination. Thus the hearing is facilitated for a series of words which are produced by operating keys.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an audio information processing device that allows a computer to perform effective information processing using audio, for example.

<Prior art> For example, when using speech synthesis technology to operate a key on an electronic desktop calculator, perform a desired operation corresponding to that key, and obtain the result of the operation, the standard method is The function that can be used is that when the ■ key is pressed, the corresponding sound is output.

■When the calculation is completed, the answer is automatically output as voice.

etc.

Automatically outputting the answers aloud is suitable for transcription, etc.

For example, when one person performs calculations and another transcribes them, the keys are pressed continuously, so it is especially important to search for the answer and then input data using the numerical keys for the next calculation. When doing so, both the answer and the input key sound are numerical data, so it may be difficult to tell where the key input starts.

Also, for example, when A■B■ is set, the value B is placed,
There was a problem in that when the equal key ■ was pressed, the answer was immediately obtained, making it difficult to distinguish between the answer and the numerical value B.

Also, when calculating 125X670, for example, if you interrupt the calculation midway through, you may forget whether you pressed the ward key before, or you may not be able to confirm whether you pressed the ward key or not.
If you mistakenly thought that you had pressed the ward key when you had not pressed it and pressed 670, the result would be 125670, resulting in a wrong calculation.

<Object of the invention> The object of the present invention is to solve the above problems,
It is an object of the present invention to provide a voice information processing device that allows a computer to perform effective information processing using voice, for example.

Another object is to provide an audio information processing device that can distinguish between key input information and processing information (for example, calculation results).

Another purpose is to insert specific words after the answer in order to differentiate between them, and to express the answer as a series of words to make it easier to hear and to eliminate unnaturalness. For example, ■
After pressing a key, words such as ``Answer'' or ``Answer is'' are appended and the data is output.

Another purpose is to generate the previously operated key by voice in response to the operation of a specific key when a desired key is operated;
It is an object of the present invention to provide a voice information processing device that can confirm the previously operated key.

Another purpose is to perform key lead-in by determining the state before key operation.

Another purpose is that audio equipment, such as audio calculators, can output the necessary information both visually and audibly, allowing for vast improvements in usability such as transcription and checking.
In order to increase the expressive power, it is necessary to directly increase the size of the display and increase the expressive part, but in the case of voice, it can be implemented as an LSI, and a slight increase in circuits does not change the size or cost of the device. The goal is to provide the following.

Other objects and features will become apparent based on the following description of the embodiments and in conjunction with the drawings.

<Description of Embodiment> FIG. 1 is a block diagram showing an embodiment in which the audio information processing device of the present invention is employed in a computer.

In the figure, the CPU is a microprocessor, the specific configuration of which is shown in FIG. 2, and its operation and contents will be described in detail later.

The DSP is a display body, with digit selection electrodes connected to the W terminal of the CPU, and segment electrodes connected to the SD terminal of the CPU, for dynamic display. In other words, memory M1 (RA
Display the contents of M). The key input device KEY is connected to one terminal of the CPU and terminals KN1, KN2, KF1, and KF2. In the key input device KEY, the ■ key is a key for outputting the contents of the previously pressed key in voice. The contents of memory M1 are displayed and audio output is also performed, and the data for audio output is stored in stack register S.
It is derived from the X and SA outputs. VCC is a speech synthesis circuit (see FIG. 4), which receives words to be uttered from the stack registers SX and SA. The timing of acceptance is determined by the S0 input signal, and the S0 input is connected to the output of a flag flip-flop (F/F) FB of the CPU.

A confirmation signal S2 indicating that the words have been uttered is generated from VCC, and the CPU accepts this from the α input and uses it for control.

FIG. 2 is a concrete logic circuit configuration diagram of the microprocessor CPU, and FIG. 3 includes FIGS. 2A to 2D, and FIG. 2 is obtained by combining these A to D.

FIG. 3 is a diagram showing a circuit equivalent to the circuit of FIGS. 2A-D.

The circuit configuration of the microprocessor CPU will be described below.

(CPU circuit configuration) RAM is random access memory with 4 inputs and outputs.
This is done bit by bit, and by specifying the entire digit address and file address, the desired digit content can be input and output. BL is a digit address counter of the memory RAM, DC1 is a digit address recorder of the memory RAM, BM is a file address counter of the memory RAM, DC2 is a file address decoder of the memory RAM, and AD1 is an adder, to which a control instruction (14) is given. When (14) is not given, it works as a subtracter, and when (14) is not given, it works as an adder. AD2 is an adder, G1 is an adder/subtracter AD1, and one input of the value is 1 or the operand I.
A control command (15
) is given, outputs I, and when (16) is given, outputs IA. G2 is memory digit address counter BL
When the input gate is (10), the output of the adder/subtractor AD is
When (11), operand IA is output, and when (12), operand IB is output. G3 is a gate for supplying either the numerical value 1 or the operand IA to one input of the adder/subtractor AD2, and outputs the numerical value 1 when the value is ■, and the operand 1A when the value is ■.

G4 is the input gate of memory file address BM,
When (2), the output of the adder AD2 is output, when (2), the operand IA is output, and when (2), the contents of the accumulator ACC are output. G
5 is a file selection gate of the memory RAM, and DC3 is an operand IA decoder that decodes operand IA.
A signal specifying a desired memory bit is input to gate G6. G6 is the input gate of the memory RAM, and when the control command ■ is given, it inputs a binary number 1 to the desired bit of the memory specified by the operand decoder DC3, and when it is ■, it inputs a binary number 1 to the desired bit of the memory specified by DC3. It has a built-in circuit that inputs a binary number 0, and also uses ■ to input the accumulator ACC.
Output the contents of. ROM is a read-only memory, and PL is a program counter that specifies a desired step in the read-only memory ROM. DC4 is the read-only memory ROM step access decoder, G7 is the read-only memory ROM output gate, and the judge flip-flop (F/F) J
When is set, transmission of the ROM output to the instruction decoder DC5 is cut off. DC5 is an instruction decoder that decodes the instruction code from the ROM.The instruction code in the ROM is divided into an operation code part IO and an operand part I.
A and 1B, the operation code is decoded, and one of control instructions 1 to 61 is generated in accordance with the operation code. It also includes a built-in circuit that determines that the opcode is accompanied by an operand and outputs the operand IA or 1B as is at that time. AD3 is an adder that adds the value 1 to the contents of the program counter Pl to count up.

G8 is an input gate of the program counter PL, which outputs the operand 1A when it is 20, and transmits the contents of the program stack register SP when it is 61.

The output of adder AD3 is not transmitted during processing of gates 20 and 61 and during processing of 60 for gate G39. 20, 61, 6
If it is other than 0, the AD3 output is transmitted and 1 is automatically added to the contents of the program counter PL. FC is flag F/F,
G9 is the input gate of flag F/FFC, 2 when it is 17
When the number is 18, the binary number is 0, and the flag F/
This is for inputting to the FFC. G is the key signal generation gate, and the flag F/FFC is in the reset state (0)
In this case, the desired output of the memory digit address decoder DC1 is output as is, and when the flag F/FFC is set to 1, regardless of the DC output, ■1 to 1n
It has a built-in circuit that sets the outputs to 1 all at once. ACC is an accumulator consisting of 4 bits, X is a temporary (temporary storage) register consisting of 4 bits, G11 is an input gate of temporary register In this case, the contents of stack register SX are transmitted.

AD4 is an adder, which is used to perform binary addition of the contents of the accumulator ACC and other data.

During binary addition, if a carry comes out with the help of the 4th pit, C.
Set 4 outputs to 1. 1 carry F/F in C, G12 is the input gate of the carry F/F, if the 4th bit carry C4 is 1 when the control command ■ is generated, the carry F/F
It has a built-in circuit that inputs 1 to C, and inputs 0 to C if C4 is O. When it is 21, put 1 in C, and when it is 22, put 0 in C.
This is for inputting. G13 is a carry C for performing binary addition including carry in adder AD4.
When the input gate is 25, it is transmitted to the output adder AD4 of the carry F/FC. G14 is an input gate of adder AD4, which transmits the output of the memory RAM when it is 23 and the operand IA when it is 24. F is an output buffer register consisting of 4 bits, G15 is the input gate of the output buffer register F, and when 31, the accumulator ACC
It transmits the contents of and inputs it to F. SD is an output decoder for decoding the contents of the output buffer register F and converting it into display segment signals SS1 to SSn.

W is an output buffer register, and SHC is for shifting all bit contents of the output buffer register W by one bit to the right at once, and operates when 32 or 33 occurs. This is a shift circuit for the output buffer register W. G16 is an input gate of the output buffer register W, and when it is 32, it inputs 1 to the first pin of W, and when it is 33, it inputs 0 to the first bit of W. It is assumed that the output buffer shift circuit SHC operates immediately before inputting 1 or 0 to the input signal, and inputs the output buffer after shifting. NP is the output control flag F/
F and G17 are input gates of the output control flag F/FNP, and when the flag is 34, 1 is input, and when it is 35, 0 is input. G18 is an output control gate of the buffer register W, and is used to output the outputs of each bit of W at the same time only when the flag F/FNP is set (1). J is judge F/F, IV1~IV
4 is an inverter circuit, and G19 is an input gate of the judge F/FJ, which is used to transmit the state of the input KN1 to J at the time of 36. However, since it is passed through the inverter IV1, J=1 when KN1=I.

G20 is an input gate of judge F/FJ, and transmits the state of input KN2 to J at 37. However, since it is passed through the inverter IV2, J=1 when KN2=0. G21 is the input gate of judge F/FJ, and is used to transmit the state of input KF1 to J at the time of 38. However, since it is via inverter IV3, when KF1=0, J
=I. G22 is the input gate of judge F/FJ, and is for transmitting the state of input KF2 to J at the time of 39. However, since it is via inverter ■V4, KF2
When , J=1. G23 is the input gate of judge F/FJ, and is used to transmit the state of input AK to J at 40.

When AK=1, J=1. G24 is Judge F/FJ
This is an input gate for transmitting the state of input TAB to J at the time of 41. When TAB=1, J=l. G2
5 is a gate for setting judge F/FJ, and is for inputting I to J at 42. V1 is a comparison circuit which compares the contents of the memory digit address counter BL with predetermined data and generates an output 1 if they match, and the circuit operates when 43 or 44 is generated. Data to be compared is output from gate G26. G26 is a comparison input gate to the comparison circuit V1, and the comparison value n1 corresponds to a high-side specific address value often used for controlling the memory RAM. When the value is 43, n1 is outputted as a comparison value, and when it is 44, n2 is outputted as a comparison value. G27 is the input gate of judge F/FJ, when the content of carry F/FC is 1 when it is 45,
Enter 1 in J. DC6 is an operand IA decoder which decodes operand IA and uses it to judge whether the contents of a desired bit in the memory RAM is 1 or not. G28 is a gate that transmits the bit contents specified by the operand decoder DC6 of the memory RAM to the judge F/FJ;
It works when . When the designated bit of RAM is 1, J=1. V2 is a comparator circuit, accumulator AC
It judges whether the contents of C and the contents of operand IA are equal, and when they are equal, output 1 is generated. It works at 47. V3 is a comparison circuit which judges whether the contents of the memory digit address counter BL and the contents of the operand IA are equal, and generates an output 1 when they are equal. 48
It works when .

V4 is a comparison circuit that judges whether the contents of the accumulator ACC and the contents of the memory RAM are equal, and generates an output 1 when they are equal. G29 is a transmission gate for the addition fourth bit carry C4 to the judge F/FJ, and when it is 50, C4 is transmitted to the F/FJ.

At C4, J=I.

FA is a flag flip-flop, G31 is a flag F
/FFA input gate outputs 1 at 52 and 0 at 53. G32 is the input gate of judge F/FJ, and when flag F/FA is 1, F/FJ is set (1
)do.

FB is a flag F/F, and G33 is an input gate of the flag F/FFB, which outputs 1 at 55 and 0 at 56. G34 is the input gate of judge F/FJ, which transmits the contents of flag F/FFB to F/FJ.

It operates when 54. G35 is an input gate of the judge F/FJ, which transmits the entire contents of input β, and is operated by 19.

When β=1, J=1. G36 is accumulator AC
When the input gate of C is 26, the output of the adder AD4 is transmitted, and when it is 27, the contents of the accumulator ACC are inverted and transmitted by the inverter TV5.

When it is 28, the contents of the memory RAM are transmitted, and when it is 13, the contents of the operand IA are transmitted. When 59, input k1
The contents of 4 bits of ~k4 are transmitted. At 59, the contents of stack register SA are transmitted.

IV5 is an inverter circuit, and SA is a stack register whose output is led out of the system. SX is a stack register whose output is led out of the system. G37 is an input gate of the stack register SA, and when it is 58, it transmits the contents of the accumulator ACC. G38 is an input gate of the stack register SX, and when it is 58, the contents of the temporary register X are transmitted. SP is a program stack register, and G39 is an input gate of the program stack register SP, which is used to input the contents of the program counter PL plus 1 by an adder AD3 into the program stack register at 60.

Next, the table below shows an example of the instruction code stored in the storage section ROM of the CPU device, the instruction name, the operation content, and the control command generated based on the instruction code.

In Table 1, A indicates an instruction code, B indicates an instruction name, C indicates content, and D indicates a CPU control command signal.

Explanation of Table 1 (C) 1SKIP Does not execute the next program step instruction, increments only the program counter PL, and essentially skips it.

2AD Performs binary addition of the contents of accumulator ACC and the contents of memory RAM, and inputs the addition result to accumulator ACC.

3ADC accumulator ACC, memory RAM carry F/F
Perform binary addition of the contents of C and add the addition result to accumulator AC.
Enter in C.

4ADCSK Accumulator ACC, memory RAM, carry F/
Add the contents of FC in binary and add the result to accumulator A.
If the fourth bit carry C4 occurs as a result of this addition, the next program step is completely skipped.

5ADI Performs binary addition of the contents of accumulator ACC and operand I, inputs the addition result to accumulator ACC, and skips the next program step if fourth bit carry C4 occurs as a result of this addition.

6DC Operand IA is set to 1010 (decimal number 10), and A
Similar to the DI instruction, by performing binary addition of the contents of the accumulator ACC and this operand 1A, a decimal number 10 is essentially added to the contents of the accumulator ACC, and the result is input to ACC.

7SC Set carry F/FC.

(Enter I in C.) 8RC Reset the carry F/FC.

(Input 0 to C.) 9SM Deciphers the contents of operand IA and sets the desired bit in the memory specified by the operand. (Input 1.) 10RM Decodes the contents of operand IA and resets the desired bit in the memory specified by the operand. (Input 0.) 11COMA Inverts the contents of each bit of accumulator ACC and inputs 15
Take the complement of and input it to accumulator ACC.

12LDI Introduce operand IA to accumulator ACC.

13L Inputs the contents of the memory RAM into the accumulator ACC and inputs the operand IA into the file address counter BM.

14LI Loads the contents of the memory RAM into the accumulator ACC and inputs the operand IA into the memory file address counter BM. Furthermore, the memory digit address counter BL is increased. However, when the content of BL is equal to the predetermined value n1, the next program step is skipped.

15XD Exchange the contents of the memory RAM and the contents of the accumulator ACC, and input operand ■A to the memory file address counter BM. Furthermore, the memory digit address counter BL is decreased.

However, when the content of BL is equal to the predetermined value n2, the next program step is skipped.

16X Exchanges the contents of the memory RAM and the contents of the accumulator ACC, and inputs the operand TA to the memory file address counter BM.

17XI Exchanges the contents of the memory RAM and the contents of the accumulator ACC, and inputs the operand IA to the memory-file address count BM. Furthermore, the memory digit address counter BL is increased.

However, when the content of BL is equal to the predetermined value n1, the next program step is skipped.

18XD Exchanges the contents of the memory RAM and the contents of the accumulator ACC, and inputs the operand 1A to the memory-file address counter BM. Furthermore, the memory digit address counter BL is decreased.

However, when the content of BL is equal to the predetermined value n2, the next program step is skipped.

19LBLI Input to operand IA and memory digit address counter BL.

20LB Operand IA to memory file address counter B
At the same time, the operand IB is input to the memory digit address counter BL.

21ABLI Performs binary addition of the contents of memory digit address counter BL and operand IA, and stores the addition result in BL. However, when the content of BL is equal to the predetermined value n1, the next program is skipped.

22ABMI Memory - Performs binary addition of the contents of file address counter BM and operand ■A, and stores the addition result in BM.

23T Write the contents of operand IA to program step counter P.
Enter in L.

24SKC If carry F/FC is 1, skip the next program step.

25SKM Deciphers the contents of operand IA, and if the desired bit of the memory specified by the operand is 1, skips the next program step.

26SKB1 Compares the contents of the memory digit address counter BL and the operand TA, and if they are equal, skips the next program step.

27SKAI Compares the contents of accumulator ACC and operand TA, and if they are equal, skips the next program step.

28SKAM Compares the contents of the accumulator ACC with the contents of the memory RAM, and if they are equal, skips the next program step.

29SKN1 When the KN1 input is 0, skip the next program step.

30SKN2 When the KN2 input is 0, skip the next program step.

31SKF1 When the KF1 input is 0, skip the next program step.

32SKF2 When the KF2 input is 0, skip the next program step.

33SKAK When the AK input is 1, skip the next program step.

34SKTAB When TAB input is 1, skip next program step.

35SKFA When flag F/FFA is 1, skip the next program step.

36SKFB When flag F/FFB is 1, skip the next program step.

37WIS Shifts the contents of the output buffer register W to the right by 1 bit and inputs 1 to the first bit (most significant bit).

38WIR Shifts the contents of the output buffer register W by 1 bit to the right and inputs 0 to the first bit (most significant bit).

39NPS Set buffer register W output control F/FNp. (Input 0.) 40NPR Reset buffer register W output control F/FNp. (Input 0.) 41ATF Outputs the contents of accumulator ACC to buffer register F
Transfer to.

42LXA Save the contents of accumulator ACC to temporary register
to be introduced.

43SFA Contents of accumulator ACC and temporary register X
exchange the contents of

44SFA Set flag F/FFA. (Enter 1.) 45RFA Reset flag F/FFB. (Enter 0.

) 46SFB Set flag F/FFB. (Enter 1.) 47RFB Reset flag F/FFBk. (Enter 0.

) 48SFC Set the input test flag F/FFC. (Input 1.) 49RFC Reset the input test flag F/FFC. (0
Enter. ) 50SKB When input β is 1, skip the next program step.

51KTA Introduce the contents of inputs k1 to k4 into accumulator ACC.

52STPO The contents of accumulator ACC are transferred to stack register SA, and the contents of temporary register X are transferred to stack register S.
Introduce it to X.

53EXPO The contents of the accumulator ACC and the contents of the stack register SA are exchanged, and the contents of the temporary register X and the contents of the stack register SX are exchanged.

54TML Transfers the contents of program counter PL plus 1 to program stack register SP. Furthermore, operand IA is introduced into program counter PL.

55RIT Transfers the contents of the program stack register SP to the program counter PL.

Next, Table 2 shows the relationship between the opcodes and operands stored in the ROM of the CPU device.

However, IO: operation code IA, ■B: operand Here, for example, if we take the case where the output of a read-only memory ROM is 10 bits, instruction AD or COMA (see Table 1) is instruction decoder DC5. The 10-bit code is 0001011000 or 0001011111, respectively, and the control commands 23, 26 or 2 are read.
Generates 7.

On the other hand, SKBI is determined based on the fact that the upper 6 bits are 000110, and at this time, the lower 4 bits 0010 are treated as operand IA.

Furthermore, LB is determined by the fact that the upper two bits are 01, and at this time, the third to eighth bits, 001010, are treated as operand IA, and the ninth and tenth bits, II, are treated as operand IB.

An operand is a constituent part of an instruction word.
This part indicates the address where data and the next instruction are stored, and can be called the address part of the instruction.

Next, an example of the main processing operations of the above-mentioned CPU device (hereinafter referred to as a processing list) will be explained.

(Processing List) (1) Introduce the same numerical value N to a desired area of the memory RAM. (NNN→X) (2) Introduce a plurality of different predetermined numerical values into a desired area of the memory. (N1, N2, N3...→X) (
3) Transfer the contents of the desired area of memory to another desired area of memory. (X→Y) (4) Exchange the contents of the desired area of the memory with the contents of another desired area of the memory. (X←→Y) (5) Add or subtract a predetermined numerical value N to or from a desired area of the memory. (X1N) (6) Add the contents of another area to the contents of the desired area of the memory in decimal form. (X+Y) (7) Shift the contents of the memory in the desired area by one digit. (X right, X left) (8) Set or reset the 1-bit conditional F/F in the desired area of the memory.

(Fset. Freset) (9) Judge the contents of the 1-bit conditional F/F in the desired area of the memory, and change the next program address based on the judgment result.

(10) Judge whether the digit content in the desired area of the memory is a predetermined value, and change the next program step based on the judgment result.

(11) Judge whether the contents of a plurality of digits in a desired area of the memory are all equal to a predetermined value, and change the program step based on the judgment result.

(12) Judge whether the contents of the desired area of the memory are smaller than a predetermined value, and change the next program step based on the judgment result.

(13) Judge whether the contents of the desired area of the memory are larger than a predetermined value, and change the next program step based on the judgment result.

(14) Display the contents of the desired area of memory.

(15) Determine the type of pressed key switch.

A specific example of executing the processes (1) to (15) above based on the instruction code will be described below in accordance with the process list.

(Specific example of processing list) (1) Introduce the same numerical value N to a desired area of memory. (
NNN)→X) (Type I) P1: The first digit to be processed in memory is
Specify with file address mA and digit address nE.

P2: Introduce the numerical value N to ACC.

P3: Introduce the number N into the specified area of memory by exchanging the contents of memory and ACC. Since the memory file address does not change, specify mA,
The digit address is down to determine the next digit to introduce.

By predetermining the value of the final digit nA to be introduced as n2, BL=n2 when the numerical value N has been introduced into all desired areas, so the next P4 is skipped and the Type I location FI! finish.

P4: Specify the program address as P2 and repeat the LDI and XD processing until BL=v.

(Type 2) P1: Specify the digit to be processed in the memory using file address mB and digit address nC.

P2: Introduce the numerical value N to ACC.

P3: Introduce the number N into the specified area of memory by exchanging the contents of memory and ACC. In this way, the Type 2 processing is completed. The operand part of XD is necessary for the subsequent processing and is not relevant to this processing.

(Type 3) P1: Specified by the first file address mc to be processed in memory and digit address nO.

P2: Introduce the numerical value N to ACC.

P3: Introduce the number N into the specified area of memory by exchanging the contents of memory and ACC. Since the memory file address does not change, mc is specified, and the digit address is down to determine the next digit to be introduced.

P4: Checks whether the digit processed in P3 is the final digit, and if it is nB, the digit address goes down and becomes nA.
Therefore, the operand part of the SKI instruction is
By setting the number N to the final digit and proceeding to P4, the condition is satisfied and the next address P5
Skip Type 3 and end Type 3. If the conditions are not satisfied, proceed to P5.

P5: Specify the program address to P2, BL=n
Processes P2 to P4 can be repeated until A is reached.

(2) Introducing a plurality of different predetermined numerical values to the desired value in the memory. (N1, N2, N3...→X
) (Type I) An example of introducing a 4-digit numerical value N4N3N2N1 into memory is shown. (The same applies to the introduction of arbitrary digits.) P1: Specify the first digit to be processed in the memory using file address mA and digit address nE.

P2: Introduce a first constant N1 to ACC.

P3: Introduce the number N1 into the designated area of memory by exchanging the contents of memory and ACC. Since the memory file address does not change, specify mA,
The digit address is updated to determine the next digit to be introduced.

P4: Introduce a second constant N2 to ACC.

P5: Since the memory is designated as the second digit in the process of P3, the second constant N2 is introduced into the second digit of the memory by exchanging the contents of the memory and ACC.

P6 to P9: Process in the same manner as above.

(Type 2) When introducing any numerical value from O to 15 into a predetermined register P1: A numerical value N is introduced into ACC.

P2: Introduce the numerical value N contained in ACC into register X.

(Type I) P1: The first memory file address to be processed is specified by mA, and the first digit address to be processed is specified by nE.

P2: ACC the contents of the desired digit in the first memory.
At the same time, in preparation for the transfer process at P3, the file address of the second memory of the transfer destination is specified in mB.

P3: The contents of the first memory introduced into the ACC k The contents of the same digit in the second memory designated by P2 are exchanged to essentially transfer the contents of the first memory to the second memory. In order to repeat this process simultaneously, the original file address of the first memory is specified in mA.

By predetermining the value of the final digit nA to be transferred as n1, BL=n1 when all the contents of the first memory have been transferred to the second memory, so the next P4 is skipped and Type I Finish processing. Upgrade the digit address one by one until RL=v (last digit)
The file address that returns to P2 via 4 is set to mA, and the first memory is specified.

P4: Specify the program address in step P2,
Repeat commands P2 and P3 until BL=n1,
The transfer process proceeds digit by digit.

(Type 2) P1: The memory area to be processed is specified as the file address m.
Specify by A and digit address nC.

P2: The contents of the memory area specified in P1 are introduced into ACC, and the file address of the transfer destination memory is specified in mc in preparation for the transfer process in P4.

P3: Specify the digit address of the transfer destination memory. The transfer destination memory area is specified in the processes P2 and P3.

P4: The contents of ACC are essentially transferred by exchanging the memory areas specified by P2 and P3. The operand of X is not directly related to this processing.

(Type 3) P1: Specify the memory area to be processed as file address m
Specify by A and digit address nC.

P2: Extend the contents of the memory area specified in P1 to ACC.

P3: The contents of the memory introduced into ACC are stored in register
, and execute the desired Type 3 transfer process.

(4) Exchange the contents of the desired area of the memory with the contents of another desired area of the memory. (X←→Y) (Type I
) P1: Specify the file address of the first memory to be processed by mA, and specify the first digit address to be processed by nE.

P2: ACC the contents of the desired digit in the first memory.
At the same time, the file address of the second memory is specified in mB in preparation for the exchange process with the second memory in step P3.

P3: The contents of the desired digit in the first memory stored in ACC are exchanged with the contents of the same digit in the second memory specified in P2, and this process
In order to introduce the contents of the second memory transferred to the first memory into the first memory, the file address of the first memory is specified in mA.

P4: Exchange the contents of the second memory introduced into the ACC with the contents of the first memory of the same digit, and transfer the contents of the second memory to the first memory. In the processing of P2 to P4, contents are exchanged between desired digits in the memory. The designation of the first memory is continued by designating the file address mA, the digit address is increased, the next digit address is designated, and the exchange is performed for each digit in sequence.

Note that the value of the final digit nA to be exchanged is determined in advance by n.
1, the first memory and
When the contents of the second memory have been exchanged over all digits, BL=n1, so the next P5 is skipped and the Type 1 processing ends.

P5: Specify program address to P2, BL=n1
The commands P2 to P4 are repeated until the exchange process is performed one digit at a time.

(Type 2) P1: The file address of the first memory to be processed is specified by mA, and the digit address to be processed is specified by nC.

P2: ACC the contents of the desired digit in the first memory.
At the same time, the file address m of the second memory is
Specify C and prepare for content conversion.

P3: Transfer destination second memory digit address nO
and specify the memory address of the replacement destination.

P4: Exchange the contents of the first memory contained in the ACC with the contents of the second memory. At this time, in order to transfer the contents of the second memory to the ACC to the first memory, the file address of the first memory is specified again in mB.

P5: Specify the digit address nC of the first memory and determine the first memory address of the transfer destination.

P6: Exchange the contents of the second memory contained in the ACC with the contents of the first memory.

(Type 3) P1: The file address of the first memory to be processed is
A specifies the digit address to be processed, and nC specifies the digit address to be processed.

P2: Introducing the first memory contents into the ACC, and
Specify the exchange destination using the file address mC of the second memory.

P3: Exchange the contents of the first memory of ACC with the contents of the second memory specified in P2, and introduce the contents of the first memory into the second memory. In preparation for processing at P4, the first
Specify the memory using the file address mB.

P4: Exchanging the contents of the first memory and the second memory by exchanging the contents of the second memory introduced into the ACC and the contents of the first memory.

(Type 4) P1: Specify the memory area to be processed as file address m
Specify by A and digit address nC.

P2: Introduce the contents of the memory specified in P1 to ACC.

File address m in preparation for exchange with the contents of register
Keep B.

P3: Contents of memory in ACC and register X
and transfer the contents of memory to register X.

P4: By exchanging the contents of register X contained in ACC with memory, the contents of register X are substantially transferred to memory and Type 4 is executed.

(5) Binary addition or subtraction of a predetermined numerical value N to a desired area of the memory.

(Type I) M1+N→M P1: Memory area to be processed is set to file address m
Specify by B and digit address nC.

P2: Introduce the contents of the memory specified in P1 to ACC. Specify mB as the memory file address in order to return to the same memory later.

P3: Specify the numerical value N to be added with the operand, and add ACC
Add the contents of the memory introduced in , and the numerical value N, and obtain the result in ACC.

P4: Exchange the sum found in ACC with the original memory content specified in P2, and execute Type 1.

(Type2) N+N→X P1: Exchange the contents of register X and ACC.

P2: Specify the numerical value N to be added with the operand, and add ACC
Add the contents of the register X introduced into the register and the numerical value N, and obtain the result in ACC.

P3: By exchanging the sum obtained from ACC and the contents of register X, Type 2 is executed, which is substantially X+N→X.

(Type 3) M1+N→M2 P1: Specify the area to be processed in the first memory using file address mB and digit address nC.

P2: Introduce the contents of the memory specified in P1 to ACC. To specify the memory file address, the file address mC of the second memory is specified in order to return the addition result to the second memory.

P3: Specify the numerical value N to be added in the operand, and
The contents of the memory introduced in are added to the numerical value N, and the result is obtained from ACC.

P4: Exchange the sum found in ACC with the contents of the second memory specified in P2, and execute Type 3.

(Type 4) M1-N→M1 P1: Specify the file address mB and digit address nC of the memory to be processed.

P2: Subtraction is a method of adding the complement of the subtracted number to the minuend, and since there is no lower digit, there is no borrow and F/FC is set.

P3: Introduce a subtractive number N to ACC.

P4: In the process of taking the 15's complement of the subtracted number, the complement is A.
Find it in CC.

P5: Subtraction is 16 if there is no borrow from the lower digit.
Replaced by adding the complement and minuend of . A state in which there is no borrow is assumed to be C=1, and pure binary subtraction is executed as follows: ACC+C+M→ACC.

P6: AC to return the difference found in P5 to the same memory
Replace C and memory.

(Type 5) M1-N→M2 P6: In order to introduce the difference found in P5 into the second memory, specify the file address mc and digit address nC of the second memory.

P7: Transfer the difference data found in ACC to the second memory specified in P6 by exchange.

(Type 6) P1: Specify the temporary save memory address in P5 using file address mB and digit address nC.

P2: Subtraction is a method of adding the complement of the subtracted number to the minuend, and since there is no lower digit, there is no borrow and F/FC is set.

P3: Introduce a subtractive number N to ACC.

P4: In the process of taking the 15's complement of the subtracted number, the complement is A.
Find it in CC. .

P5: In preparation for operation with the contents of register X, the contents of ACC are introduced into the memory specified by P1.

P6: Transfer the contents of register X in exchange with ACC. After this process is completed, the memory contains the 15's complement of the subtracted number,
ACC contains the contents of X.

P7: ACC+M+C is a processing binary subtraction result corresponding to X-H, and the substantial subtraction result is found in ACC.

P8: Exchange the contents of ACC and the contents of X, transfer the value of X-N to X, and finish the Type 6 processing.

(Type 7) N-M1→M1 Specify the file address mB and digit address nC of the memory to be processed.

P2: Since this is a subtraction of one digit and the complement of the subtrahend is added to the minuend, F/FC is set.

P3: Introduce minuend to ACC.

P4: Exchange the memory contents (subtraction) and ACC, and also P
In preparation for the process in step 7, leave the memory file address as mB.

P5: The complement of ACC is found in the process of taking the 15's complement of the subtracted number of ACC.

P6: Subtraction is 1 if there is no borrow from the lower digits.
It is replaced by the process of adding the six's complement and the minuend.

Assuming that there is no borrow, C=1, ACC+C+M substantially performs N-M, and the difference is obtained from ACC.

P7: The memory file address remains mB in P4.
, so the difference in ACC is stored in the original memory,
Finish executing Type7.

(Type 8) N-M1→M2 P1: Specify the file address mB and digit address nC of the memory to be processed.

P2: Introduce the content corresponding to the subtraction specified in P1 into ACC. The file address mC of the second memory is specified in preparation for the process of P5.

P3: The complement of ACC is determined by the process of taking the 15's complement of the subtracted number of ACC.

P4: The contents of the operand are set to the minuend plus 1. This subtraction is for one digit, and is replaced by the process of adding the complement of the subtracted number and the minuend.

A general complement addition without a borrow is ACC+C+M as in Type 7, and is processed as C=I.

Since there is no C in the ADI instruction, ACC+I is performed in advance for processing. As a result, the result of the Type 8 operation of NM is found in ACC.

P5: The difference data obtained in P4 is converted to the second data specified in P2.
Transfer to memory.

(Type9) M±1→M P1: (When M+1) Binary number 0001 (=1) in ACC
will be introduced.

P'1: (When M-1) Binary number 1111 (=1
5) will be introduced.

P2: Specify the file address mB and digit address nC of the memory to be processed.

P3: Contents of memory specified by P2 and P1 or P1
The introduced contents of ACC are added and the sum is introduced into ACC. In the case of P1, it becomes ACC+1, and in the case of P1, it becomes substantially ACC-1.

P4: Transfer the result obtained by ACC to the original memory and finish Type 9.

(6) Add the contents of another area to the contents of the desired area of memory.
Add or subtract in decimal.

(Type I) X+W→X P1: Specify the first digit of the first memory to be processed using file address mA and digit address nE.

P2: When adding the first digit, there is no carry processing from the lower digits, so the carry F/FC is reset.

P3: The contents of the desired digits in the first memory are introduced into the ACC, and mB of the second memory is specified in the file address in preparation for addition with the contents of the second memory in P4.

P4: Add 6 to the contents of the desired digit in the first memory introduced into ACC, and use it to determine whether or not the next digit is on the decimal digit during addition in P5.

P5: The 6-corrected value in the first memory in P4 is required for ACC, and the content of this ACC and the content of the same digit in the second memory specified in P3 are added in pure binary,
Introduced to ACC again.

If a carry is found in the addition of the fourth bit of this pure binary addition, P6 is skipped and the process proceeds to P7. If a carry occurs in the addition of the fourth bit, it means that there was a decimal carry.

P6: When the addition in P5 does not result in a decimal digit, the 6 added in P4 is subtracted in this step to return to the original value. 1
Addition of 0 is the same as subtraction of 6.

P7: Add the sum of one decimal digit found in ACC to the second
The data is transferred to the memory by exchange, the digit address is increased in preparation for addition of the next digit, and the first memory is designated with the file address mA. By predetermining the final digit to be added as n1, if BL=n1 is reached after all digits in the first and second memories have been added, the next P8 can be skipped and Type 1 processing can be performed. Finish.

P8: Specify program address P3, repeat commands P3 to P7 until BL=n1, and proceed with decimal addition for each digit.

(Type 2) X-W→X P1: Specify the first digit of the first memory to be processed using file address mA and digit address nE.

P2: Subtraction is a method of adding the complement of the subtracted number to the minuend.
Since there is no borrow processing from the lower digits in digit subtraction, F/FC is set.

P3: Introduces the content that is the subtraction of the desired digit in the first memory into the ACC, and also inputs the second memory file address mB in preparation for processing with the second memory in P5 and P7.
Specify.

P4: Processing for taking the 15's complement of the subtracted number. 15
The complement of is found in ACC.

P5: The subtrahend is 1 if there is no borrow from the lower digits.
It is replaced by adding the 6's complement and the minuend, and if there is a borrow from the lower digits, it is replaced by adding the 15's complement of the subtrahend and the minuend. Let C = 1 in the state with no borrow, and ACC
Pure binary subtraction is executed at +C+M→ACC. The occurrence of a carry as a result of the ADCSK instruction execution means that no borrow occurred in the subtraction, so P6 is skipped and the process proceeds to P7.

Note that since the addition here is performed with the second memory designated by P3, it is essentially the second memory minus the first memory.

P6: If a carry does not occur with the ADCSK instruction in P5, subtract 6 because the result is obtained in hexadecimal (1
equivalent to adding 0) to convert it back to a decimal number.

P7: Transfer the difference between the second memory and the first memory found in the ACC by exchanging it with the contents of the second memory. In preparation for subtracting the next digit, the digit address is increased and the first memory is specified with the file address mA. By predetermining the final digit to be subtracted as n1, BL=n when the subtraction between the second memory and the first memory is completed for all digits.
1, so the next P8 is skipped and the Type 2 processing ends.

P8: Specify program address P3, repeat commands P3 to P7 until BL=n1, and proceed with decimal subtraction for each digit.

(7) Shift the contents of the memory in the desired area by one digit.

(Type 1) Right shift P1: Specifies the file address mA and digit address nA of the memory to be processed.

Introduce P2:0 to ACC and prepare to put 0 in the most significant digit when shifted to the right.

P3: Exchange the contents of the memory with ACC, lower the digit address, and designate one lower digit. The memory file address does not change in mA.

It returns to P3 again via the next P4, which means repeating XD. The 0 you put in ACC in P2 is the first ACC←→
At M, the most significant digit of the memory is entered, and the content originally in the most significant digit is entered into ACC. When the digit address is down in P3, and when you return to P3 via P4 and execute XD, the content of the original most significant digit in ACC is 1 because the 1 digit lower than the most significant digit is specified. The lower digits are transferred. At this time, the contents of one digit lower than the most significant one are transferred to ACC. By predetermining n2 as the least significant digit, if the above transfer is repeated up to the least significant digit, BL=n2 is satisfied, and P4 is skipped and the process ends. That is, the content of each digit is transferred to the lower digit, and Type 1 is executed.

P4: P to repeat XD of P3 until BL=v.
Return to 3.

(Type 2) Left shift P1: Specifies the file address mA and least significant digit nE of the memory to be processed.

Introduce P2:0 to ACC and prepare to put 0 in the least significant digit when shifted to the left.

P3: Exchange the contents of the memory with ACC, increase the digit address, and specify the higher digit. The memory file address does not change in mA. Since it returns to P3 again via the next P4, it means a repetition of XI. The 0 you put in ACC in P2 is the first ACC → M
This enters the lowest digit of the memory, and the content that was in the original lowest digit is stored in ACC. The digit address is updated in P3, returns to P3 via P4, and
When I is executed, one digit higher than the lowest digit is specified, so the content of the original lowest digit in the ACC is transferred to one digit higher. At this time A
The contents of one digit higher than the lowest order are transferred to the CC. By predetermining the most significant digit as n1, if the above transfer is repeated up to the most significant digit, BL=n1 is satisfied, and P4 is skipped and the process ends.

That is, the contents are transferred to the upper digit for each digit, and Type 2 is executed.

P4: Return to P3 to repeat XI of P3 until BL=v.

(8) Set or reset the 1-bit conditional F/F in the desired area of memory.

(Type I) P1: Specify the digits of the memory area to be processed using file address mB and digit address nC.

P2: Introduce 1 to desired pit N in the memory digit specified by P1 and execute Type 1.

(Type 2) P1: Specify the digits of the memory area to be processed using file address mB and digit address nC.

P2: Introduce 0 to the desired pit N in the memory digit specified by P1 and execute Type 2.

(9) Judge the contents of the 1-bit conditional F/F in the desired area of memory, and change the next program address (step) based on the judgment result.

(Type 1) P1: Specify the file address mB and digit address nC where 1 bit of the desired conditional F/F exists.

P2: If the content of the bit specified by N (corresponding to the desired conditional F/F) in the memory area specified by P1 is 1, skip P3 and proceed to P4 to execute operation OP1. If the content of the desired bit is 0, the process advances to the next step P3.

P3: Conditional F/F is 0 by judge at P2
In order to execute operation OP2, the program step is designated as Pn.

(10) Judge whether the digit content in the desired area of the memory is a predetermined value, and change the next program address (step) based on the judgment result.

P1: Specify the memory area containing the content to be judged using file address mn and digit address nC.

P2: Introduce the contents of the memory specified in P1 to ACC.

P3: Compare the contents of ACC with a predetermined numerical value N, and if they are equal, skip P4, proceed to P5, and execute operation OP1.

If the contents of ACC and N are not equal, proceed to P4.

P4: Specify program, address (step) Pn, and jump to Pn. Operation OP2 at Pn
Execute.

(11) Judge whether the contents of a plurality of digits in a desired area of the memory are all equal to a predetermined value N, and change the next address (step) based on the judgment result.

P1: Specify the memory area to be judged by file address mB, and specify the first digit address by nE.

P2: Introduce the numerical value N to be compared into ACC.

P3: Compare the contents of the comparison value N of ACC with the desired digit in the desired area of the memory, and if they match, skip P4 and proceed to P5 to compare the subsequent digits. If they do not match, proceed to P4.

P4: When there is a mismatch in P3, the program address (step) is specified to Pn and a jump is made to execute the operation immediately.

P5: Increase the digit address by adding 1 to the digit address. This process is for sequentially judging multiple digits in memory.

By predetermining the final digit address of the memory to be judged as (v), the above comparison is repeated for a desired number of digits. If a mismatch occurs midway, operation OP2 is executed via P4, but if the matches continue until BL=v, P6 is skipped and the process proceeds to P7, where operation OP1 is executed.

P7: When a match continues at P5, return to P3 and repeat the judgment.

(12) Judge whether the contents of the desired area of the memory are smaller than a predetermined value N, and change the next address (step) based on the judgment result.

P1: Memory file address mB to be judged
and digit address nC.

P2: Introduce the contents of the memory specified in P1 to ACC.

P3: If the numerical value to be compared with the memory contents is N,
Specify the numerical value 16-N as an operand, and write its contents and A
Add the memory contents of CC and obtain ACC. The occurrence of the fourth bit carry in this addition means that the binary addition result exceeds 16. In other words, M+(1
6-N)>16, which means that M>N is not satisfied, so proceed to P4.

P4: When M>N is not satisfied, in this step, the program address is designated as Pn, a jump is made, and operation OP2 is executed at Pn.

(13) Judge whether the contents of the desired area of the memory are larger than a predetermined value N, and change the next program address (step) based on the judgment result.

P1: Memory file address mB to be judged
and digit address nC.

P2: Introduce the contents of the memory specified in P1 to ACC.

P3: Let N be the numerical value to be compared with the contents of the memory. 15
- Specify the numerical value N as an operand, and its contents and ACC
Add the memory contents of and obtain ACC.

This addition results in a carry in the 4th bit, which means 2
This means that the base addition result exceeds 16. In other words, M+
(15-N)>16, which means M≧N+1
, , that is, M>N. In this case, this instruction skips P4, proceeds to P5, and executes operation OP1. If there is no carry, then M>N does not occur, so P
Proceed to step 4.

P4: When M>N is not satisfied, the program address (step) is designated as Pn at this step, a jump is made, and operation OP2 is executed at Pn.

(14) Display the contents of the desired area of memory.

(Type 1) P1: The number n1 of bits of W is input to ACC in order to reset the entire contents of the buffer register W that generates a digit selection signal for time-divisionally displaying the display.

P2: After shifting all the contents of register W by 1 bit to the right, the first
Enter 0 into the bit. P4 until C4=1 at P3
By repeating this through , the entire contents of W are reset.

P3: A by setting operand TA to 1111
C+1111 is removed and ACC-1 is essentially performed. P
Since n1 is put in ACC in step 1, by repeating this number of times, the 4th bit carry C4 becomes 0 only when adding with the next 1111 when ACC = 0, so only in this case go to P4, otherwise skips to P5.

P4: 4th bit carry at AC+1111 C4=0
In this case, all the contents of W have been set to 0, so the preprocessing is completed and the first address P6 of the display step in the memory is jumped.

P5: 4th bit carry C4= at ACC+1111
When it is 1, the process of setting all contents of W to 0 has not yet been completed, so the process returns to P2 and 0 input to W is repeated.

P6: The first memory area containing the content to be displayed
File address mA and digit address nA
Specify with.

P7: After right-shifting the contents of the register W that generates the display digit selection signal by 1 bit, 1 is placed in the first bit. This prepares for supplying a digit selection signal to the first digit display.

P8: Input the contents of the desired area of the specified memory to ACC. The memory file address remains mA. Also, in preparation for processing the next digit, the digit address is down.

P9: Transfer the contents of the memory stored in ACC to output buffer register F. The contents of register F are input to segment decoder SD, which generates a segment display signal.

P10: In order to output the contents of the register W to the outside as a display signal, 1 is put in the conditional F/FNP to set it to the set state. With this, the memory contents processed in P9 are displayed on the first digit display.

P11: Input count initial value n2 for determining display time for one digit into ACC.

P2: Perform ACC-1 substantially in the same way as P3. A.C.
When C becomes 0, skip to p13, and when the content of ACC is not 0 (when C4=1), skip to p14, and repeat this process.

P13: The desired display time is processed by counting the contents of ACC in P12, and when the count is finished, P1 is displayed via P13.
Jump to 5. This count time becomes the one-digit display time.

P14: From P12 to P1 until the desired display time elapses
Skip step 3 and proceed to P14, jump to P12 again, and repeat this.

P15: Reset NP and stop supplying the digit selection signal to the display. Next, until NP is set again in P10, it is applied to prevent overlapping display by adjacent digit signals of display.

P16: In preparation for displaying the next digit, the register W is shifted to the right by 1 bit, 0 is placed in the first bit, and I, which was input in P7, is essentially shifted to the lower digit by 1 bit, in preparation for selecting the next digit.

P17: Check whether the last digit of the memory to be displayed has been completed. Since BL-1 has been done in the process of P8, it is checked whether the value nE of the last digit -1 has been reached.

P18: When the final digit has not arrived, the process returns to P8 and displays the next digit.

P19: For example, if flag F/FFA is used as the display end condition, FA=1 and P20 is skipped to end the series of display processing.

P20: If FA=0 in P19, the process jumps to P6 to repeat the display process starting from the first digit.

(Type 2) P1: In order to reset the entire contents of the buffer register W that generates a digit selection signal for time-divisionally displaying the display, the number of bits n1 of W is input to ACC.

P2: After shifting all the contents of register W by 1 bit to the right, the first
Enter 0 into the bit. P4 until C4=1 at P3
By repeating this through , the entire contents of W are reset.

P3: A by setting operand IA to 1111
CC=+1111 is made, essentially performing ACC-1. Since n1 is put in ACC in P1, by repeating this number of times, the fourth bit carry C4 becomes 0 only when adding with the next 1111 where ACC = 0, so only at this time do you proceed to P4 and add it. Otherwise, skip to P5.

P4: 4th bit carry C4= at ACC+1111
When it is 0, it means that the entire contents of W have been set to 0, so the preprocessing is completed and the process jumps to the first address P6 of the display step in the memory.

P5: 4th bit carry C4= at ACC+1111
If it is 1, the process of setting all the contents of W to 0 has not yet been completed, so the process returns to P2 and the input to W is repeated.

P6: The first memory area containing the content to be displayed
The upper 4 bits of the digits are specified by the file address mA and digit address nA.

P7: Input the contents of the desired area of the specified memory to ACC. The memory file address remains mA. Also, lower the digit address to specify the lower 4 bits.

P8: Transfer the contents of ACC, ie, the upper 4 bits, to temporary register X.

P9: Input the contents of the desired area of the specified memory to ACC. The memory file address remains mA. Also, lower the digit address and enter the top 4 of the next digit.
Specify bit.

P10: Insert the contents of ACC into stack register SA and the contents of temporary register X into stack register SX.

P11: After shifting the contents of the register W that generates the display digit selection signal to the right by 1 bit, 1 is placed in the first bit. For this purpose, provision is made for supplying the first digit selection signal.

P12: Put 1 into the conditional F/FNP for outputting the contents of the register W as a display signal to the outside to bring it into a set state. The memory contents processed in P14 are then displayed on the first digit display.

P13: Input the count initial value n2 for determining the display time for one digit into ACC.

P14: Perform ACC-1 substantially in the same manner as P3. A
When CC becomes 0, go to P15, when ACC/0 (C
4=1), skips to P16 and repeats this process.

P15: The desired display time is processed by counting the contents of ACC in P14, and when the count is finished, P1 is displayed via P15.
7 Hejjump. This count time becomes the one-digit display time.

P16: From P14 to P until the desired display time has elapsed.
Skip 15 and proceed to P16, jump to P14 again, and repeat this.

P17: Reset NP and stop supplying the digit selection signal to the display. Next, until NP is set again at P10, the adjacent digit signals are used to prevent overlapping display.

P18: In preparation for displaying the next digit, shift the register W by 1 bit to the right and put 0 in the first bit, essentially shifting the 1 input in P7 to the lower digit by 1 bit.

P19: Checking whether the last digit of the memory to be displayed has been completed. Since Bl1 has been done in the process of P9, it is checked whether the value nE of the last digit minus 1 has been reached.

P20: When the final digit has not arrived, the process returns to P7 and displays the next digit.

(15) Something that determines the type of key switch that is pressed. (Check whether or not a key is pressed during display) P1 to P18:
This is the display process described in (14).

P19: After displaying the contents of all digits in register W, flag F/FFC is set and key signals I1 to In are all set to 1.

P20: If any of the keys connected to key input KN1 is pressed, jump to P30.

It is judged whether any of the keys connected to each of P22 to P27 key inputs KN2 to KF2 has been pressed, and if not pressed, the next step is skipped. If pressed, jump to P30.

P28: When no key is pressed, F/F
Reset the FC and finish the key suppression check.

P29: Jump to P and continue displaying again.

P30: A step that comes when a key is pressed, setting the memory digit address to the first state n1 in order to generate the first key strobe signal I1.

P31: First key strobe signal I1 to key input KN1
It judges whether or not it has been input, and if it has not, it skips to P33.

P32: First key strobe signal Il to key input KN1
When the key is input, the type of key is determined, the PA is jumped to, and the control corresponding to the determined key is performed as follows.

After completing the key control, the controller jumps directly to the PI and starts displaying it.

(P2 is an example of steps for jumping to P1) P33 to P38: The keys connected to the first key strobe signal ■1 are sequentially determined, and if the desired key is pressed, jumps to PB-PD and returns to that key. Perform corresponding control.

P39: When the key connected to the first key strobe signal 11 is not pressed, the memory digit address is increased to generate the second key strobe signal.

P41~: Generates a desired key strobe signal, sequentially judges KN1~KF2, determines the type of pressed key, and jumps to a desired step to control the pressed key.

PA~: Control step for the first key PX: After the first key control is completed, return to P1 and restart the display.

The above is an explanation of the main processing operations of the CPU.

Next, the audio output control method will be explained.

FIG. 4 shows an example of an audio output control circuit, in which V
R is read-only where audio data is stored.
Memory (ROM), VAC is VR address counter, VAD is VR address decoder, FA is adder, C
LA is the VAC reset circuit, DAC is the digital-to-analog conversion circuit, LPF is the reduction filter, SP is the speaker, DD is the speaker drive circuit, JE is the END code detection circuit, CC is the code conversion circuit, and S1 is the CC input. signal, S
2 is the output signal of JE, VCC is the audio output control circuit, VR
0 represents the output of VR, respectively. Audio data is stored in the memory VR. P1P2... indicates each region of spoken words.

When VAC is not outputting audio, it is assumed that it is reset by CLA. When the address counter VAC is in the reset state, no address of the VR is specified, and therefore no audio is substantially output.

When it is desired to output audio, the initial address of the corresponding audio area P is set in VAC. For example, if the desired word is P
2, the initial address of P2 is set to VAC.

Then, data at the initial address VR0 is output.

Note that the FA is an adder circuit for increasing the address of VAC by one step, and performs VAC+1→VAC. When VAC is in the reset state, this FA does not operate and the contents of VAC do not change. In other words, it remains reset.

However, when the initial address arrives and the state becomes "0", the above VAC is automatically set at a constant sampling frequency.
+1→VAC shall be performed.

Therefore, once the initial address is set in VAC, the address is automatically increased one step at a time thereafter. Therefore, as the output of VR0, the quantized data of the region P2 is sequentially output.

The output of VR0 is converted from D to A by a DAC, and then L
PF passes low frequency components. This converts the data to D-
If the analog output after A conversion is step-like, if it is output as is from a speaker, noise-like audio may be mixed in due to high frequency components, making it difficult to hear, so it is desirable to filter it with an LPF.

In this way, the output of the LPF is outputted as sound by the speaker SP via the speaker drive circuit DD.

The data structure of each area of VR is formed by adding an END (end) code to the last step of the audio data, as shown in FIG. Therefore, when the desired audio output is completed, the END code is output from VR0.

JE detects this and activates CLA to reset VAC. As a result, no address in the VR is designated, and the series of audio outputs stops.

This state is maintained until a new initial address is subsequently set in the VAC.

CC is a conversion circuit for determining a desired initial address in accordance with the audio area designation signal S1 in order to set the initial address of the audio area desired to be output by the code conversion circuit to VAC.

S2 is the output of JE, and when multiple words are continuously generated, the output of JE provides the S1 signal corresponding to the next word.

The code converter receives the audio area designation signal S1 and converts the VR
However, it is also possible to incorporate a gate circuit inside and transmit the code-converted designation signal S1 to the VAC only when the trigger signal S0 arrives.

The operation of the audio equipment of the present invention will be explained below using the flowcharts shown in FIGS. 6 and 7.

FIG. 6 is a flowchart for performing processing for generating sounds corresponding to keys.

In the figure, n1+n2+...n3 is a step to judge which key was pressed. For example, if the key "0" was pressed, the process goes from step n1 to n4, and "0" is read in. Perform the processing to do so using a general method.

After this is completed, audio output control is performed. step n
When the operand I3 of the accumulator ACC is input in step 7, the operand here is assumed to be 4 bits, and in the case of a multi-value key, for example, 0000 is input. And this A in n8
Introduce the contents of CC into temporary register X. At the next n9, the LDI command is output again. (1st
(See No. 12 in the table) However, the operand here is set to 0001, for example, to represent the "0" key. This introduces 0001 into the accumulator ACC. Jump to n18 with T command of n10. Since the contents of the accumulator ACC and register X are transferred to the stack registers SA and SX by the 5TPO instruction of n18, the contents of the stack register will eventually become a code representing 0 as SXSA 00000001.

These SX and SA outputs are given to the S1 input of the speech synthesis circuit VCC. And in the next n19 flag F/FF
Set B. The FB output is connected to the S0 input of VCC, and when S0 = 1, the codes of SX and SA become VC.
It is substantially incorporated into the code converter CC of C to perform code conversion and generate the word "ray" or "zero" which hereinafter corresponds to the number "0". The FB set in step n20 is reset.

If the ward key is pressed, general processing of the ward key is performed at step n6, and then the process proceeds to step n15. At n15, put the first operand I8 into accumulator ACC, and at n16
Move this to temporary register
Operand I9 is placed in ACC and transferred to stack registers SX and SA at once at n18.

The first and second operands are as follows.

SXSA 00010101 -1st--2nd- For example, if you set it as 0001 and 0101 as above,
00010101 code is entered in SX and SA. You can think of this code as the code corresponding to "x". The reason why it is set to 8 bits is to prevent this, since 4 bits can only handle 16 different words.

After transferring to SX and SA at n18, the flag flip-flop FB is set at n19, and this code is converted into a code by the code converter CC of the audio output control circuit VCC. For example, the word "Kakeru" corresponding to "x" is written. The initial address of is input to the address counter VAC of the memory VR. The following ``Kakeru'' will be output as audio.

Next, the method of outputting sound after pressing the equal key and performing the desired calculation will be explained based on the flowchart shown in FIG.

■If you do not press the key, proceed to step n22 and select Memo M.
1 is displayed and the key confirmation process is performed again. ■When a key is pressed, the corresponding process is performed in step n23,
The processing results are obtained in the memory M1 using a general method. Then proceed to n24.

Hereinafter, description will be continued of parts particularly related to the present invention.

Steps n24 to n31 are processing steps for uttering the word "Answer wa", in which the LDT command of n24 specifies the initial address of the voice output control circuit VCC containing the synthesized data "Answer wa" in the accumulator ACC. Specify the upper 4 bits of the code (8 bits). n25 temporarily stores this upper 4 bit code.
Put it into register X, and put the lower 4 bits into accumulator ACC in the next n26. Then, the 8-bit code is transferred to the stack registers SX and SA all at once using the STPO instruction of n27 (instruction code No. 52, see Table 1).

Then, in step n28, the flip-flop FR is set to specify the initial address of "Answer wa", and the utterance is started. Reset the FR using n29.

n30 and n31 are checks to see if the word "Answer wa" has been finished. Since the input terminal of the central processing unit CPU is connected to the termination signal S2 of the audio output control circuit VCC, when the S2 signal is not generated, n30→n
Repeat 31→n31... (The operand of the T instruction of n31 is of course the address value of n30.) S2
If this occurs, skip n31 and proceed to n32. Steps n12 to n50 are for outputting audio while performing 0 suppression processing on the data in the memory M1. Since this is numerical data, the upper 4 bits are always 00 here.
Set it to 00.

n32 stores 0000 in accumulator A through this process.
CC and move it to the X register at n33.

The LB command of n34 specifies the most significant digit of memory M1. Then, at n35, the contents of the memory M1 are introduced into the accumulator ACC. When processing is completed to the lowest digit, BL=v built into the LD instruction is satisfied, and n3
Skip 6 and proceed to n37, but until then proceed to n36 and then jump to n38. SKFA here is a judge of flag F/FFA, and as will be described later, it judges whether the high order of data is 0 or not, so when =0 comes, FA is set, and until then, FA is in a reset state. Therefore, if the most significant digit is 0, jump from n39 to n41. SKAI of n41 is a judge whether the contents of accumulator ACC and operand I match or not, and operand I here is 000.
Select 0. That is, since the memory contents are stored in ACC in n35, it is checked whether this contents is decimal number 0 or not. If ACC=0, skip n42 and proceed to n42, and from there return to n35. This is A
Repeat until CC=0.

When the n35 LD command is executed, the memory digit address counter is automatically decremented, so the above processing is possible. In this way, when ACC=O, n4
1→n42→n43, and the flip-flop FA is set at n43. With the STPO command in the subsequent step n44, the numerical codes at that time are transferred to SX and SA all at once. Then, n45 sets the flip-flop FB, so
This number begins to be emitted audibly. Reset FB using n46. At the judge of the end of the audio output of n47n49,
This process is repeated until the above-mentioned numerically corresponding words are outputted aloud.

When the audio output is finished, the process skips n48, proceeds to n49, returns to n35, and introduces the next digit of data from the memory M1 into the accumulator ACC. n35→n
The process goes from 36 to n38, but since the flip-flop FA is set at n43, skip n37 and go to n38.
The process advances to step 40, and then to n44, where the numerical code utterance process for the next digit is performed. Repeat this below.

If n2 is one digit below the least significant digit of the memory M1 containing data, then n
When we come to 35, here BL=(v=n2), so n
Skip 36 and proceed to n37, then jump to n50. At this point, the FA is reset and the series of data output is completed.

Further, steps n51 to n56 will be explained.

This step shows the audio output process for "desu" according to the present invention.

Step n51 is the process of putting the above 4 bits of the code for "desu" into the accumulator ACC, and in step n52 this is
Transfer to the register, put the lower 4 bits into the accumulator ACC at n53, and transfer them all at once to the stack register SX at n54.
, SA, and the flip-flop FB set of n55 causes the voice output control circuit VCC to output ``desu'' as voice. n57 and n58 are similar to n30 and n31, and perform processing to return to the initial state after generating the voice "desu".

This prevents the occurrence of the word "Desu" being cut off when a key is pressed while the voice output "Desu" is being uttered.

Steps n1, n2, ... n3, n21, n mentioned above
The process No. 22 can be executed based on the process list (15) of the CPU device described above.

In this way, after the automatic voice output of the data "is"
By generating words other than numerical values, such as ``answer,'' it is possible to distinguish between the voice when a key is pressed and the processed data, or to distinguish data using words such as ``answer'' immediately before outputting the processed data.

On the other hand, in FIG. 6, steps m1 to m3 are steps added to output the content of the previous key pressed by the V key shown in FIG. 1 as voice.

When the X key is pressed, the process advances from step m1 to step m2, and flag F/FFB is set. The state in which the key has been pressed can be determined by checking the processing of the 0, 1, . . . ward keys in the figure.

In other words, the STPO instruction of n18 causes stack register S
Key codes are entered in X and SA, and those codes remain as they are until the next key is pressed.

Therefore, if the flip-flop FB is set and the output of FB is given to the trigger input S0 of the voice control circuit VCC, naturally the key codes stored in the stack registers SX and SA at that time will be successively handled within VCC. Output audio.

m3 is a step for resetting the FB and returning it to its initial state.

By pressing the concave key as described above, the previous key can be confirmed by voice.

<Effects> As described above, according to the present invention, there is an advantage that information can be effectively processed using voice, and information in each operation mode can be distinguished by voice.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a computer in which the audio information processing device of the present invention is adopted, and FIG. 2 is a specific logic circuit configuration diagram of a microprocessor CPU.
Includes diagram D. 3 is a diagram showing a circuit equivalent to 2A-D, FIG. 4 is a block diagram of the audio output control circuit, FIG. 5 is a diagram showing the data structure of each area of the memory VR, and FIGS. FIG. 7 shows a flowchart for explaining the operation of the above computer. CPU: Microprocessor, DSP: Display, KEY
: Key input device, V: Voice confirmation key, M1: Memory,
VCC: Voice synthesis circuit, SX, SA Nistack register, VR: Read-only memory, VAC: Address counter, VAD: Address decoder, FA: Adder, C
LA: Reset circuit, DAC: Digital-analog conversion circuit, LPF: Low-pass filter, SP: Speaker, DD=
Drive circuit, JE: END code detection circuit, CC: code conversion circuit, VCC: audio output control circuit. Representative Patent Attorney Yoshihiko Fukushi (and 2 others)

Claims (3)

[Claims] (1) An operation mode setting means that can be set to a first operation mode and a second operation mode, and means for generating an audible sound, the audible sound generation means representing the first operation mode. a first audible tone, said second audible tone;
a second audible tone generated in accordance with the first audible tone;
1. An audio information processing device, comprising: means for generating a third audible sound that is generated before the second audible sound for distinguishing the operation mode from the second audible sound. (2) the first operation mode is an information input mode, the first audible sound represents the information input mode, and the second operation mode consists of a processing result output mode that occurs in response to completion of the information input mode; A second audible sound represents a processing result output mode, and a third audible sound is generated between the first audible sound and the second audible sound to distinguish between the information input mode and the processing result output mode. An audio information processing device according to claim 1, characterized in that: (3) The audio information processing device according to claim 1 or 2, wherein the third audible sound is spoken words of a predetermined language.