JPS584371B2 - Relative address determination method for object instruction generation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address determination formula for an object instruction in a computer which has a plurality of addressing mechanisms for instructions of the same function and thus has a plurality of instruction word lengths.

In the following explanation, for the sake of simplicity, we will use two types of words, one word length and two word lengths (hereinafter simply referred to as short words/long words), but the concept is the same even if there are more types.

A calculator with two machine word lengths, long words and short words, for example 16
In a small computer (mini computer) where a bint is one word, the judgment as to whether the object (machine language) of the assembler synutem should be a long word or a short word has traditionally been made at the coding stage. This was done by the user identifying and specifying.

Originally, whether it should be a command word, a long word, or a short word is
It is determined by whether the long/short words of each command group before and after the command are as follows.

Therefore, due to user changes or program changes,
When a command word that should originally be a long word is mistakenly designated as a short word, the long/short words of other command words will also change due to the incorrect designation, and the program work that needs to be corrected will be affected. The user had to undertake the work themselves, which placed a heavy burden on the user.

If an attempt was made to automatically perform this long word/short word determination and correction work using an assembler synutem, there was a problem that the changed value would spread to the address portions of other instructions, making it difficult to determine the address.

Accordingly, a principal object of the present invention is to provide an address determination method for object instructions which eliminates the various drawbacks of the conventional art.

In other words, when a user codes or when an object instruction is generated by a compiler, short words and long words are automatically identified without the need to specify short words and long words, and the address determination formula of object instructions is Our goal is to provide the following.

Another object of the present invention is to provide a relative address determination method for object instructions that allows efficient determination of long words/short words and efficient optimization of object instructions.

The outline of the long word/short word determination work in the present invention is as follows.

(a) First, one command word (hereinafter referred to as a line) in the user program UP is a short word or a command word without a long word.

) into the assembler synutem.

(Mouth) Next, determine whether this line should be a long word or a short word from the status of each command group before and after this line, and input the decision information on whether it is a short word or a long word into the input information UP. Add and output.

(c) If this line is the last line of the user program, the work is finished; otherwise, the work in (c) is repeated.

The above series of scans is repeated from the first line to the last line of the user program.

However, scanning the user program once does not necessarily result in an optimal decision.

Therefore, in order to optimize, the above (a), (0)
, (C) must be performed multiple times.

However, for those whose long/short words have been determined,
Of course, the processing in (mouth) will not be executed.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

First, let's explain assembler instructions written in assembler language.

Several types of assembler instructions are defined depending on the type and scale of the computer, and also based on software considerations.

When a user wants to input a program into a computer using an assembler language, the user creates a program using a combination of the above assembler instructions and inputs the program.

For ease of explanation, the assembler instructions are LD (data read) instruction, ST (data store) instruction, and DC (constant definition) instruction.
Let's limit it to four types: commands and BSS (area security) commands.

FIG. 1 shows the form in which these instructions are actually used as a user program.

In this figure, the LD command...transfers the contents of the address M1 specified in the address column ADDR indicating the address on the memory to the accumulator.

ST command: Transfers the contents of the accumulator to the memory M2 specified by the address field ADDR.

DC instruction: An instruction that requests the assembler/syntem to set the constant C specified in the address column ADDR to the address L1 of the memory indicated by the label column LABEL before executing the program. be.

BSS instruction: Requests the assembler system to secure an area corresponding to the word length corresponding to the constant a specified in the address field ADDR from address L2 in the memory indicated by the label field LABBL before executing the program. This is an order to do so.

A user program written using such assembler instructions is input and processed by the assembler system, and the output obtained is an object (machine language, format).

Object instructions obtained by converting to objects include:
There are two commands: short word command SW and long word command DW.

The actual formant of this short word/long word command is the LD command,
FIG. 2 shows a DC instruction as an example.

Here, the LD command has two forms: short word/long word, and DC
Instructions should be in short form only.

In the figure, OP is the part that indicates the type of instruction (operand), and the instruction column shown in Figure 1, from the contents of COMM, is converted into a binary instruction by the assembler system. The result is obtained by decoding into a code.

F: Flag section indicating whether the word is a short word or a long word, and occupies 1 bit.

“O” for short word commands, “O” for long word commands "1" is set.

DISP: This is a relative address field for setting the relative address value n from the address where this instruction exists to the specified address M specified in the address column ADDR shown in FIG.

For example, set the occupied bits of this relative address part to 8 bits. In this case, the relative address part The value n of DISP is -128≦n≦ The range is 127.

A-ADDR: This is an absolute address section that indicates an absolute address, unlike the relative address section DISP.

In other words, the content is the address value itself of the specified address. is set.

For example, if the first address of memory is O address, Specify this absolute address part A-ADDR. The specified address must be at the beginning of memory. This corresponds to the address number It shows that.

In FIG. 2, the short word instruction SW is 16 bits, and the long word instruction DW is 16 bits.
is set to 32 bits.

Further, the occupied bits of the relative address section DISP are 8 bits, and the occupied bits of the absolute address section A-ADDR are 16 bits, and the bits below 0 are based on the bit occupancy state.

As is clear from the above explanation, determining whether a word is a short word or a long word is determined by the relative address.

That is, the relative address is the relative address part D shown in FIG.
If n is within the ISP limit value of -128≦n≦127, the instruction will be in short word format, and if it exceeds this range, it will be in long word format.

The effective address E-ADDR when converted to short word format is E-ADDR-(PC)+n...{1
).

PC is a program counter that stores the next address of the program instruction currently being executed, and (PC) indicates the contents of the count PC.

n is a relative address value. The effective address E-ADDR in long word format is E-ADDR-(A-ADDR) ・・・・・・(
2).

(A-ADDR) means the display content of the absolute address section A-ADDR.

As shown in Figure 2, the object format of the DC instruction, which is in short word format, is that the value C specified in the address field ADDR shown in Figure 1 is set as a binary number in the data field DATA. There is.

Next, embodiments of the present invention will be described with reference to FIGS. 3 to 5.

The main components of the present invention are the input section IT and the input attribute section NA.
It consists of MET (mainly a label registration table section).

First, the input section will be explained with reference to FIG.

This input section contains the user program UP and the address/address created by the assembler system based on the program.
This is established from table LACT and flag table FT.

User program UP is programmed using instructions written in the assembler language as described above.

Address table LACT: A table that stores the address value of each instruction (so-called "line") of the user program UP, and the contents of the program counter PC (pc) when the instruction is executed. has a value equivalent to .

In the diagram, the symbol ■ indicates that the distinction between long words and short words is correct. A so-called temporary address that is not determined by a formula This means a response, and the display of ■ means The distinction between long words and short words has been officially established. Modified address under the condition I'm tasting it.

As a matter of course, the contents of this address table LACT change during the process of processing by the assembler synutem.

Flag table FT: A table that records whether the machine language that is an object of the assembler system is a short instruction or a long instruction. When it is a short instruction, "0" is set. In the case of a long instruction, ``1'' is set.The indications ``■'' and ``■'' have the same meaning as described in the address table LACT.

Next, the input attribute section will be explained with reference to FIG.

This input attribute section consists of a label registration table NAMET and a table pointer NAP created by the assembler system for the display contents of the label field LABEL in the user program UP.

Label registration table NAMET: Consists of a label mLABEL2 indicating the display label of the label column LABEL of the user program UP, ADDR2 indicating its address, and an entry ENTRY.

Entry ENTRY is label registration table This indicates the registration order of NAMET. It consists of numbers such as 1, 2, 3, etc.

The labels appearing in the label field in the user program UP are set in the label section LABEL2 in order.

■ and ■ are the values before correction and the values after correction, as described above.

Table pointer NAP...Label registration table N
It is used as a table pointer for AMET and consists of one word (for example, 16 bits) of occupied bits.

The value actually set is the row currently being processed. (command) of the label field that appeared previously Among the labels, the most recent label This is the content of the ENTRY.

Therefore, according to the figure, there are 12 rows currently being processed. It turns out that.

In Figures 3 and 4 and subsequent figures, the display (()) is the value before correction, () is the value to be corrected, and other display, that is, ((
A value that does not belong to both )) and () is a value at the time of current processing.

Further, the portions related to LACI and LAC2 shown on the right side of FIG. 3 will be described later.

FIG. 5 shows a specific embodiment of the present invention.

The input section IT and the input attribute section NAMET consist of storage devices, and their initial states are shown in FIGS. 6a and 6C.

The input attribute section NAMET is slightly different from that shown in FIG. 4 in that it has an entry ENTRY, but this is provided to make the explanation easier to understand, and in this embodiment, the entry ENTRY section is omitted. However, it is replaced by another function (described later).

In FIG. 6C, this is indicated by a dotted line to make the explanation easier to understand.

FIG. 6a shows the initial state of IT, C shows the initial state of NAMET, b shows the initial state of LAC, and d shows the initial state of NAP.

The initial states of the input section IT and the input attribute section NAMET are generally obtained as the output of a label analysis section (display omitted) of a language processing processor that analyzes a user source program.

In this embodiment, in addition to this, there is also a block gram counter PC that specifies the address of the input section IT, a register ITR that temporarily stores the readout output of the human section IT, and a label detector that detects the presence or absence of a label in the register. DET2, an AND gate A2, a register LAC1 that temporarily takes in the contents of the address table LACT, a register LAC2 whose contents are changed according to the determination of short/long words, an adder circuit LADD1 that adds 1 to the register LAC2, and It consists of an adder circuit LADD2 which adds 2 to the register LAC2, and a register LAC3 used to determine whether all lines of the program have been completed.

Further, a detector DET1 for detecting the presence or absence of the contents of the register LAC2, an AND gate A1, and comparison circuits COMP1 and C
OMP2, COMP3, COMP4, COMP5, CO
Consists of MP6 and COMP7.

Register N that specifies the entry of the input attribute section NAMET
It consists of AP1, registers NAP2 and NAP3 that assist this register NAP1, and an adder circuit ADD1.

Furthermore, in this embodiment, a register NAMETR temporarily stores the content of the address of the input attribute section NAME, and a short word detector SFT that outputs data of "0" or "1" depending on the short/long word. Long word detector DFT, intermediate output section MT,
It consists of a register MTR that temporarily stores the contents of the address of the output section MT, an output conversion section MI, and a suspension section OT.

The initial states of the input section IT and the input attribute section NAMET are as shown in FIG. 6 alC, and the flag. Table FT
is "0" for an instruction that is absolutely determined to be a short word (DC instruction), and "0" for an instruction that is absolutely determined to be a long word (≠ not shown in this example). "1" is set, and commands whose short/long edicts are undetermined are unconditionally treated as long commands, and "1" is set.

Based on this, the initial state of LACT is set.

The initial states of LAC1-3 and NAP1-3 corresponding to this initial state are shown in FIGS. 6b and 6d.

Here, it is assumed that the contents of LACT corresponding to the last line (2) of IT in FIG. 6a are set in LAC3.

For reference, Figure 6 d shows the NAP corresponding to Figure 4.
It also shows the initial state of
The label LABEL1 in P is registered, and the corresponding address is set in the address field ADDR2.

Under the above preconditions, it is assumed that No. 1 is processed up to No. 2, and No. 1 is processed from now on.

At this time, the input section ■ T1 manual attribute section NAMET is shown in Figure I a.
, c. Figures a to d are explanatory diagrams of label processing for "ALDM" (No-■).

The value of LAC2 to LACT, the value of LAC2 to NAMET
is transferred to ADDR2 corresponding to label A.

The state before the start of the label processing for No=■ is such that the LACT is modified from the initial state (750, (soo)) to 700, 730 in the processing for Nos. 1, 2.

In the processing of rot=■, LACT is about to be corrected from the initial state 900 to 820 as a result of word length adjustment.

The states of LAC1 to LAC3 are as shown in Fig. γ (b).

Next, change the contents of LACT (=LAC2) to NAME
Set to T.

When registering label ADDR2, logically, if there is a NAP register, the next entry indicated by the contents of the NAP register becomes the label without scanning from the top of NAMET, but in the embodiment shown in FIG. To simplify (commonize) the process, we use a method that scans from the top every time.

Now, in Figure 1 a, the process No. 1 is a program.
The process is started by address designation by the counter PC (FIG. 5).

The address indicated by this counter PC indicates No=■, and as a result, the register ITR contains "ALD M" as the user program UP corresponding to No.
”, “900” as location table LACT
, "1" is read and set as the flag table FT, respectively.

The contents of the location table LACT in this register ITR are then transferred to the register LAC1.

Next, in order to replace the provisional content of LACT with the latest adjustment result in the processing up to No. 1, the address detector DETI detects whether an address is stored in the register LAC2.

If the address is set, the contents of the register LAC2 are sent through the AND gate A1 to the location table LACT of the previous register ITR and stored therein.

The details of this register LAC2 will be described later, but the short word/
The structure is such that the content changes depending on the length of the word.

Now, in Fig. γb, since "820" is set in LAC2, the address table LAC
The address [820J] will be set to T.

Of course, it goes without saying that the contents of LACT are cleared before r820j is set.

In this case, the contents of LAC1 remain as they were.

Next, the label detector DET2 detects whether a label actually exists in the label section LABLL1 in the user program UP of the register ITR.

Since No. 1, which is currently being processed, has the label "A", a detection output signal is obtained.

This output signal causes the AND gate A2 to open, and the label content fAJ of the label section LABEL1 of the open register IT,R to be sent to the comparator COMPI.

The comparator COMP1 is configured to receive the contents of the label section LABEL2 of the register NAMETH.

The comparator CO determines whether these two labels match.
It is compared and detected by MPI, and when there is a match, AND gate A is executed.
3 is opened, the contents of register LAC 2 [820- are sent to the address field ADDR2 of register NAMETR, and the contents are stored and registered in the label registration table NAMET (
Comparator COMP1 (line 12 of entry 12 in Figure γ)
During the operation process, the label part L of the register NAMETR
The contents of ABEL2 are sequentially changed by scanning each address of table 'NAME'I'.

This will be explained below. Address scanning of table NAMET is performed by entry register NAP as shown in FIG.
This is done by the address specified by .

In the entry register NAP, as shown in FIG.
At the current processing time, "11" is set as the entry number.

In FIG. 5, the corresponding number is stored in NAPI, but at the start of scanning NAMET, it is first stored in register N.
The first address of the table NAMET, which is temporarily held in AP3 and is instead stored in register NAP2, is set in register NAP1.

The table NAME is set according to the contents of this register NAP1.
The content of the first address of T is read out to the register NAMETR, and the label part LABE in this read content is
L2 is sent to comparator COMPI and compared.

When there is no match, the contents of the register NAP1 are added with an address m corresponding to one entry of NAMET through the adder circuit ADDI, and the address corresponding to the next entry number is sent to the register NAP1, and the address corresponding to the table NAMET is added. The contents of the address are read.

Similar comparisons are then made. Thereafter, scanning is performed sequentially, and when a match is obtained during the scanning process, the AND gate A3 is opened as described above, and the contents of the register LAC2 are written to the address field ADDR2 of the matching address and registered ( As a result, entry 12 in Figure γC
changes from 900 to 820.

). The above scanning process is not necessarily necessary when it is performed by a program.

In other words, as shown in Figure 4, if the current entry number is set as "11", you can find out what the next label is by looking at the entry number "12" (because LABEL2 of NAMET U for the part
Since the LABEL of P is stored in the order in which it appears, when No=■ is processed, NAP=11 and No=
If LABEL does not exist in the UP between ■, NA
This is because LABEL No. ■ exists at P=12.

). Therefore, in such a case, it is not necessary to scan all the addresses in the table NANET, and it is only necessary to determine the presence or absence of a label, that is, to check whether the label "A" is in the entry number "12".

Of course, in this embodiment, the address is specified instead of the entry number, and not the entry number itself, so the above-mentioned scanning process is necessary.

As mentioned earlier, the reason why NAP was not used in this embodiment was to share the SC section in FIG. 5 between the process described in FIG. γ and the process described in FIG. 8 (described later). And the result is the same either way.

After the comparison is completed, the address corresponding to the entry number 11, which is the data temporarily stored in the register NAP3, is set in the register NAP1.

Next, the comparator COM compares the address part ADDR1 of the user program UP in the register ITR with the contents of the label part LABEL2 of each address in the table NAMET.
This is done by P2 (Figure 8).

During this comparison, each address of the table file NAMET is scanned (FIG. 8a).

In this scan in FIG. 5, the contents of register NAP1 are temporarily stored in register NAP3, as in the previous scan.
The first address of table NAMET is register NAP2
is specified by the contents of and transferred to NAP1.

Addresses after the above-mentioned top address of the table NAMET, which are required when a matching output is not obtained by the comparison of COMP2, are set by addresses obtained through the adder circuit ADD1 that adds 10m.

In the course of such scanning, when a match is expected in the comparator COMP2, a match signal is output, which activates the comparator COMP3.

This comparator COMP3 determines whether a match can be obtained by scanning addresses from entry number 1 to previously processed entry number 11 on NAMET in FIG. 8a.
Alternatively, it is determined whether a match is obtained by scanning entry numbers 12 and onwards.

Therefore, the address corresponding to the previously processed entry number 11 (Regisc NAP) is stored in the comparator COMP3.
3) and register N when a match is obtained.
The address of AP1 is applied, the difference between the two is taken, and when the former address is the closest, it is assumed that a match has been obtained between entry number 1 and entry number 11, and output signal C is output.

When the latter address is larger, it is assumed that a match has been obtained at the address after entry number 12, and an output signal C1 is generated.

In this example, LABELI and ADD in the same line of UP
Assume that R1 never matches.

Therefore, the former address and the latter do not match.

In No. 1, which is currently being processed, rMJ is set at the address corresponding to entry number 10, as shown by NAMET in FIG. 8a, so the output signal is C.

get. Output signal C. The comparator COMP4 starts operating.

The comparator COMP4 stores the contents of the address corresponding to the entry number at the time when a match is obtained first, that is, the data of the address part ADDR2 in the data read out to the register NAMETR (NAMET in FIG. 8a). ADDR2 corresponding to M of LABEL2 of the table,
700) and the data in register LAC2 (
The contents of the register LAC2 (820) in FIG. 8b are input, and the value n (n=ADDR2-LAC2) of the relative address DISP mentioned earlier is calculated.

The relative address DISP is the difference between both data, and in the comparator COMP4, the value n of this difference is −128, which means a short word.
It is determined whether the word is ≦n or n≦−129, which means a long word.

When determining a short word, a short word command signal C3 is generated to drive the short word flag generator SFT, and a flag for a short word is generated.When determining a long word, a long word command signal C2 is generated and a long word flag is generated. The generator DFT is driven to generate a flag for long words.

If No=■ is currently being processed, the value n of the relative address DISP
Since n=700-820=120, it is determined that the word is a short word.

When determining a short word, `` is set in the flag section FT of register TR.
0” is set, and when determining a long word, set “1” to the flag section FT.
”.

In this embodiment, "0" is entered in the FT (FT section corresponding to No=■ in the IT table in FIG. 8b).

When a match is not obtained during the scanning from the entry next to the previous entry number to number 11, and a match is obtained during the scanning from entry number 12 onward, the comparator COMP5 is activated by the output signal C1.

This comparator COMP5 has the AD of register NAMETR.
The contents of DR2 and the contents of register LAC1 which stores the contents of LACT (900) corresponding to No.
I) and determine whether it is a short word or a long word based on the difference.

When it is a short word (n≦127), the short word command signal C4, the long word (
When n≧128), a long word command signal C is generated, which drives the short candy flag generator SFT and the long word flag generator DFT, so that the short word flag "0" and the long word flag "1" are set. IT
It will be output to R's FT.

The address of register LAC1 used here is ADDR from entry-1.3 of NAMET in Figure 8a.
This is because 2 has not been corrected.

Simultaneously with or after setting the short word and long word, the AND gate A4 or A5 is opened by the short word command signal C3 or C4 and the long word command signal C2 or C5.

That is, when determining a short word, AND gate A4 is opened and +1
The adder circuit LADD1 adds the register LAC2.
When determining a long word, the AND gate A5 is opened and the adder circuit LADD2 adds +2 to the content of the register LAC2 by +2.

In this embodiment, since the instruction during UP with No=■ is a short word, AND gate A4 is opened and the contents of LAC2 are incremented by 1 (LAC2 in FIG. 8C changes from 820 to 821).

Next, the contents of the register ITR are written and registered in the input section IT and intermediate table section MT.

The contents of the post-registration registers LACI and LAC3 in the last row are compared by a comparator COMP6 which starts operating in response to a command signal C6 generated upon completion of processing of each UP instruction.

If both names match, a termination signal C7 is generated, and if they do not match, a continuation signal C8 is generated, NAPI is set to 10 m, the next row is read from IT to ITR, and the above process is repeated.

No. 1■, which has just finished processing, is not finished yet < (∵
The contents of LAC1 and LAC3 in FIG.
The process will proceed to =■.

At this time, the content of NAP1 is increased to 10m (the corresponding NAP is 12).

In the processing of No=■ (Figure 9), the above-mentioned No.
Since this process is almost the same as the process in step 1, we will omit the redundant parts and explain only the different parts below.

First, the difference is that there is no label in the label section LABELI of the user program UP (No. 1 in the IT table in FIG. 9).

Therefore, there is no need to search whether there is a label in the table NAMET, and there is no need for comparison by the comparator COMP1.

Furthermore, the difference is that the content r of the address part ADDR1
EJ does not exist between entry number "1" and previously processed entry number "l2", but exists at entry number "l4".

The content of entry number 14 is 2000, and 廓=
Since DISP with ■ becomes larger than 128, the comparator CO
At MP3, an output signal C1 is obtained and the comparator COMP5
Then, the register LACI and the register NAMETR address are compared.

As a result of this comparison, n=2000-902=1098, a long word command signal C, is generated, and the long word flag generator DFT
generates a long word flag "1" and sets "1" in the flag section FT of the register ITR (N of the IT table in Figure 9).
FT section of o1)), the contents of register LAC2 are incremented by 2 through adder circuit LADD2 (as a result, LA
C2 becomes 823).

Even when this line ends, the program does not end and processing moves to the next line.

The end of IsT El is shown in FIG. 9e.

LAC2 becomes 821-123 and counts up by the length of the long word.

Since LAC1 and LAC3 do not match, the next line is processed.

Thereafter, each row is processed in sequence.

At the end of the last row, registers LAC2 and LAC3
The contents of the object are compared by COMP7, and if the length of the object does not change between the previous scan and the current operation, the contents of the two match.

At this time, an end signal C7 is generated, and the registered contents from the intermediate table section MT are read out through the register MTR.
The short word/long word machine language converter MI converts it into a machine language format as shown in FIG. 2, and registers it in the output table section OT.

The machine language conversion unit MI sequentially converts instructions M from the intermediate table MT.
Read it to TR and use it as input to output a machine language instruction. In this case, the address part of the word instruction is the relative location from the beginning determined using the short word/long word flag information FT and the label registration table NAMET. The address part of the long instruction is determined by taking the difference from the label location inside, and by using the label location as is.

Is it sufficient to be able to completely divide all lines of the user program into short words/long words in one scan as described above?
In practice, completely correct short/long word classification cannot be achieved by just one scan of all lines of the user program.

For example, in the process of processing instruction No. 1 (2), the label E of the instruction exists in an unprocessed line that has not yet been processed, and the value n of the relative address DISP is set in this unprocessed line.

Because there is a processing process based on the address of these unprocessed lines, which is based on pre-assumptions, it is not possible to correctly and completely determine whether a short word or long word is a word with just one scan. It will not be possible to do so.

Therefore, as a matter of course, Resinuta LAC2 and LAC
3 and the contents of each do not match.

At this time, a signal C is generated and LAC is used for the next scan.
The contents of 2 are transferred to LAC 3, and scanning is started again from the first line of the above-mentioned and <UP.

Figure 9b shows NAP1~ corresponding to the table of NAMET.
C indicates the state of LAC 1 to 3 at the end of scanning, and d indicates the state of LAC at the next scanning.

Naturally, the total number of machine words (objects) to be processed decreases with the number of scans.

FIG. 10 shows this situation.

In Figure 10, 01 is the first scan, 02 is the second scan, y01 is the i-th scan, and 01+i is the total machine language at the (i+1)th scan. It shows the number of words.

As is clear from this figure, as the number of scans increases, the total number of machine language words to be processed decreases (the difference is defined as ε), and when a certain number of times i is reached, the next number of times i +
The difference from 1 is ε=0, and a complete short word/long word match is obtained.

At this time, the contents of registers LAC2 and LAC3 also match.

This completes a complete short/long word decision optimization.

This state is shown in Fig. 9f. In other words, the (n-1st and nth) locations match.

Incidentally, as the number of scans increases, the processing time also increases, which may be a drawback.

Therefore, consideration must be given to terminating the determination process after an appropriate number of runs.

The number of scans is determined depending on whether it is a practical optimization.

In reality, this is done depending on whether the difference between the registers LAC1 and LAC3 is within a practically acceptable range.

That is, Iε is the allowable range. The comparator COMPγ is set to 1, and the difference or ratio between the two registers LAC2 and LAC3 is Iε.

If it is within 1, it is considered to be finished, and if it is outside 1εo1, it is assumed that it is not finished, and the signal C is generated.

This makes it possible to make decisions more efficient and to shorten processing time.

Next, let us explain how the decision time can be shortened.

In the determination of COMP4 and COMP5 in Figure 5, certain types of commands are necessarily short word commands or long word commands, and once it is determined that the command is a short word or a long word, the command can be used again as a short word or a long word. No word judgment is necessary.

Such "certain types of instructions" are defined as if the label of the address field ADDR1 exists before the 128th line (n-129) of that line, or if it exists after the 129th line (n>1).
2s) command (long word command) and address part AD
If the label of DR1 is between that line and the 63rd line before (including the 63rd line) (-64n), or between that line and 63rd line
If it is between the line 4 lines later (including the 64th line), this is the n63rd instruction (a short word instruction).

In other words, among these, the command line teha, which is the long word,
Even in the best case (when all the lines between the instruction line and the line where the specified label exists are short instructions), the relative address DI
The value n of SP is n<-129, n>128, so it can never be a short word.

Furthermore, even in the worst case (when all the lines between the instruction on that line and the line where the specified label exists are long instructions), the relative address n is n>-64. ，
Since n<63, it can never be a long word.

If n is -128<n 65, 64<n<127, there is a possibility that it can be both a short word and a long word, and the length of the command word is undetermined.

In order to realize addressee determination method 2 that takes into account the above points,
First, the flag table section FT of the input section IT has a 2-bit structure instead of a 1-bit structure.

In other words, if it is determined to be a short word, set it to "0," if it is determined to be a long word, set it to "1," and if it is undecided whether it is a short or long word, set it to "2." The temporary word length flag FT for an instruction whose word is not determined is set to "2").

Other registers related to this flag also have a 2-bit configuration.

Furthermore, in the embodiment shown in FIG. 5, the data of the flag section FT is not used, but the data is taken in and set to "0" or "1".
It is necessary to provide a comparison circuit that determines whether it is "" or "2".

Furthermore, this comparison circuit has three outputs, the first output is output when a "0" determination is made, the second output is output when a "1" determination is made, and the third output is output when a "2" determination is made. be done.

When determining "0" and "1", there is no need to calculate the relative address DISP, and only the contents of LAC2 are incremented by +1 and +2.

When the third output occurs, as in the case of FIG. 5, it is determined whether or not there is a label match in the line M starting from the line currently being processed.
If there is a label match before the row currently being processed, COMP4
The value n of the relative address DISP is determined by the comparator corresponding to
is calculated, and based on the calculation results, short words and long words are determined.

If there is a label match after the line currently being processed, COMP5
The value n of the relative address DISP is determined by the comparator corresponding to
is calculated, and based on the calculation result, it is determined whether the word is a short word or a long word.

Furthermore, a generator SFT,D that generates short word/long word flags
In addition to the FT, a third generator is provided which generates a +2 flag.

The output signals of these three generators generate a register ITR.
The present invention has been described in detail above, and according to the present invention, a language processing processor such as an assembler or a compiler When generating object instructions in machine language form from an intermediate output language, it is not necessary to consider whether the intermediate output language is a short instruction or a long instruction, and the time required to determine the instruction word length is shortened. Can be done.

[Brief explanation of drawings]

Fig. 1 shows the format of the user program, Fig. 2 shows the format of the machine language (object), Figs. 3 and 4 are explanatory diagrams of the main parts of the present invention, and Fig. 5 FIG. 6 to FIG. 9 are diagrams explaining the operation of the present invention, and FIG. 10 is a diagram explaining the repetitive calculation. ...Label registration table section, LAC1, LAC2, LAC3...
...Location register, MT...Intermediate output section, OT...Output section.

Claims (1)

[Scope of Claims] 1. When generating object instructions in machine language form from an intermediate output language of a language processing processor such as an assembler or a compiler, in the D-relative address determination method, (a) a provisional word of the instruction in the intermediate output language; The maximum word length that each instruction can take is stored in the flag table section FT, and the relative address of the intermediate output language instruction calculated based on the maximum word length stored in the flag table is stored in a location table. (b) relative address storage of the final instruction of the intermediate output language instructions when each instruction of the intermediate output language instructions is set to the maximum word length; Means LAC3 and LAC1 (c) Calculates a relative address based on the address stored in the location table section LACT for each of the intermediate output language output instructions, and includes at least comparators COMP2 to COMP5 and a register register. ITR, LAC1.2NAM
(d) determining the word length from the calculated relative address and determining the maximum word length stored as a temporary word length in the flag table section FT; Correct and set the determined word length instead of the word length, and calculate relative addresses sequentially for each of the intermediate output language instructions up to the final instruction of the intermediate output a-language instructions based on the revised word length. storage means L for storing
AC2, LACT; and (e) a comparator COMPM that compares the relative address storage value LAC3 of the final instruction of the intermediate output language instructions and the calculated address storage value LAC2 of the final instruction; If the address deviation value obtained by the comparison operation is larger than a predetermined value, the address storage value LAC2 of the final instruction is stored instead of the address value LAC3 of the final instruction, starting from the first instruction of the intermediate output language instructions. A relative address in object instruction generation characterized in that the operations are sequentially executed and the relative address when the address deviation value obtained by the comparison operation is smaller than a predetermined value is set as the relative address of the object instruction. Address determination method. 2. A relative address determination method for generating an object instruction as set forth in claim 1, characterized in that the relative address when a predetermined number of operations are executed is the relative address of the object instruction. 3. In claim 1, the flag table section FT includes a determined word length flag corresponding to each instruction word whose word length is uniquely determined among the intermediate output language instructions.
In addition, for an instruction whose word length is undetermined, an undetermined identification flag corresponding to the maximum word length that the instruction can take is set, and relative addresses are sequentially calculated only for the undetermined word length, and the intermediate output language is Relative address determination method in object instruction generation characterized by determining the relative address of an instruction