JPS5843663A - Binary-coding circuit - Google Patents

Abstract

PURPOSE:To improve resolution of a binary-coding circuit, by considering a level of the before and behind points of a point to be binary-coded, and deciding a slice level. CONSTITUTION:In a circuit which obtains a binary-coded signal by comparing a level of a video signal obtained by a self-scanning type licenser, with a given slice level, levels of the before and behind video signals of a point to be binary- coded are compared, an inclined value being in the vicinity of the point to be binary-coded is derived by an inclination detecting circuit 4, and a corrected inclined value is derived by rectifying this output. On the other hand, the maximum level at which a white level has been detected is compared with a video signal being in the vicinity of the point to be binary-coded, and a video level being in the vicinity of the point to be binary-coded is derived by a video level detecting circuit 7. The corrected inclined value, the video level and the fixed level are inputted to a slice level generating circuit 8, a slice level is generated, is compared with an output of a sample holding circuit 2 by a comparing circuit 9, and is binary-coded.

Description

[Detailed description of the invention] This invention! This is a binarization circuit KW4.

In terms of optical character reading devices and 7 axis
C to rewrite the conveyed form image into a video signal.
Self-scanning line sensors such as OD are widely used.

Conventionally, when a video signal obtained from a self-scanning line sensor was to be binarized, a slice level was set in advance 1, and the level of the slice level and video signal was compared. However, the binarization method KFi has the following drawbacks.

FIG. 1 shows the concept of binarization using the conventional method. Starting from the top, the scanning line for the character "9", the video signal obtained by the scanning, the fixed slice level, and the video signal at a predetermined level are shown. This shows a binarized signal that has been binarized at a slice level of .

When scanning the illustrated remote, self-scanning IT line sensor one line at a time, the white between the black valleys on the scan line tends to cause the level of the video signal to exceed a predetermined slice level. Therefore, when such a video signal vr is binarized, the p1 character line where the white in the black valley is crushed may become abnormally thick, resulting in a decrease in resolution.

Hon f! A was made in view of these shortcomings,
The purpose of this invention is to make the slice level variable depending on the level of the video signal near the point to be binarized, thereby improving the resolution of the binarization circuit.

An embodiment of the present invention will be described in detail below with reference to the drawings.

Figure 2 shows the circuit height of an embodiment of the present invention.
・2・3ij sample hoist circuit, 4#: slope detection circuit, 5Fi rectifier circuit, 6: white level detection circuit, 7Fi video level detection circuit, 8TL slice level generation circuit -
9Fi comparison circuit is shown.

R41・R42tj Positive input terminal resistance of slope detection circuit 4,
x4sld slope detection 1 path 4 negative input terminal resistance, R44°, AE5-sha, □O.

R51/R52/R5Bti Positive input terminal resistance of rearranging circuit 5, R54/R55Fi negative input terminal resistance of dual-current circuit 5, R
Reference numeral 56 indicates a feedback resistor of the rectifier circuit 5, and a diode P for DI-DI rectification.

R71 and R7211 are positive input terminal resistances of the video level detection circuit 7, R73 and R74 and R75fl are negative input terminal resistances of the video level detection circuit 7, and R76 is a feedback resistance of the video level detection circuit 7.

R81/R82/R851d slice level generation circuit 8
The negative input terminal resistance, R84, is the slice level generation circuit 8.
The feedback resistance of , lFi indicates a negative voltage.

The INt'i video signals fcK1 and CKm-CKm are clocked by sample and hold circuits 1 and 2φ3, respectively.

There is a phase shift as shown in FIG. 3.

The hold circuit holds the level of the incoming video signal IN, and is simple:,? The output of the number P circuit 1 is held by the channel P circuit 2tj and the channel P circuit 1. The output of the sample and hold circuit 2 is held by the sample and hold circuit 3rj and CKs.

Since the output of the sample hold circuit 2 is applied to the comparator circuit 9, the sample hole RP path 2 holds the level of the video signal at the point to be binarized.

Further, the sample and hold circuit 1 detects the level of the video signal at the point after the point to be binarized, and the sample and hold circuit 3 and 2
The level of the video signal at the point before the point to be converted into a value should be maintained.

The slope detection circuit 4tj compares the output of the sample hold circuit 1 with the output of the sample hold circuit 3 to find the slope value near the point to be binarized.

Rectifier circuit 5Fi is a circuit that rectifies the output of the slope detection circuit 4 to obtain a corrected slope value.

The white level detection circuit 6ti is a circuit that maintains the highest white level for a long time (specifically, for row #11 or for one sheet).

Video level detection circuit 7tj each sample r circuit 1
- This is a circuit that adds the outputs of 2 and 3 and compares this with the output of the white level detection circuit 6 to find the video level near the point to be binarized.

The slice level generation circuit 8Fi determines the slice level (by the negative input terminal voltage and positive input terminal voltage),
The input terminal voltage fluctuates depending on the corrected slope value output from the rectifier circuit 5 and the video level output from the video level detection circuit 7.

The comparison circuit 9 is a circuit that compares the output of the Sunsol Hall P circuit with the slice level and binarizes it.6,' Next, the operation will be explained.

First, FIG. 4 is a diagram showing CK1*CKse'CKs and the timer of each sample-and-hold circuit 1, 2-5.

Input video signal X applied to sample pulonild circuit 1
It is held in the sample hold circuit 1 by the Mffi clock CIC.

The output of the sample hold circuit 1 is held in the sample hold circuit 2 by the clock CKs, and the output of the sample hold circuit 2 is held in the sample hold circuit 5 by the clock CKs.

Therefore, from each sample hold circuit 1, 2, and 3, the fourth
As shown in the figure, the same waveforms differing only in phase are output.

Next, FIG. 5 is a diagram showing the timing of the clock (Kl-CKI-CKm, the slope value, and the corrected slope value).

The output of Kemple hold 1 path 1 is the positive input terminal resistance Rag
When the output of the sample hold circuit 5 is supplied to the positive input terminal of the tilt detection circuit 4 via the negative input terminal resistor Ram, The slope value as shown in the figure is output.

Note that the point before the point to be converted to the output Fi21+11 of the sample and hold circuit 6 is converted to the output Fi of the sample and hold circuit 1.
The point after the point to be converted to 2m is shown, and in this embodiment, the slope detection circuit 4 is laK, in which the change from white to black is represented by a positive voltage, and the reduction from black to white is represented by a negative voltage.

When the slope value is a positive voltage, the negative input terminal voltage of the rectifier circuit 5 is stable, and the positive input terminal voltage fluctuates in accordance with changes in the slope value.

On the other hand, when the slope value is a negative voltage, the positive input terminal voltage of the Fi rectifier circuit 5 is stable, and the negative input terminal voltage varies according to the change in the slope value.

Since the difference between the voltages at both input terminals of the rectifier circuit 5ij is determined as the corrected slope value, the corrected slope value is the rectified slope value shown in FIG.

Next is Figure 6, clocks CKr, CK3, and CK.

, the video level, the highest level of the white level (output of the white level detection circuit 6), and the timing of the slice level.

First, white level detection circuit 6Fi sample hole r circuit 1
The output of the white level detection circuit 6 is supplied to the positive input terminal of the video level detection circuit 7 via the positive input terminal R. ' On the other hand, the outputs of the temple hold circuits 1, 2, and 5 each have a negative input terminal resistance Ryse Rym・R? It is supplied to the positive input terminal of the video level detection circuit 7 via I.

Since the video level detection circuit 7 uses the difference between the voltages at both input terminals as the video level, the video level as shown in FIG. 6 is output from the video level detection circuit 7, and the negative input terminal W provided to the child.

In addition to the negative input terminal of the slice level generation circuit 8, a correction slope value is applied to a negative voltage via a negative input terminal resistor R81 and a negative input terminal resistor R83. is supplied, and the positive input terminal of the slice level generating circuit 8 is grounded.

Since the slice level generating circuit Elf is a circuit that outputs the difference between the voltages of both input terminals as a slice level, the slice level generating circuit 8 outputs slice levels such as Fllll and 67+.

This slice level is applied to the negative input terminal of the comparison circuit 9, and the output of the sample and hold circuit 2 is applied to the positive input terminal of the comparison circuit 9.

FIG. 7 shows this slice level and the output of the sample-and-hold circuit 2 superimposed at one reference level.

Comparison circuit 9#i compares both input terminal voltages, and outputs a binary signal indicating "1" when the output voltage of sample hold circuit 9 is lower.

Therefore, the output of the comparator circuit 9 is as shown in FIG. 7, 9a. Here, if the period between the rising edge of the clock CK1 and the falling edge of the clock CK is defined as valid, the output of the comparator circuit 9 can be conceptualized as shown in FIG. 7, 9b, and a correct binary signal can be obtained.

As explained above, according to the present invention, the slice level is determined by taking into consideration the levels of the points before and after the power point to be binarized, so the white in the valley of black is crushed, and the dark line with # degree is abnormal. It will no longer become thicker.

Therefore, according to the present invention, it is possible to obtain a binarized signal with high resolution.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the relationship between conventional scanning lines, video No. 46, and binarized signals. FIG. 2 1 is a circuit diagram of an embodiment of the present invention. FIG. 5 is a timing diagram of clock C, Rs, CRs, and CRs. FIG. 4 shows clocks CR1, CR failure, cRs and each sample and hold circuit 1, 2, 3. Timing diagram of output. FIG. 5 is a timing diagram of clocks CRI-CR1 and CRs, slope values, and correction slope values. FIG. 6 is a timing diagram of clocks CR1, CR Mayuzumi, CRm, video level, and slice level timing -0. The seventh factor is clock CRs, CRs-C, Rs, and the input and output timing diagram of the comparator circuit 9. 1.2.5... Sample hold circuit 4... Slope detection circuit 5... Rectifier circuit 6... Level detection circuit 7... Video level detection circuit]]1. ．． ll'°
°−″′Pa″′′1- 9... Comparison circuit (7317) Agent Patent attorney Kensuke Norichika (and 1 other person) Figure 1 (Figure 3) -1)-1) -1+-10-shi÷)-1)-1
t-÷→)-1)-1 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] In a binarization circuit that obtains a binarized signal by comparing the level of the video signal obtained by the self-scanning line sensor with a given slice level, the levels of the video signal before and after the point to be binarized are compared. a slope detection circuit that calculates a slope value in the vicinity of a point to be converted into a value; a rectification tllt circuit 2 that rectifies the output of this slope detection circuit and calculates a corrected slope value;
a video level detection circuit that compares the detected highest level of the white level with the level of the video signal near the point to be binarized and obtains the video level near the point to be binarized; and the correction slope value and the video signal. A binarization circuit is provided with a slice level generation circuit for comparing a level and a fixed level to obtain a stasis level.