JPS5843569A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce photo resist patterning processes by one time less than conventional process and obtain a memory cell in an Hi-C structure with a good accuracy, by performing two times of ion implantations by self-alignment in one time of photo resist patterning process. CONSTITUTION:A thick thermal oxide film 2 to insulate each active element is formed on a P type Si substrate 1, and thereafter a capacitive oxide film 4 to form a memory cell capacity is formed. Thereafter, a photo resist pattern 17 for ion implantation for an Hi-C structure is formed, and boron ion implantation 9 is performed with said photo resist pattern as a mask (fig. a). After finishing the ion implantation, said photo resist pattern 17 is applied to an oxygen plasma treatment, and the fringe of the resist pattern is removed (fig. b). Next, an As ion implantation, As 5 for the Hi-C structure wherein an ion implanted region is wider, is preformed with a photo resist pattern 18 as a mask. Thereafter, a capacitive poly Si 12 is grown, and a gate oxide film 10, gate poly Si 13, an n<+> diffused layer 11, etc. finally are formed resulting in a dynamic memory cell structure in an Hi-C structure shown in the figure.

Description

DETAILED DESCRIPTION OF THE INVENTION This town is a semiconductor device manufacturing method Ilr74! Firstly, there is the field-effect integrated circuit (MO8-IC) memory, semiconductor memory, especially M'os. The increase in the size of xc memory is remarkable, perhaps 4 to 1 in a few years?
It is up to K so that 6 times the capacity can be obtained. When increasing the capacity of such MO8/IC memory, due to the constraints of the pellet area, -! The area of the individual memory cells constituting the IIOS-IC memory becomes smaller in inverse proportion to the size of the memory. In MOS-IC memory, especially dynamic MO8 memory, as the area of the memory cell becomes smaller, the capacity of the memory cell becomes smaller. This means that the charge stored in each memory is small. Second, the load on the circuit, such as increasing the sensitivity of the sense amplifier, increases accordingly.
MO8 Memo 17 - Narrows the IC's circuit operating range and causes problems in circuit design. In addition, if alpha rays are incident on the memory cell, the probability that the information stored in the cell will be lost increases, and there will be a big problem in terms of the reliability of the MO8@IC memory. −ζ+
Una, memo? With the increase in capacity,? Endpage of voice one:1 Memory cell structure K% place @ Hi-C structure memory cell generally proposed for the purpose of solving the problem? There is a le. H
The 1-C memory cell has a large capacitance due to the silane monolayer, and by forming a one-to-one junction capacitance, the memory cell capacity i can be increased, and the fractional carriers generated in the substrate can be recombined in one layer. ζ and k), it is possible to reduce the soft edge by the 1′ line. However, Hj
In order to fabricate a -C structure memory cell, conventionally two ion implantations were performed for n+ and t, each using a different photoresist patterning method, which resulted in a long wafer manufacturing process and increased product cost. The downside is that it is also expensive.

The present invention reduces the photoresist patterning process by 41 times compared to the conventional method by performing ion implantation twice with self-alignment in the BLML (D photoresist turning process).Accuracy: 1... This is an attempt to create a memory dragon with the H1-C structure.

The present invention will be described in detail below with reference to the drawings and compared with conventional methods.

First, a conventional method for manufacturing a memory cell having an H i -C structure will be explained with reference to FIG. Semiconductor substrate, e.g. LDP
・After forming a thick thermal silane film 2 on the die substrate l for the purpose of insulating each active element constituting the MO8 IC,
An oxide film 4 is formed to obtain the memory capacity of the O8-IC dynamic memory.

After that, a photoresist pattern 3 is created to serve as a mask for the first ion implantation to form a Hi-C structure, and the photoresist pattern 3 is used as an i-sk and has a conductivity opposite to that of the substrate l. An impurity such as arsenic 5, for example, is ion-implanted (FIG. 1(a)).

After that, after removing the photoresist pattern, the photoresist pattern 7, which will be used for the second ion implantation.
Then, using the photoresist pattern 7 as a mask, ions of an impurity, such as boron 9, having the same conductivity as the substrate 1 are implanted (see Fig. 1(b)). The cell capacitance becomes 9 because the junction capacitance of the first layer 8 due to the first ion implantation and the second layer 6 due to the second ion implantation is added to the capacitance due to the capacitive oxide film 4, and the area of the cell 5 is small. However, in the conventional method mentioned above, arsenic ion implantation and boron ion implantation must be carried out twice, and boron ion implantation must be carried out twice. ．．
O ion implantation region 1 is arsenic ion f! Even in the planning area, if it is large, is it possible to use a memory cell? The pattern alignment accuracy was expected between the photoresist pattern 7 for the ion implantation process and the photoresist pattern 3 process for the arsenic ion implantation. The disadvantage of having to reduce the amount of leeway in the calculation was revealed.

The present invention provides a manufacturing method capable of manufacturing a memory trench having a Hi-C structure by self-alignment and by adding only one foot resist patterning step.

The present invention will be explained using No. 211. tzu, p 渥81
A thick thermal oxide film 2' for active bare insulation is formed on the substrate 1, and then a capacitor oxide liI4t- is formed to form a memory cell capacitor. After Shikatatsu, H1-C
Form a gate resist pattern 17 for ion implantation in the first structure, and perform ion implantation of the smaller ion implantation region, boron 9 in the case of ζ, using the seven gate resist pattern as a mask. Figure (a)). After the ion implantation is completed, the photoresist pattern 17 is subjected to, for example, oxygen plasma treatment to remove the peripheral edge of the resist pattern (second
Figure <<b>>). When removing the periphery of the butter, K1
Although the resist film thickness also decreases slightly, it does not lose its stability against the next ion implantation. Perform one-element plasma treatment and photoresist head turn 17a
It becomes smaller until the mist pattern 18. Next, using the scissors photoresist pattern 18 as a mask, ions are implanted for the Hi-C structure in the wider ion implantation region, in this case arsenic 5. After that, capacitance polysilicon 1y is grown and gate oxide film is grown. 10. Gate polysilicon 13, diffusion layer 11, etc. are formed to obtain the final Hl-C dynaelectric memory cell structure shown in FIG.

That is, according to the present invention, the photoresist process may be performed one less time than the conventional method, and after one photoresist patterning process, the peripheral edge of the photoresist pattern can be removed. Depending on the person doing the removal,
Since the second ion implantation can be performed to obtain the H1-C structure, there is no need to design with the precision of mask alignment in mind.MO8 has a wide operating range and is highly reliable against all・IC memory can be manufactured.

[Brief explanation of drawings]

Figures 1 (a) and 2) are cross-sectional views for explaining the conventional method, Figures 2 (1) to (C) are cross-sectional views for explaining an embodiment of the present invention, and Figure 3 is a cross-sectional view for explaining the conventional method. H1- created by the invention
FIG. 2 is a sectional view of a main shaft having a C structure. !・・・・・・-p@81 Go board, 2... Field oxidation metal, 3... Fodresist pattern (for arsenic ion implantation mask), 4... Capacity Oxide film, 5
Arsenic ion, 6...more, 7...7 more. Gist pattern (for TM Cao Chi ion implantation mask)
, self..., , ,, , + layer, 9...Pone ion, 1 G-...gate oxide film, 11...
...? Diffusion layer (e.g. digit line), 12...
Capacitive polysilicon, 13...Gate polysilicon, 14...Interlayer insulating film, 15...M
Wiring, 16...M08-IC protective film insulation film, 1
7...7# photoresist pattern (for final ion implantation), 18...Photoresist pattern with the periphery of the 7 photoresist pattern of 17 removed. Susumu Haraendpage:3

Claims (1)

[Claims] (1) Photo 2 trace x 1 strike pattern. Let be the mask, and the first conductivity type! Naru impurity: A material for injecting impurity into the conductive substrate. , 4Maesaki Photoregis 2
After removing the periphery and edges of the pattern. 1. A method for manufacturing a first-in-one inspection device, in which ions of an impurity having a second conductive layer are implanted using the photoresist pattern as a mask. 5
(2) One edge of the pre-beat resist pattern. ? Remove μ. ζ performed using a monoatomic plasma, as described in claim 8jlIl, and cattle 7. Conductor device?
Cape, structure, method. ,