JPS5842972B2 - signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal generation circuit that generates an output signal having a frequency equal to an arbitrary N times the frequency of a reference signal generated from a reference signal source.

In a signal generating circuit that generates an output signal with a frequency equal to N times the frequency of a reference signal, a phase lock circuit is used to obtain an accurate and stable output frequency.

However, when a reference signal and an input signal (for example, the output signal of a voltage-tuned oscillator) are applied to a sampler included in the phase-locked circuit, the frequency of the reference signal or its harmonic signal and the input signal Since the locking operation is performed when the frequencies of these signals reach a certain relationship, frequency locking may occur in many combinations of the frequencies of these signals.

Therefore, in order to obtain an output signal having a frequency equal to the frequency of a specific harmonic among the harmonics of the reference signal, frequency lock must occur only with the specific harmonic signal.

To accomplish this, prior art devices have used multiple filter circuits to prevent frequency locking at undesired frequencies.

That is, the filter circuit is switched in accordance with the selected output frequency so that only a signal having a desired frequency among the output signals of the voltage-tuned oscillator (hereinafter referred to as VTO) is applied to the sampler.

However, such a device requires a large number of complex filters corresponding to the selectable frequency range, and as the selectable adjacent frequency range becomes narrower, it is necessary to use filters with steeper characteristics.

However, designing such a filter is very difficult and the circuit is very complex.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and the present invention merely digitally sets a value related to the harmonic order of a reference signal in a counter, and the frequency is determined only by the reference signal having the harmonic order. The present invention provides a signal generation circuit in which locking occurs, thereby providing an accurate and stable output signal with a frequency equal to the frequency of the desired harmonic of the reference signal.

The present invention will be explained below using the drawings. Output signal FV of a voltage-tuned oscillator (hereinafter referred to as VTO) 5 whose output frequency f changes depending on the magnitude of the control signal (ft to fn)
is applied to one input terminal of a sampler 7, which is a harmonic mixing means, for example.

The reference signal of the reference oscillator 3 (its frequency is assumed to be fS) is applied to the other input terminal of the sampler 7.

The output signal of the sampler 7 is applied to one input terminal of an integrator 17 and a waveform shaping circuit 25 via a low-pass filter (hereinafter referred to as LPF) 9.

The integrator 17 has an input resistor 11 connected to one of its input terminals. Input resistor 2 connected in series to the other input terminal
1, a switch 19 (for example, composed of a field effect transistor), an amplifier 15, and a capacitor 13 connected between the input and output terminals of the amplifier 15.

The output terminal of the integrator 17 is connected to each input terminal of the VTO 5 and the comparator 23.

The output terminal of the comparator 23 is connected to one terminal of the input resistor 21, a frequency detection circuit 27, and a harmonic order determination circuit 33, which will be described later.

The output terminal of the waveform shaping circuit 25 is connected to the input terminal of the frequency detection circuit 27.

Here, the frequency detection circuit 27 is composed of a t-IJ glass pull mono multi-by-break (hereinafter referred to as mono multi) 29 and a D-type flip-flop (hereinafter referred to as FF) 31.

The output signal vF of the waveform shaping circuit 25 is applied to the input terminal of the monomulti 29 and the clock terminal of the FF 31.

Further, the output signal of the comparator 23 is applied to the clear terminal of the FF 31.

The output terminal of the waveform shaping circuit 27 is connected to the harmonic order determining circuit 33.
is connected to one input terminal of the

The other input terminal is connected to the output terminal of the comparator 23.

The harmonic order determining circuit 33 determines a desired harmonic of the reference signal to be mixed with the signal FV in the sampler 7.
AND gate 35, programmable counter 37, R-
It is composed of an S flip-flop 39.

The output terminal of the AND gate 35 is connected to the input terminal of the counter 37, and the carry terminal of the counter 37 is connected to the set terminal of the R-8FF 39.

The output signal of the R-8FF 39 is applied to the switch 19 to open or close the switch 19.

The reset terminals of the counter 37 and the R-8FF 39 are connected to the terminal 36, and are reset by a signal applied to the terminal 36.

The signal generating circuit configured as described above operates as follows.

The operation will be explained below using FIGS. 2 and 3.

FIG. 2 is an explanatory diagram of the operation of the frequency detection circuit shown in FIG. 1.

In order to understand the present invention, the operation of the frequency detection circuit 27 will first be explained.

FIG. 2A shows the output signal F that has been shaped by the waveform shaping circuit 25, and it is assumed that the frequency changes as shown in the figure, such that it becomes lower with the passage of time and then becomes higher.

The monomulti 29 is triggered by the falling edge of the signal vF and the second B
A pulse with the pulse width τ shown in the figure is generated.

FF31 has a monomulti 29 applied to its D input terminal.
When the output signal (Q signal) of is high level, it is triggered by the rising edge of the signal ■F applied to the clock terminal and generates a high level signal, and when the Q signal is low level, the signal vF at that time is triggered. It reverses to a low level at the rise of (Figure 2C)
.

Therefore, the frequency detection circuit 27 performs a time comparison between the time width of the signal vF and the pulse width τ, and the frequency of the signal vF is determined to be f
A high level signal is generated when the frequency is equal to or lower than the frequency determined by =1/2τ.

One signal FD is generated when the frequency of the signal vF changes from high to low to high.

Next, the operation of the harmonic order determining circuit 33 shown in FIG. 1 will be explained.

The counter 37 is a programmable counter whose count value can be preset externally.

For example, assume that the number 7 is preset.

The counter 37 counts the signal FD applied through the AND gate 35, and generates a carry signal TO when the count reaches 10.

Carry signal TO sets R-8FF39 and FF3
9, that is, the output signal v of the harmonic order determination circuit 33
For example, D is a high level signal.

The counter 37 and the R-8FF 39 are reset by a signal applied to the terminal 36.

Here, the preset value is M=9 (NMAX N)
is set to

N is the selected harmonic order (integer), NMAX is VTO5
is the highest order of the reference signal within the frequency band of

Note that when (NMAX N) is 10 or more, the number of digits of the counter is increased.

Next, the overall operation of the signal generating circuit according to the present invention will be explained.

FIG. 3 is an explanatory diagram of the operation of the signal generation circuit shown in FIG. 1.

When the output signal vD of the harmonic order determining circuit 33 is at a low level, the switch 19 is turned on and the output signal Vo of the comparator 23 is integrated by the integrator 17 via the input resistor 21.

Comparator 23 has a positive and negative comparison level, and when the input signal exceeds this comparison level, it generates a rectangular wave signal shown in FIG. 3B.

Therefore, integrator 17 generates the triangular wave signal vT shown in FIG. 3A.

That is, the integrator 17 and the comparator 23 constitute an oscillation circuit.

Since this triangular wave signal vT is applied to VTO5, VT
The frequency of the output signal FV of O5 is swept from f1 to fn.

The signal FV and the reference signal are harmonically mixed by the sampler 7 to generate a signal having a difference frequency between the frequency f of the signal FV and the frequency Nf8 (N is the harmonic order) of the harmonic signal of the reference signal. The signal is applied to LPF9.

When the frequency of the output signal of the sampler 7 becomes lower than the cutoff frequency fo of the LPF 9, an output signal of the LPF 9 is generated, and this output signal is applied to the integrator 17 and the waveform shaping circuit 25.

Here, due to the combination of the frequency of the sweep output signal FV of the VTO 5 and the frequency of the harmonic of the reference signal, a plurality of discrete signals are generated in the LPF 9 during one sweep period of the VTO 5.

This signal is waveform-shaped by the waveform shaping circuit 25 and applied to the frequency detection circuit 27 .

Here, the scheduled frequency of the frequency detection circuit 27 is f of the LPF 9.

Since they are set close to each other, the operation explained in FIG. 2 generates the signal FD shown in FIG. 3C at the output of the frequency detection circuit 27.

The harmonic order determining circuit 33 counts the signal FD when the triangular wave signal vT is in the downward direction due to the action of the AND gate 35.

Now, assuming that the counter 37 is preset to a value of 7, the counter 37 receives three signals FD and generates a carry signal Tc, which causes the harmonic order determining circuit 3
3 generates an output signal vD.

The switch 19 is turned off by the output signal vD, and the VTO5
The sweep operation stops.

At this time, the output frequency f of the VTO 5 is almost close to the frequency obtained by multiplying the reference frequency fs by the harmonic order N determined by the harmonic order determining circuit 33.

After the switch 19 is turned off, an error signal is generated by the sampler 7 in a closed loop consisting of the VTO 5, sampler 7, LPF 9, and integrator 17, and a phase lock operation is performed to adjust the output of the VTO 5 so that f=NfS. The frequency f is controlled.

Therefore, a signal with a frequency equal to N times the reference frequency f can be taken out at the output terminal 1.

Next, explanation will be given using specific numerical values.

Set the frequency band of VTO5 to 490~101101O,, f
S=100MHz.

Let fo-1■h.

NMAX is 10. Assume that we want to obtain an output signal FV of f-800MH2 (eighth harmonic of fS).

M=9-(NMAX-N
)=9-(10-8)7 is preset.

Therefore, the harmonic order determining circuit 33 receives three FD signals as shown in FIGS. 3C and 3D, and outputs a carry signal T as shown in FIG. 3E.

and generates signal D. Therefore, when the signal vD is generated and the sweep of the VTO 5 is stopped, the frequency f of the output signal FV of the VTO 5 has a frequency close to 800 MHz.

Thereafter, a phase lock is applied so that this signal FV and the eighth harmonic signal of the reference signal have the same frequency and a constant phase relationship, and an output signal of f=8f,=800 MHz is obtained.

As is clear from the above explanation, according to the present invention, it is possible to obtain an output signal of a desired frequency simply by digitally setting values related to the frequency of the reference signal and the frequency of the output signal in the program counter. I can do it.

A stable and accurate output signal can then be obtained.

The present invention is highly effective when used in a frequency synthesizer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal generation circuit according to the present invention, and FIG.
The figure is an explanatory diagram of the operation of the frequency detection circuit shown in Figure 1.
This figure is an explanatory diagram of the operation of the harmonic order determining circuit shown in FIG. 1. 3... Reference signal source, 5... Voltage-tuned oscillator, 7.
... Sampler, 9 ... Low-pass filter, 17 ... Integrator, 23 ... Comparator, 27 ... Frequency detection circuit, 3
3...Harmonic order determination circuit.

Claims (1)

[Claims] 1. An oscillator whose output frequency changes according to a control signal, a mixing circuit that mixes a reference signal and the output signal of the oscillator, a low-pass filter that receives the output signal of the mixing circuit, and the low-pass filter. an integrator that integrates an output signal of the low-pass filter and uses the output signal as the control signal; a frequency detection circuit that detects that the frequency of the output signal of the low-pass filter is within a predetermined frequency range; and a programmable counter. a counting circuit that counts the output signal of the frequency detection circuit and generates an output signal when the counted value reaches a predetermined value; and a counting circuit that receives the output signal of the integrator and receives the output signal of the counting circuit. a signal generating circuit comprising: a circuit for controlling the integrator and thereby causing the oscillator to sweep oscillate;