JPS584293B2 - Weighing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an apparatus for weighing lump articles such as root vegetables, vegetables, cheese for spinning, etc. to a predetermined number (boxed number) and a predetermined weight. relates to a weighing device that is not affected by variations in unit weight of items and keeps the total weight of an arbitrarily set quantity within an allowable error range.

Conventionally, when a predetermined number of items are packed in one box, if there is variation in the weight of each item (hereinafter referred to as unit weight), the total weight of the individual boxes will also vary. However, in this type of packaging work, variations in the total weight of each box are always a problem.

Therefore, as a countermeasure to this problem, the total weight is adjusted by adjusting the number of boxes packed to match the total weight, or by replacing the items using the difference in unit weight.

However, the former method often restricts the number of items packed in a box, and the latter method makes it very difficult to replace items. It is inevitable that variations will occur.

Therefore, since the stock is constantly traded at a positive (plus) weight, the loss is considerable.

In addition, when the number of items packed in one box is large, in order to weigh a predetermined number of items and a predetermined weight in one combination calculation, the number of items required for the combination calculation is (1.5 to 2) in terms of accuracy. n
Since the number of boxes (n) changes depending on the product, programming for this combination calculation is complex and expensive, both in terms of electrical circuits and mechanisms such as weighing devices, loading/unloading devices, etc. This is virtually impossible.

The present invention improves and eliminates the above-mentioned drawbacks of the conventional art, automatically processes the above-mentioned manual work, and utilizes the unit weight difference to produce a predetermined quantity of assortments, and also to minimize the amount of addition of the total weight to zero. This allows for labor savings, reduced losses, and quick packaging.

Hereinafter, the configuration of the present invention will be explained with reference to the drawings.

In Fig. 1, 1 is a first conveyor, 2 is a second conveyor for sorting, and 3 is a first weighing device installed between both conveyors 1 and 2. (not shown) from the first conveyor 1 to the first weighing device 3, its weight is weighed and then sent to the second conveyor 2 by said transfer means.

4 is an ejector for discharging items other than the allowable error weight; 5 is an ejector for discharging items having a positive allowable error weight;
Reference numeral 6 denotes a discharge device for discharging articles having a negative tolerance weight, and each of the discharge devices uses a set of air cylinders, for example, and is installed to operate perpendicularly along the running direction of the second conveyor 2. be.

7 is a discharge conveyor for discharging items other than the allowable error weight; 8 is a positive line conveyor for sending items having a positive tolerance weight to a second weighing device 9; and 10 is a conveyor for discharging items having a negative tolerance weight. A negative line conveyor for sending to the third measuring device 11, all of which are perpendicular to the side surface of the second conveyor 2, and are connected to the ejectors 4, 5, 6.
It is located opposite.

12 is a positive line stock conveyor for storing the items weighed by the second scale 9; 13 is a negative line stock conveyor for storing the items weighed by the third scale 11. It's a conveyor.

Reference numeral 14 designates a discharger for discharging the items on the plus line stock conveyor 12 onto the accumulation conveyor 15, and numeral 16 denotes a discharger for discharging the articles on the minus line stock conveyor 13 onto the accumulation conveyor 15.

17 is a chute, and 18 is a box conveyed below the chute 17, for example, by a conveyor (not shown).

In FIG. 2, numeral 19 is a sorting circuit which receives the output of the first weighing device 3, and uses the average unit quantity input Three types of selection are performed: whether the average unit weight X divided by X is within the allowable error of plus (including zero error weight), minus minus, or outside the allowable error.

Then, depending on the sorting result, the sorting circuit 19 outputs the ejector 4.
, 5, and 6 are operated to discharge the articles on the second conveyor 2 onto the corresponding conveyors 7, 8, and 10.

20 and 21 are A-D converters for converting the error weight signals of the second and third weighing devices 9 and 11, respectively, into BCD codes,
Each output is connected to a positive register 22 and a negative register 23.

Both registers 22 and 23 each have a capacity to store four pieces of data, and each piece of data is connected to an arithmetic circuit 24.

Reference numeral 25 denotes a box quantity setting unit, which sets the number of pieces per box, such as 5, 10, or 20 pieces, using a dial type, push button type, etc.
This is for setting the number of items to be packed in a box.

Therefore, by setting the number of boxes, the total weight can be determined.

Reference numeral 26 denotes a combination code operation number setting circuit which receives the output of the packaging quantity setting unit 25. The packaging quantity setting unit 25 sets the packaging quantity, and the output determines the positive and negative side registers 22, 5 out of 23 total 8 codes
This is to determine how many individual combination code operations should be performed, how many times four combination code operations should be performed, and how many three combination code operations should be performed.

In other words, as shown in the table in Figure 4, for an integer number of 3 or more boxes, it can be obtained by combining 5, 4, and 3, so for example, in the case of 22 pieces, the 5 piece combination code It is determined that the number of calculations is three, the number of four-piece combination code calculations is one, and the number of three-piece combination code calculations is once.

Note that the codes are X1, X2, X3,
The numbers X4, X5, X6, X7, and X8 do not represent the error weights themselves.

In addition, the number of times of combination code operations means that the storage capacity of both registers 22 and 23 is now 8 in total.
The combination of 5 is (X1+X2+X3+X4+X5), (
X1+X2+X3+X4+X6), (X1+X2+X3
+X4+X7), ・・・・・・・・・・・・(X4+
There are a total of 56 combinations such as (X5 + X6 + X7 + The number of operations and the number of three-piece combination code operations are 70 and 56, respectively.
This means that you should do it as many times as you like.

Reference numeral 27 denotes a 5-combination code operation number control section, 28 a 4-combination code operation number control section, and 29 a 3-combination code operation number control section, each of which is constructed as follows.

In other words, the 5-piece combination code operation number control unit 27 has 56
5-piece combinational code circuit 271 consisting of the same combinational circuits
The output of the AND circuit 272 is connected to the input of the AND circuit 272.

Then, the output of the five combination code operation number detection circuit 273 and the output of the combination code operation number setting circuit 26 are respectively connected to the input of the coincidence circuit 2740, the output thereof is connected to the NOT circuit 275, and the output is connected to the AND circuit 272 and the output of the combination code operation number setting circuit 26. AN
Connected to each input of the D circuit 276.

Similarly, the 4-piece combination code operation number control section 28 and the 3-piece combination code operation number-of-time control section 29 operate on the 4-piece combination code circuit 281 and the 3-piece combination code circuit 291, which are respectively composed of 70 combinations and 56 combinations. Each output is A
Connected to the inputs of the ND circuits 282 and 292.

Then, the output of the combination code operation number setting circuit 26 and 4
The output of the individual combination code operation number detection circuit 283 and the output of the three combination code operation number detection circuit 293 are connected to the inputs of the corresponding matching circuits 284 and 294, and each of these outputs is connected to the NOT circuits 285 and 295. , their respective outputs are connected to AND circuits 282, 286 and AND circuit 292,
296 inputs.

The outputs of the AND circuits 272, 282, and 292 are connected to the inputs of the OR circuit 30, and the outputs thereof are connected to the arithmetic circuit 24 and to one input of the AND circuit 31.

On the other hand, the output of the coincidence circuit 274 of the 5-piece combination code operation number control section 27 is combined with the AND circuit 282 of the 4-piece combination code operation number control section 28 and the 3-piece combination code operation number control section 2.
9 AND circuits 292 and NAND circuits 32 are connected in parallel to each input, and the output of the matching circuit 284 of the 4 combination code operation number control section 28 is connected to the AND circuit 292 of the 3 combination code operation number control section 29 and the NAND circuit. 32, and further, the output of the matching circuit 294 of the three-piece combination code operation number control section 29 is connected to the input of the NAND circuit 32.

Each combination code operation number detection circuit 273, 283
293 counts the number of operations, and outputs this count from the output of each combination code operation number from the combination code operation number setting circuit 26 to corresponding matching circuits 274, 284,
294, and when both outputs match, each matching circuit 27
The output of 4,284,294 becomes "H" level.

When they do not match, the output becomes "L" level.

Further, if the output from the combination code operation number setting circuit 26 is zero, that is, there is an output indicating that no operation is necessary, the corresponding matching circuits 274, 284, 29
The output of No. 4 is configured to be at "H" level.

33 is a memory circuit for storing the packaging start signal a, and this signal a is connected to the set input s, and the reset input R is connected to the set input s.
The output of the NAND circuit 32 is connected to.

Then, the Q output of this memory circuit 33 is connected to one input of the AND circuit 34, and via the differentiating circuit 35,
Each of the above-mentioned 5 pieces, 4 pieces, and 3 pieces combination code operation number detection circuit 2
73, 283, 293 and each reset input of a second register 60, which will be described later, are connected in parallel.

The memory full signal b from the plus side and minus side registers 22 and 23 is connected to the other input of the AND circuit 34.

36 is a differentiation circuit which receives the output of the AND circuit 34;
7 is a storage circuit for storing the calculation end signal c each time,
The output of the differentiating circuit 36 is connected to the set input S, and the calculation end signal c is connected to the reset input R.

Then, the Q output is connected to each input of AND circuits 39 and 40 via a differentiating circuit 38, and also connected in parallel to the reset input R of the memory circuit 42 via a NOT circuit 41, and the other (2) output is connected to the AND circuit 43. , 440 are connected in parallel to each input, and an AND circuit 46 and 5, 4, and 3 combination code operation number control units 27 and 2 are connected in parallel to each input.
It is connected in parallel to each input of each AND circuit 276, 286, 296 of 8 and 29.

The differentiating circuit 35 outputs an "H" level trigger pulse when the Q output of the storage circuit 33 changes from "L" to "H" level, and the differentiating circuit 36 outputs a "H" level trigger pulse when the output of the AND circuit 34 changes from "L" to "H" level.
When the level changes to "H", a trigger pulse of "L" level is output, and the differentiating circuit 38 and the differentiating circuit 45 output the trigger pulse of the "L" level.
When the Q output and the ■ output of the
Each of them is configured to output a trigger pulse of "H" level (see FIG. 3).

47 is for setting the allowable error weight at the end of each intermediate combination code calculation (for example, in the case of 5 combination code calculations, 56 combination code calculations) excluding the allowable error weight of the final total weight. intermediate tolerance weight setting circuit,
48 is a total allowable error weight setting circuit for setting the total allowable error weight for the final total weight when all combination code calculations are completed, and the allowable error weight in the latter is set smaller than that in the former. It has been done.

49 is a final operation detection circuit that detects the start of the last operation among all combination code operations.

Then, the output of this final operation detection circuit 49 is connected to one input of an AND circuit 50, and is also connected in parallel to one input of an AND circuit 52 via a NOT circuit 51.

On the other hand, the output of the intermediate tolerance weight setting circuit 47 is connected to the other input of the AND circuit 52, and the output of the total tolerance weight setting circuit 48 is connected to the other input of the AND circuit 50. Each output of 52 is connected to an input of an OR circuit 53.

54 is a first comparison circuit, and 55 is an AND circuit, in which the output of the arithmetic circuit 24 is connected to the input of the first comparison circuit 54 and also to one input of the AND circuit 55.

Then, the output of the OR circuit 53 is connected to the other input of the first comparison circuit 54, and the output of the first comparison circuit 54 is connected to the output of the first comparison circuit 54.
It is connected to the other input of the ND circuit 55 and also connected to the set input s of the memory circuit 42 via the NOT circuit 56.

The first comparison circuit 54 compares the calculation result of each combination code performed by the calculation circuit 24 with each permissible error weight set by the intermediate permissible error weight setting circuit 47 or the total permissible error weight setting circuit 48. It is something to do.

57 is the second comparison circuit, 58 is the AND circuit, and 59 is the first comparison circuit.
60 is a second register, and 61 is a code storage register.

Then, the output of the AND circuit 55 is connected to the input of the second comparison circuit 57 and also connected to one input of the AND circuit 58, and the output of the second comparison circuit 57 is connected to the input of the two AND circuits.
It is connected in parallel to the other input of the circuits 31 and 58.

The second comparison circuit 57 compares the calculation result of the calculation circuit 24 with the error weight stored in the first register 59, and the first register 59 compares the minimum error weight of each calculation result. Furthermore, the code storage register 61 is used to store the combination code resulting in the minimum error weight.

d is a preset signal for presetting all the first registers 59 to "I", and is connected to the other input of the AND circuit 40, and the output of this AND circuit 40 is input to the preset input of the first register 59. Connecting.

Then, the output of the AND circuit 58 is transferred to the first register 59.
, and its output is fed back to the second comparison circuit 57 and connected to one input of the AND circuit 46 .

On the other hand, the Q output of the storage circuit 42 is input to each AN of the 5, 4, and 3 combination code operation number control units 27, 28, and 29.
It is connected in parallel to one input of the D circuits 276, 286, and 296, and also connected in parallel to one input of the AND circuit 46.

Then, the output of this AND circuit 46 is connected to the input of the second register 60, and this output is connected to the input of the arithmetic circuit 24.

This second register 60 is for storing the minimum error weight of the previous combination code calculation, and the calculation circuit 24 takes this output into account, that is, corrects it and calculates it.

In addition, if the (1) output of the memory circuit 42 is connected to the other input of the AND circuit 44, and the output e of this AND circuit 44 is determined to be within the allowable error range in one operation, At the end of all calculations, it is taken out as an alarm signal.

f is a preset signal for presetting all the code storage registers 61 to "O", and is connected to the other input of the AND circuit 39, and the output of this AND circuit 39 is connected to the preset input of the code storage register 61; AN
The outputs of the D circuits 31 are connected to the inputs of the code storage registers 61, and the outputs of the code storage registers 61 are connected to the A circuits.
Connected to the other input of the ND circuit 43, this AND circuit 4
3 is sent to the ejectors 14 and 16 as an ejection signal g,
Activate the appropriate ejector 14, 16.

At the same time, it is sent as an erase signal h to the plus side and minus side registers 22 and 23 to designate the corresponding storage contents.

The code storage register 61 is used to store a code combination resulting in the minimum error weight among each combination code operation.

62, 63, and 64 are AND circuits, which connect the other output of the 5-piece combination code circuit 271, the output of the NOT circuit 275, the other output of the 4-piece combination code circuit 281, and the NO circuit.
The output of the T circuit 285, the other output of the three combination code circuit 291, and the output of the NOT circuit 295 are respectively input.

65 is a NOR circuit, and the AND circuit 6
The respective outputs of 2, 63, and 64 are connected to the input, and the output is connected to the reset input R of the memory circuit 37 as the calculation completion signal c for each time as described above.

The operation of the present invention having the above structure will be explained as follows.

The items sent by the first conveyor 1 are sent one by one to the first weighing device 3 by a transfer means (not shown), and the weight of the items is measured by the first weighing device 3.

A sorting circuit 19 compares this weight with the average unit weight
, 6 is the positive line conveyor 8, negative line
The other items are sent to the conveyor 10 and the other items are sent to the ejector 4.
is discharged to the discharge conveyor 7.

Next, the items on both line conveyors 8, 10 are sent to the second and third weighing devices 9, 11 by a transfer means (not shown), the error weight with respect to the average unit weight X is measured, and this weight value is calculated. It is converted into a BCD code by A-D converters 20 and 21, and the positive error weight is stored in the positive register 22 and the negative error weight is stored in the negative register 23, respectively.

Then, weighing is performed until the error weight is stored in a total of 8 capacities of both registers 22 and 23, and when both registers 22 and 23 are full, the weighing is stopped and A
A memory full signal b is sent to the ND circuit 34.

At this time, the positive line and negative line stock conveyors 12, 13 are stopped, and each of four items is placed thereon.

Next, when the number of boxes to be packed is set to, for example, 22 pieces in the boxed pieces number setting section 25, the fourth
As shown in the table in the figure, signals are sent to each coincidence circuit 274, which performs three combination code operations for 5 combination codes, once for 4 combination code operations, and once for 3 combination code operations, respectively.
284, 294.

Then, when the packaging start signal a is externally sent manually or automatically to the set input S of the memory circuit 33 as shown in Fig. 3A, the Q output changes to the "H" level (Fig. 3A). B).

At this time, each input of the NAND circuit 32 is at the "L" level, and its output is at the "H" level.

On the other hand, the output of the differentiating circuit 35 is as shown in FIG.
A trigger pulse of "H" level is output, and with this pulse, each of 5, 4, and 3 combination code operation number detection circuits 273,
283, 293 and second register 60 are each reset.

At the same time, the output of the AND circuit 34 becomes "H" level, the output of the differentiating circuit 36 outputs a trigger pulse of "L" level as shown in FIG. Changes to "H" and "L" levels (see Figure 3)
.

Then, the output of the differentiating circuit 38 outputs a trigger pulse of "H" level as shown in FIG.
, d are passed through AND circuits 39 and 40, respectively, and all first registers 59 are filled.

"I" respectively presets all code storage registers 60 to "O".

At the same time, the Q output and ■ output of the memory circuit 42 are set to "L", respectively.
Reset to "H" level (Fig. 3 O).

Further, no trigger pulse is output from the differentiating circuit 45 as shown in FIG.

On the other hand, at the same time as the packaging start signal a is input, the first combination code X1+X2+X3+X4+X5 is calculated in the calculation circuit 24 according to the combination code set in the five-piece combination code circuit 271, and this total value, that is, the error weight The first comparison circuit 54 compares whether the total value is within the intermediate tolerance weight range set in advance by the intermediate tolerance weight setting circuit 47, and if it is within the range, the total value is ANDed.
It is sent to a second comparator circuit 57 through a circuit 55.

Then, the Q output and ■ output of the memory circuit 42 are set to "H" and "L" levels, respectively, as shown in FIG. does not change.

At this time, all of the first registers 59 have already been preset to "I" by the trigger pulse of the differentiating circuit 38 as described above, so the first calculation result is unconditionally transferred to the second comparator circuit 57. , that is, AND circuit 58
, and is sent to the first register 59 to replace the stored contents therein.

The contents of the first register 59 are as described below.
When all calculations are completed each time, “H
” level trigger pulse (Fig. 4 H) is applied to the AND circuit 46.
is sent to the second register 60 only when it is sent to the second register 60.

On the other hand, at the same time, five combination code circuits 271, 272, 272, 30,
The current operation code 1 sent through the AND circuit 31
1111000 (i.e. X1, X2, X3, X4X5
) is memorized.

Next, the second computation of X1 + X2 + X3 + X4 + If it is within the range, this total value is sent to the second comparison circuit 57, and the second comparison circuit 57 compares it with the first total value previously stored in the first register 59. be compared.

If the second total value is smaller in absolute value than the first, then this second total value is smaller than the first total value.
register 59, and replaces the first total value.

At the same time, the code storage register 61 also stores the second code 1.
1110100 (that is, X1, X2, X3, X4,
6), this second code is stored.

Contrary to the above, if the second total value is larger in absolute value than the first, the third operation, that is, X1+X2+X3+X4+X7 is performed, and the first register 59 is set to the first value. As for the total value, the code storage register 61 also continues to store the first code.

Further, as a result of the comparison in the first comparator circuit 54, if the second total value is not within the intermediate tolerance weight range, the third calculation is immediately performed, and at this time, the first register 59 , the contents stored in the code storage register 61 remain unchanged.

In this way, the combination code calculations are sequentially performed by the calculation circuit 24.
Each time, the first comparison circuit 54 compares whether or not the weight is within the intermediate allowable error weight range, and the first register 54 stores the value of the minimum error weight from the previous calculation. 59 in the second comparison circuit 57, and based on the result, the stored contents of the first register 59 are updated, the value of the minimum error weight is stored, and at the same time, the value of the code storage register 61 is updated. The stored contents are also updated, and the code for the minimum error weight value stored in the first register 59 is stored.

And the final 56th operation X4+X5+X6+X7+
X8 is performed in the same way, and when it is completed, the operation end signal c is sent from the 5-piece combination code circuit 271 through the AND circuit 62 and the NOR circuit 65 to the reset input R of the memory circuit 37.
(Figure 3).

As a result, the memory circuit 37 is reset, and its Q output,
■The output changes to "L" and "H" levels as shown in FIG. The value of the minimum error weight stored in the second register 60
, and stores the minimum error weight due to the current combination code calculation, and sends one pulse to the 5 combination code calculation number detection circuit 273 via the AND circuit 276.
It is stored that the individual combination code operation has been completed once.

At the same time, the output of the memory circuit 37 and the signal of the code storage register 61 are used to output a discharge signal g and an erase signal h from the AND circuit 43 (see FIG. 3). The corresponding ejector 14 according to the combination code of the minimum error weight by combination code calculation
.

At the same time, the positive side and negative side registers 22,
23 is deleted.

Next, the items are weighed again by the second and third weighing devices 9, 11 for the number of erased memory contents, and the items are sent to the plus line and minus line stock conveyors 12, 13, and the measured error weight is Save the value to both registers 22 and 23
to be memorized.

At this time, the error weight values that have not been erased are sequentially X1 to X2, X2 to X3, X3 to X4, and X5 to X6.
It is shifted and re-stored from X6 to X7 and from X7 to X8.

Then, when the memories in both registers 22 and 23 become full again, the memory full signal b is sent to the AND circuit 34 (
With this signal b and the Q output of the memory circuit 33, a trigger pulse is output again from the differentiating circuit 36 as shown in FIG. All the registers 59 of 1 are preset to "I", all the code storage registers 61 are preset to "O", and the memory circuit 42 also sets the Q output and the ■ output to "L" and "H", respectively, as shown in FIG. ” level.

Then, the second five-piece combination code calculation is performed again as described above.

However, in the second and subsequent calculations, the minimum error weight in the first calculation stored in the second register 60 is fed back to the calculation circuit 24, and this is taken into account, that is, corrected. Perform calculations.

In this way, when the calculation is performed the same number of times as the number of 5 combination code calculations set by the combination code calculation number setting circuit 26, the output of the matching circuit 274 becomes "H" level, and as a result, the NOT circuit 275 The output becomes "L" level, and the output of the 5-piece combination code circuit 271 is AND
It cannot pass through the circuit 272, and henceforth, no 5-piece combination code operation will be performed.

Also, the trigger pulse of the differentiating circuit 45 (
Since the trigger pulse h) in FIG. 3 cannot pass through the AND circuit 276, this trigger pulse will not be counted by the five-combination code operation count detection circuit 273 thereafter.

Then, when the 5, 4, and 3 combination code calculations are completed each predetermined number of times as described above according to the set number, at this time,
The output of each matching circuit 274, 284, 294 becomes "H" level, and the output of the NAND circuit 32 becomes "L" level, and this output resets the memory circuit 33 as a complete operation completion signal (Figure 3). The Q output changes to the "L" level as shown in FIG. 3B, and the packing operation for one box is completed.

Therefore, the minimum error weight stored in the second register 60 at the end of the final calculation indicates the packing error weight of the total weight in the packaging.

Of the total number of calculations, when starting the final calculation, the total permissible error weight set by the total permissible error weight setting circuit 48 based on the output of the final calculation detection circuit 49 is determined by the AND circuit 60, O.
It is sent to the first comparison circuit 54 via the R circuit 53, and only during the final calculation, the range of the total allowable error weight and the total value calculated by the calculation circuit 24 are compared in the first comparison circuit 54. be done.

To carry out the next packing, the positive and negative registers 22 and 230 are filled up, and the packing start signal a is externally sent to the memory circuit 33 to repeat the above operation.

The above operation has been explained for the cases where the number of 5-, 4-, and 3-piece combination code operations is performed at least once each, but for example, when the number of 4-piece combination code operations is set to zero, the above As shown, the output of the matching circuit 284 is already at the "H" level, and when the 5-piece combination code calculation is completed a predetermined number of times, the 3-piece combination code calculation is performed next, and
For example, when the number of 4-piece and 3-piece combination code calculations is set to zero, each output of the matching circuits 284 and 294 is already at the "H" level, and the 5-piece combination code calculation is performed a predetermined number of times. It will be easily understood that when all the calculations are completed, the "L" level output from the NAND circuit 32 is sent to the reset input R of the storage circuit 33 as the completion signal for all calculations.

Further, in each combination code calculation, the results of the combination code calculation corresponding to one time are sent to the first comparison circuit 54.
When all of the weights are out of the set range of the allowable error weight, a set signal is sent from the first comparison circuit 54 to the storage circuit 42 at least once from the start to the end of this calculation. Since there is no output, its Q output and ■ output are "L", respectively.
It remains reset to the "H" level.

In other words, it remains reset by the trigger pulse of the differentiating circuit 38 that is issued at the start of calculation (dotted line in FIG. 3).

Therefore, an alarm signal e is outputted from the AND circuit 44 as shown by the broken line in FIG. Calculation number detection circuit 273, 283,
The output of the differentiating circuit 45, which is the computation end signal, is prohibited from being sent to 293.

At this time, all the code storage registers 61 remain preset to "O", so the discharge signal g and the erase signal h are not output from the AND circuit 43.

Then, new error weights are stored in the plus side and minus side registers 22 and 23, and the same combination code calculation is performed again.

At this time, the trigger pulse is output from the differentiating circuit 38 as described above with the memory droplet signal b of both registers 22 and 23 (FIG. 3), but since the memory circuit 42 remains reset, its Q output, ■The output remains at the "L" and "H" levels (Fig. 3, O).

Next, explanation will be given based on specific numerical values.

Now, assuming that the number of boxes is 22, the total weight of the boxes is 33kg, the intermediate tolerance weight is ±20g, and the total tolerance weight is +10g and -0g, the average unit weight is 33kg÷22 pieces = 1.5kg, and Fig. 4 From the table, the number of times of 5, 4, and 3 combination code operations are 3, 1, and 1, respectively.

Then, the average unit weight was 1.5k on the second and third scales 9 and 11.
The error weight for g is measured, and the error weight is sequentially stored in the plus side and minus side registers 22 and 23, and the error weight becomes the minimum error weight, and +71g, +10g, +8g, and the minus line stock conveyor 12 are weighed. -25g, -65 from stock conveyor 13
The items having respective error weights of g are discharged onto the accumulating conveyor 15.

At this time, the number of pieces discharged is 5 pieces, the error weight E1=-1 g, and the total weight is 7499 g.

Next, it is assumed that the item is weighed three times using the second weighing device 9 and twice using the third weighing device 11, and the results are as follows.

Then, in the same way, the second 56 calculations are performed by adding the previous error weight E1 = -1g, that is, by correcting it. Similarly, it is discharged onto the collection conveyor 15.

At this time, the total number of pieces discharged up to the second time is 10 pieces, error weight E2 = +3g, total weight is 1500g x 10 + E2 = 1
It becomes 5003g.

Then, a third weighing was carried out, and the results were Suppose it was.

Similarly, 56 calculations are performed for the third time by correcting the error weight E2=+3g up to the previous time, and becomes the minimum error weight up to the third time, and the corresponding items are similarly discharged.

At this time, the total number of pieces discharged up to the third time is 15 pieces, error weight E3 = -1g, total weight is 1500g x 15 + E3 = 2
It becomes 2499g.

Next, the fourth weighing result is Suppose it was.

Here, 4 combination code calculations (70 ways) are performed by correcting the error weight E3=-1g up to the previous time, and the following becomes the minimum error weight up to the fourth time, and the corresponding item is discharged.

At this time, the total number of pieces discharged up to the fourth time was 19 pieces, error weight E4 = -16g, total weight was 1500g x 19 + E4 =
It becomes 28484g.

Next, the result of the 5th weighing is the minimum error weight until the 5th, that is, the final weighing.
Dispose of the corresponding items in the same way.

At this time, the total number of pieces discharged until the fifth time, that is, the last time, is 22 pieces, the final error weight E5 = +2 g, and the total weight is 150 pieces.
0g×22+E5=33002g.

As a result, the number of items packed in one box is 22, and the total weight of each box is 33.
002, resulting in an error of +2g.

Also, each error weight (E1), (E2) up to the 4th time
, (E3) and (E4) are within the range of the initially set intermediate tolerance error weight ±20g, and the final error weight (E5) is also within the range of the total tolerance weight +10g and -0g.

In the above embodiment, the positive side and negative side registers 22
, 23 have a storage capacity of 4 each, for a total of 8, but the number is not limited to this number.

Further, although the error weight with respect to the average unit weight X is stored in both registers 22 and 23, the unit weight may also be stored.

At this time, a division circuit is incorporated in the arithmetic circuit 24, and the total weight obtained by each combination code calculation is divided by the number of pieces at that time to calculate the average unit weight at that time, and the original average unit weight set in the sorting circuit 19 is calculated. The calculation circuit 24 calculates the error in the average unit weight of each time obtained by the calculation circuit 24 for X, and the sum of this error and the total error weight up to the previous time stored in the second register 60 is calculated as the first The comparison circuit 54 may compare the intermediate allowable error weight or the total allowable error weight set by the intermediate allowable error weight setting circuit 47 or the total allowable error weight setting circuit 48.

As explained above, according to the present invention, variations in the unit weight of items do not affect the measurement accuracy, and it is possible to weigh a predetermined number of items, a predetermined weight, or the closest to a predetermined weight with extremely high accuracy, and to Since the error weight in the calculation is taken into consideration in the next calculation, that is, corrected, the weighing error can be minimized even if the number of combination code calculations increases.

Furthermore, since the register that stores the unit weight error or unit weight of the item is provided with a shift function, a plurality of items can be weighed one after another with one weighing device, and the device itself can be manufactured at a low cost.

Furthermore, even if the weight of the item is linearly biased, the positive line
Since each item is stored on a negative line conveyor, there is no problem with calculations.

Furthermore, even if the predetermined number of units is large, the calculation is performed in multiple steps, so the electric circuit and mechanism can be manufactured easily and at low cost.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of a weighing system to which the present invention is applied;
The figure is a block circuit diagram of the present invention, and FIG. 3 is an operation waveform diagram. FIG. 4 is a table showing the relationship between the number of boxes and the number of combination code operations. 22... Plus side register, 23... Minus side register, 24... Arithmetic circuit, 25
... Packing number setting unit, 26... Combination code operation number setting circuit, 27... 5 pieces Combination code operation number control unit, 28... 4 pieces Combination code operation number control unit, 29...3 Combination code operation number control unit, 47...Intermediate allowable error weight setting circuit, 48...Total allowable error weight setting circuit ,5
4...First comparison circuit, 57...Second comparison circuit, 59...First register, 60...
...Second register, 61...Code storage register.

Claims (1)

[Claims] 1 A conveyor that forcibly transports items to a weighing machine, a weighing machine that receives and weighs items from the conveyor, a stock conveyor that stores weighed items, and a conveyor that stores selected items on the stock conveyor. It consists of a plurality of ejectors that push out the items in the opposite direction, and an accumulation conveyor that receives the items pushed out by the extruders, and the conveyor
A weighing device characterized in that a weighing machine, a stock conveyor, a discharger, and a collection conveyor are arranged on the same level, and a combined weighing section is constituted by the weighing machine, the stock conveyor, and a plurality of dischargers.