JPS5848845B2 - Weighing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a method for weighing bulk articles such as root vegetables, vegetables, or cheese for spinning to a predetermined number (boxed number) and a predetermined weight. relates to a weighing method that is not affected by variations in the unit weight of items and keeps the total weight of an arbitrarily set quantity within an allowable error range.

Conventionally, when a predetermined number of items are packed in one box, if there is variation in the weight of each item (hereinafter referred to as unit weight), the total weight of the individual boxes is also bulk. However, in this type of packaging work, variations in the total weight of each box are always a problem.

Therefore, as a countermeasure to this problem, the total weight is adjusted by adjusting the number of boxes packed to match the total weight, or by replacing the items using the difference in unit weight.

However, the former method often restricts the number of items packed in a box, and the latter method makes it very difficult to replace items. It is inevitable that variations will occur.

Therefore, since the stock is constantly traded at a positive (plus) weight, the loss is considerable.

In addition, when the number of items packed in one box is large, in order to weigh a predetermined number of items and a predetermined weight in one combination calculation, the number of items required for the combination calculation is (1.5 to 2) in terms of accuracy. n
Since the number of boxes (-) varies depending on the product, programming for this combination calculation is complex and expensive, both in terms of electrical circuits and mechanisms such as weighing devices, loading/unloading devices, etc. This is practically Fumachi Noh.

The present invention improves and eliminates the above-mentioned drawbacks of the conventional art, automatically processes the above-mentioned manual work, and utilizes the unit weight difference to produce a predetermined quantity of assortments, and also to minimize the amount of addition of the total weight to zero. This allows for labor savings, reduced losses, and quick packaging.

Hereinafter, the configuration of the present invention will be explained with reference to the drawings.

In Fig. 1, 1 is a first conveyor, 2 is a second conveyor for sorting, and 3 is a first weighing device installed between both conveyors 1 and 2, and the items are transported by an appropriate transfer means ( (not shown) from the first conveyor-1 to the first scale 3, its weight is measured, and then it is sent to the second conveyor-2 by the transfer means.

4 is an ejector for discharging items other than the allowable error weight; 5 is an ejector for discharging items having a positive allowable error weight;
Reference numeral 6 denotes a discharge device for discharging items having a negative allowable error weight, each of which uses a set of air cylinders, for example, and is installed to operate perpendicularly along the running direction of the second conveyor 2. There is.

1 is a discharge conveyor that discharges items with weights other than the allowable error weight.
Reference numeral 8 denotes a positive line conveyor for transporting items having a positive tolerance weight to the second scale 9, and 10 a negative line conveyor for transporting items having a negative tolerance weight to a third scale 11. , all of which are perpendicular to the side surface of the second conveyor 2, and ejectors 4, 5, 6.
It is located opposite.

12 is a positive line stock conveyor for stocking the items weighed by the second scale 9, and 13 is a negative line stock conveyor for storing the items weighed by the third scale 11. be.

14 is a discharger for discharging the items on the positive line stock conveyor 12 onto the accumulation conveyor 15, and 16 is a discharger for discharging the articles on the negative line stock conveyor 13 onto the accumulation conveyor 15. .

1γ is a chute, and 18 is a box conveyed below the chute 17, for example, by a conveyor (not shown).

In FIG. 2, numeral 19 is a sorting circuit that receives the output of the first weighing device 3, and uses the average single weight force Three types of selection are performed: whether the average unit weight X divided by X is within the allowable error of plus (including zero error weight), minus minus, or outside the allowable error.

Then, depending on the sorting result, the sorting circuit 19 outputs the ejector 4.
, 5, 6 are operated to discharge the articles on the second conveyor 2 onto the corresponding conveyor 7, 8, 10.

20 and 21 are A'-D converters that convert the error weight signals of the second and third weighing scales 9 and 11 into BCD codes, and each output is connected to the positive register 22 and the negative register 23. do.

Both registers 22 and 23 each have a capacity to store four pieces of data, and each piece of data is connected to an arithmetic circuit 24.

Reference numeral 25 denotes a box quantity setting unit, which sets the number of pieces per box, such as 5, 10, or 20 pieces, using a dial type, push button type, etc.
This is for setting the number of items to be packed in a box.

Therefore, by setting the number of boxes, the total weight can be determined.

Reference numeral 26 denotes a combination code operation count setting circuit which receives the output of the packaging quantity setting unit 25, and the packaging quantity setting unit 25 sets the packaging quantity, and the positive side and negative side registers 22.26 are set by the packaging quantity setting unit 25. This is to determine how many times to perform the 5 combination code operation, how many times to perform the 4 combination code operation, and how many times the 3 combination code operation should be performed among the 23 total 8 (7) I-codes. be.

In other words, as shown in the table in Figure 4, for an integer number of 3 or more boxes, it can be obtained by combining 5, 4, and 3. For example, in the case of 22 pieces, the 5 piece combination code It is determined that the number of calculations is three, the number of four-piece combination code calculations is one, and the number of three-piece combination code calculations is once.

Note that the codes are X1, X2, X3,
The numbers X4, X, X6, X7, and X8 do not represent the error weight itself.

In addition, the number of times of combination code operations means that the storage capacity of both registers 22 and 23 is now 8 in total.
The combination of 5 is (X1+X2+X3+X4+X5), (
X1+X2+X3+X4+Xa), (X1+X2+X3
+X4+X7), ......, (X4+Xy +Xa
+X7 +Xs), there are a total of 56 combinations, and if the number of 5-combination code operations is 3, then
This means that the number of operations for the other 4-piece combination code and the number of operations for the 3-piece combination code are the same as the number of operations for each of the 70 and 56 combinations. That's what it means.

Reference numeral 21 denotes a 5-combination code operation number control section, 28 a 4-combination code operation number-of-time control section, and 29 a 3-combination code operation number control section, each of which is constructed as follows.

In other words, the 5-piece combination code operation number control unit 21 has 56
5-piece combinational code circuit 211 removed from the standard combinational circuit
The output of is connected to the input of AND circuit 212.

Then, the output of the five combination code operation number detection circuit 273 and the output of the combination code operation number setting circuit 26 are connected to the input of the matching circuit 274, the output thereof is connected to the NOT circuit 275, and the output is connected to the AND circuit 212. and AN
Connect to each input of D circuit 2γ6.

Similarly, the 4-piece combination code operation number control section 28 and the 3-piece combination code operation number-of-time control section 29 operate on the 4-piece combination code circuit 281 and the 3-piece combination code circuit 291, which are respectively composed of 70 combinations and 56 combinations. Each output is A
Connected to the inputs of the ND circuits 282 and 292.

Then, the output of the combination code operation number setting circuit 26 and 4
The output of the individual combination code operation number detection circuit 283 and the output of the three combination code operation number detection circuit 293 are connected to the inputs of the corresponding matching circuits 284 and 294, and each of these outputs is connected to the NOT circuits 285 and 295. , their respective outputs are connected to AND circuits 282, 286 and AND circuit 292.
, 296 respectively.

The outputs of the AND circuits 212, 282, and 292 are connected to the inputs of the OR circuit 30, and the outputs thereof are connected to the arithmetic circuit 24 and to one input of the M circuit 31.

On the other hand, the output of the coincidence circuit 274 of the 5-piece combination code operation number control section 27 is combined with the AND circuit 282 of the 4-piece combination code operation number control section 28 and the 3-piece combination code operation number control section 2.
9 AND circuits 292 and NAND circuits 32 are connected in parallel to each input, and the output of the matching circuit 284 of the 4 combination code operation number control section 28 is connected to the AND circuit 292 of the 3 combination code operation number control section 29 and the NAND circuit. 32, and further, the output of the matching circuit 294 of the three-piece combination code operation number control section 29 is connected to the input of the NAND circuit 32.

@Note, each combination code operation number detection circuit 273, 283
, 293 count the number of operations, and match this count output with the output of each combination code operation number from the combination code operation number setting circuit 26 to corresponding matching circuits 274, 284.
, 294, and when both outputs match, each matching circuit 2
The outputs of 14, 284, and 294 are at rHJ level.

When they do not match, the output becomes rLJ level.

Further, if the output from the combination code operation number setting circuit 26 is zero, that is, there is an output indicating that no operation is necessary, the corresponding matching circuits 274, 284, 29
The output of No. 4 is configured to be at the rHJ level.

33 is a memory circuit for storing the packing start signal a, which connects this signal a to the set human power S and resets the human power R.
The output of the NAND circuit 32 is connected to.

Then, the Q output of this memory circuit 33 is connected to one input of the AND circuit 34, and via the differentiating circuit 35,
The circuits 273, 283, and 293 are connected in parallel to each of the five, four, and three combination code operation count detection circuits 273, 283, and 293, and to each reset input of a second register 60, which will be described later.

The memory full signal b from the plus side and minus side registers 22 and 23 is connected to the other input of the AND circuit 34.

36 is a differentiation circuit which receives the output of the AND circuit 34;
1 is a storage circuit for storing the computation end signal C each time,
The output of the differential circuit 36 is connected to the set human power S, and the calculation end signal C is connected to the reset human power R each time.

Then, the Q output is connected to each input of the AND circuit 39 and 40 via the differentiating circuit 38, and connected in parallel to the reset input R of the memory circuit 42 via the NOT circuit 41, and the other Q output is connected to the AND circuit 43. .44 are connected in parallel to each input, and an AND circuit 46 and 5, 4, and 3 combination code operation number control units 2γ, 2 are connected in parallel to each input of
8. 29 AND circuits 2γ6, 286, 296
Connect in parallel to each input of

The differentiating circuit 35 outputs a rHJ level trigger pulse when the Q output of the memory circuit 33 changes from rLJ to "H" level, and the differentiating circuit 36 outputs a trigger pulse of rHJ level when the output of the AND circuit 34 changes from rLJ to "H" level.
When it changes to the HJ level, a trigger pulse of the rLJ level is output, and the differentiating circuit 38 and the differentiating circuit 45 are connected to the memory circuit 3.
When the Q output and the Q output of No. 1 reach the rHJ level, they are each configured to issue a trigger pulse at the rHJ level (see Figure 3). an intermediate permissible error weight setting circuit for setting the permissible error weight when an intermediate combination code calculation (for example, in the case of 5 combination code calculations, 56 combination code calculations) is completed;
48 is a total allowable error weight setting circuit for setting the total allowable error weight for the final total weight when all combination code calculations are completed, and the allowable error weight in the latter is set smaller than that in the former. It has been done.

49 is a final operation detection circuit that detects the start of the last operation among all combination code operations.

Then, the output of this final operation detection circuit 49 is connected to one input of an AND circuit 50, and is also connected in parallel to one input of an AND circuit 52 via a NOT circuit 51.

On the other hand, the output of the intermediate tolerance weight setting circuit 4T is connected to the other input of the AND circuit 52, and the output of the total tolerance weight setting circuit 48 is connected to the other input of the AND circuit 50. Each output of 52 is connected to an input of an OR circuit 53.

54 is a first comparison circuit, and 55 is an AND circuit, in which the output of the arithmetic circuit 24 is connected to the input of the first comparison circuit 54 and also to one input of the AND circuit 55.

Then, the output of the OR circuit 53 is connected to the other input of the first comparison circuit 54, and the output of the first comparison circuit 54 is connected to the output of the first comparison circuit 54.
It is connected to the other input of the ND circuit 55 and also connected to the set input S of the memory circuit 42 via the NOT circuit 56.

The first comparison circuit 54 compares the calculation result of each combination code performed by the calculation circuit 24 with each permissible error weight set by the intermediate permissible error weight setting circuit 4γ or the total permissible error weight setting circuit 48. It is something to do.

5γ is the second comparison circuit, 58 is the AND circuit, and 59 is the first comparison circuit.
60 is a second register, and 61 is a code storage register.

Then, the output of the AND circuit 55 is connected to the input of the second comparison circuit 57 and also connected to one input of the AND circuit 58, and the output of the second comparison circuit 57 is connected to the input of the two AND circuits.
Circuit 31. 58 in parallel to each other input.

The second comparison circuit 5T compares the calculation result of the calculation circuit 24 with the error weight stored in the first register 59, and the first register 59 compares the calculation result of the calculation circuit 24 with the error weight stored in the first register 59. Furthermore, the code storage register 61 is used to store the combination code resulting in the minimum error weight.

d is a preset signal for presetting all the first registers 59 to rIJ, and is connected to the other input of the AND circuit 40, and the output of this AND circuit 40 is connected to the preset input of the first register 59. do.

Then, the output of the AND circuit 58 is transferred to the first register 59.
, and its output is fed back to the second comparison circuit 57 and connected to one input of the AND circuit 46 .

On the other hand, the Q output of the pupil circuit 42 is controlled by each of the ANs 27, 28, and 29 for controlling the number of calculations of the 5, 4, and 3 combination codes.
It is connected in parallel to one input of the D circuits 2161286 and 296, and also connected in parallel to one input of the AND circuit 46.

Then, the output of this AND circuit 46 is connected to the input of the second register 60, and this output is connected to the human power of the arithmetic circuit 24.

This second register 60 is for storing the minimum error weight of the previous combination code calculation, and the calculation circuit 24 takes this output into account, that is, corrects it and calculates it.

In addition, if the Q output of the memory circuit 42 is connected to the other input of the AND circuit 44, and the output e of the AND circuit 44 is calculated once, if all the calculation results are outside the allowable error range, At the end of all calculations, it is taken out as an alarm signal.

f is a reset signal for presetting all the code storage registers 61 to rOJ, and is connected to the other input of the AND circuit 39, and the output of this AND circuit 39 is connected to the preset input of the code storage register 61, and the AN
The outputs of the D circuits 31 are connected to the inputs of the code storage registers 61, and the outputs of the code storage registers 61 are connected to the A circuits.
Connected to the other input of the ND circuit 43, this AND circuit 4
Send the output of 3 to the ejector 14.16 as the ejection signal g,
Activate the appropriate ejector 14.16.

At the same time, it is sent as an erase signal h to the positive and negative side registers 22 and 23 to erase the corresponding memory contents.

The code storage register 61 is used to store a code combination resulting in the minimum error weight among each combination code operation.

62, 63, and 64 are AND circuits, which connect the other output of the 5-piece combination code circuit 211, the output of the NOT circuit 215, the other output of the 4-piece combination code circuit 281, and the NO circuit.
The output of the T circuit 285, the other output of the three combination code circuit 291, and the output of the NOT circuit 295 are respectively input.

Then, 65 is a NOR circuit, and the AND circuit 6
2,63. The respective outputs of 64 are connected to the inputs, and the outputs are sent to the memory circuit 3γ as the calculation end signal C each time as described above.
Connect to the reset human power R.

The operation of the present invention having the above structure will be explained as follows.

The items sent by the first conveyor 1 are sent one by one to the No. 1 scale 3 by a transfer means (not shown), and then their weight is measured by the first scale 3.

A sorting circuit 19 compares this weight with the average unit weight
, 6 is the positive line conveyor - 8, negative line
The other items are sent to the conveyor 10 and the other items are sent to the ejector 4.
and discharge it to the discharge conveyor l.

Next, the items on both line conveyors 8 and 10 are sent to the second and third weighing devices 9 and 11 by a transfer means (not shown), and the error weight with respect to the average unit weight X is measured. The value is converted into a BOD code by the A-D converter 20 and 21, and the plus error weight is stored in the plus side register 2.
2, each minus error weight is stored in the minus side register 23.

Then, weighing is performed until the error weight is stored in a total of 8 capacities of both registers 22 and 23, and when the memories of both registers 22 and 23 are full, the weighing is stopped and A
A memory full signal b is sent to the ND circuit 34.

At this time, the positive line and negative line stock conveyors 12.13 are stopped and each has 4 items placed thereon.

Next, when the number of boxes to be packed is set to, for example, 22 pieces in the boxed pieces number setting section 25, the fourth
As shown in the table in the figure, signals are sent to each coincidence circuit 274, which performs three combination code operations for 5 combination codes, once for 4 combination code operations, and once for 3 combination code operations, respectively.
284, 294.

Then, when the packaging start signal a is sent manually or automatically from the outside to the set manual S of the memory circuit 33 as shown in Fig. 3A, the Q output changes to the rHJ level (Fig. 3).
.

At this time, each input of the NAND circuit 32 is at the rLJ level, and its output is at the rHJ level.

On the other hand, the output of the differentiating circuit 35 is r
A trigger pulse of HJ level is output, and with this pulse, each of 5, 4, and 3 combination code operation number detection circuits 273
, 283, 293 and the second register 60. Each will be reset.

At the same time, the output of the AND circuit 34 becomes rHJ level, the output of the differentiating circuit 36 outputs a trigger pulse of rLJ level as shown in FIG. Change (see Figure 3).

Then, the output of the differentiating circuit 38 outputs a trigger pulse of "H" level as shown in FIG.
.

At the same time, the Q output and the Q output of the memory circuit 42 are respectively rLJ and
Reset to rHJ level (Fig. 3 O).

Furthermore, no pulse is output from the differentiating circuit 45 as shown in FIG.

On the other hand, at the same time as the packaging start signal a is input, the calculation circuit 24 calculates the first combination code, X1+X2+X3+X4+X, according to the combination code set in the five-piece combination code circuit 271, and calculates the total value, that is, the error weight. The first comparison circuit 54 compares whether or not the total value is within the intermediate tolerance weight range set in advance by the intermediate tolerance weight setting circuit 41, and if it is within the range, this total value is ANDed.
It is sent through the circuit 55 to the second comparison circuit 5T.

The Q output and Q output of the storage circuit 42 are set to "H" and "L" levels, respectively, as shown in FIG. does not change.

At this time, the first register 59 has already been preset to rIJ by the trigger pulse of the differentiating circuit 38 as described above, so the first calculation result passes through the second comparator circuit 51 unconditionally. In other words, AND circuit 58
, and is sent to the first register 59 to replace the stored contents therein.

The contents of the first register 59 are as described below.
When all calculations are completed each time, “H
” level trigger pulse (Fig. 4
It is sent to the second register 60 only when it is sent to the second register 60.

On the other hand, five combinational code circuits 2γ1 to AND circuit 2γ2, OR circuit 30,
The current operation code 1 sent through the AND circuit 31
1111000 (that is, X1, X2, X3, X5
) is memorized.

Next, the second computation of X1 + X2 + X3 + X4 + If it is within the range, this total value is sent to the second comparison circuit 57, and the second comparison circuit 51 compares it with the first total value previously stored in the first register 59. be compared.

If the second total value is smaller in absolute value than the first, then this second total value is smaller than the first total value.
register 59, and replaces the first total value.

At the same time, the code storage register 61 also stores the second code 1.
1110100 (that is, X1, X2, X3, X4,
6), this second code is stored.

Contrary to the above, if the second total value is larger in absolute value than the first, the third operation, that is, X1+X2+Xs+X4+X7, is performed, and the first register 59 is As for the total value, the code storage register 61 also continues to store the first code.

Further, as a result of the comparison in the first comparator circuit 54, if the second total value is not within the intermediate tolerance weight range, the third calculation is immediately performed, and at this time, the first register 59 , the contents stored in the code storage register 61 remain unchanged. In this way, the combination code calculations are sequentially performed by the calculation circuit 24.

Each time, the first comparison circuit 54 compares whether or not the weight is within the intermediate allowable error weight, and the first register 5 stores the value of the minimum error weight from the previous calculation.
The second comparison circuit 51 performs a comparison with the value of 9 and updates the storage contents of the first register 59 based on the result, stores the value of the minimum error weight, and at the same time updates the value of the code storage register 61. The memory contents are also updated and the first register 5
Store the code for the value of minimum error weight stored in 9.

Then, the final 56th operation X4 +X5 +X6 +
X7 +
5, the computation end signal C is sent to the reset input H of the memory circuit 31 each time (FIG. 3, 9).

As a result, the memory circuit 37 is reset, and its Q output,
The Q output changes to "L" and "H" levels, respectively, as shown in FIG. The value of the minimum error weight that has been set is stored in the second register 60.
, and stores the minimum error weight due to the current combination code calculation, and sends one pulse to the 5 combination code calculation number detection circuit 213 via the AND circuit 216.
It is stored that the individual combination code operation has been completed once.

At the same time, an output signal g and an erase signal h are output from the AND circuit 43 using the Q output of the memory circuit 31 and the signal of the code memory register 61 (L- in FIG. 3), and are stored in the code memory register 61. According to the combination code of the minimum error weight resulting from the current combination code calculation, the corresponding ejector 14, 16 is operated to eject the item onto the accumulating conveyor 15, and the item is placed into the box 18 via the chute 17.

At the same time, the positive side and negative side registers 22.
23 is deleted.

Next, the items are weighed again by the second and third weighing devices 9 and 11 by the number of erased memory contents, and the items are sent to the plus line and minus line stock conveyor-12.13, and the measured error weight is Save the value to both registers 22 and 23
to be memorized.

At this time, the error weight values that have not been erased are sequentially X1 to X2, X2 to X3, X3 to X4, and X, to X6,
It is shifted and re-stored from X6 to X7 and from X7 to X8.

And both registers 22. When the memory of 23 becomes full again, the memory full signal b is sent to the AND circuit 34 (FIG. 3, 2), and this signal b and the Q output of the memory circuit 33 are used as shown in FIG. 3, E. , a trigger pulse is output again from the differentiating circuit 36 to set the memory circuit 3γ, preset all the first registers 59 to rIJ and all the code memory registers 61 to “0” as described above, and also preset the memory circuit 42 to 0. As shown in FIG. 3E, the Q output and Q output are reset to "L" and "H" levels, respectively.

Then, the second five-piece combination code calculation is performed again as described above.

However, in the second and subsequent calculations, the minimum error weight in the first calculation stored in the second register 60 is fed back to the calculation circuit 24, and this is taken into account, that is, corrected. Perform calculations.

In this way, when the calculation is performed the same number of times as the number of 5 combination code calculations set by the combination code calculation number setting circuit 26, the output of the matching circuit 214 becomes rHJ level, and as a result, the output of the NOT circuit 215 becomes rLJ level, and the output of the 5-piece combination code circuit 211 is AND
It cannot pass through the circuit 212, and henceforth, no 5-piece combination code operation will be performed.

Also, the trigger pulse of the differentiating circuit 45 (
3) cannot pass through the AND circuit 216, henceforth, the 5-piece combination code operation count detection circuit 273 will not count this tribanomanores.

Then, when the 5, 4, and 3 combination code calculations are completed each predetermined number of times as described above according to the set number, at this time,
The output of each matching circuit 274, 284, 294 becomes rHJ level, and the output of NAND circuit 32 becomes rLJ level, and this output resets the memory circuit 33 as a complete calculation signal (Figure 3), and its Q output becomes rLJ level. As shown in Figure 3, the level changes to rLJ, and the packing operation for one box is completed.

Therefore, the minimum error weight stored in the second register 60 at the end of the final calculation indicates the packing error weight of the total weight in the packaging.

Of the total number of calculations, when starting the final calculation, the total permissible error weight set by the total permissible error weight setting circuit 48 based on the output of the final calculation detection circuit 49 is determined by the AND circuit 50, O
It is sent to the first comparison circuit 54 via the R circuit 53, and only during the final calculation, the range of the total allowable error weight and the total value calculated by the calculation circuit 24 are compared in the first comparison circuit 54. be done.

To carry out the next packing, it is sufficient to fill up the memories in the plus side and minus side registers 22 and 23, and then send a packing start signal a to the memory circuit 33 from the outside to repeat the above operation.

The above operation has been explained for the cases where the number of 5-, 4-, and 3-piece combination code operations is performed at least once each, but for example, when the number of 4-piece combination code operations is set to zero, the above As shown, the output of the matching circuit 284 is already at the rHJ level, and when the 5-piece combination code calculation is completed a predetermined number of times, the 3-piece combination code calculation is performed next, and
For example, when the number of 4 and 3 combination code calculations is set to zero, the outputs of the matching circuits 284 and 294 are already at the rHJ level, and the 5 combination code calculations are performed a predetermined number of times until all calculations are completed. It is easy to see that when the combination code operation is completed, the rLJ level output from the NAND circuit 32 is sent to the reset manual R of the memory circuit 33 as a completion signal for all calculations. The results of the combinational code operations corresponding to
If all of the weights are out of the set range of the allowable error weight, the first comparison circuit 54 to the storage circuit 42
Since no set signal is sent to , its Q output and Q output remain reset to the rLJ and rHJ levels, respectively.

In other words, it remains reset by the trigger pulse of the differentiating circuit 38 that is issued at the start of calculation (dotted line in FIG. 3).

Therefore, an alarm signal e is output from the M-width circuit 44 as shown by the broken line in FIG. Code operation number detection circuits 273, 283,
The output of the differentiating circuit 45, which is the computation end signal, is prohibited from being sent to 293.

At this time, all the code storage registers 61 remain preset to rOJ, so the discharge signal g and the erase signal h are not output from the AND circuit 43.

Then, new error weights are stored in the plus side and minus side registers 22 and 23, and the same combination code calculation is performed again.

At this time, the trigger pulse is output from the differentiating circuit 38 as described above with the memory full signal b of both registers 22 and 23 (see Fig. 3), but since the memory circuit 42 remains reset, its Q output , the Q output remains at the rLJ rHJ level (Fig. 3E) 0 Next, an explanation will be given based on specific numerical values.

Now, assuming that the number of boxes is 22, the total weight of the boxes is 33Kp, the intermediate tolerance weight is ±20g, the total tolerance weight is +10g, -Og, the average unit weight is 33K2 ÷ 22 pieces - 1.5Kp, and as shown in Figure 4. From the table, the number of operations for 5, 4, and 3 combination codes is 3, 1, and 1, respectively.

Then, the average unit weight was 1.5K on the second and third scales 9 and 11.
The error weight for 2 is measured, and the error weight is sequentially stored in the plus side and minus side registers 22 and 23, X,, X2, X3, X4, x, X6, X
7, + 71 g1+ 30g1+ iog, + 8
Suppose that gs 30g125 gs - 65g %X8 -14g.

The first 5-piece combination code operation is performed 56 times, and the result is E1=X, +x3X 4+X6+X 7=71
+101-25-65=-1g is the minimum error weight,
Plus line stock conveyor -12 to +71gs
Items having error weights of +1 0 g, +8 g, and -25 g, -65 g from the negative line stock conveyor -13 are discharged to the accumulation conveyor -15.

At this time, the number of pieces discharged is 5 pieces, and the error weight El "" - 1
gz total weight is 7499g.

Next, the items are weighed three times using the second weighing device 9 and twice using the third weighing device 11, and the results are as follows:
7g, +42g, +4g, +30g, -24g,
-8g1-30g, -14g.

Then, in the same way, the second 56 calculations are performed by adding the previous error weight E,=-1g, that is, by correcting it, E2=E1+X2+X4+X5+X7+X8=-1+
42+30-24-30-14113g is the minimum error weight up to the second time, and the corresponding items are discharged to the collection conveyor 15 in the same manner as last time.

At this time, the total number of pieces discharged up to the second time is 10 pieces, error weight E2 = +3g, total weight is 1500gX10 + E2 = 1
It becomes 5003g.

Then, perform the third weighing and the results are X1, X2, X3, X4, X,, X6, X7, X8+6
g. +33g, +87g, +4gx - 70
Suppose that it is gs - 45gs - 60gi - 8g.

Similarly, the third 56 calculations are performed by correcting the error weight E2 = +3g until the previous time, and E s "" E 2 +X 1 +X 2 +X s
+X5 +X7=3+6+33+87-70-60 111g is the minimum error weight up to the third time, and the corresponding items are similarly discharged.

In case B, the total number of pieces discharged up to the third time is 15 pieces, error weight E3 = -1gs, total weight is 1500g x 1
5 + E 3 = 2 2 4 9 9 g.

Next, the fourth weighing results are X1, X2, X3, X4, X5, X6, X7, X8+
16g, +10g, +2g, +4g, -51g
, -47g1-45g, -8g.

Here, 4 combination code calculations (70 ways) are performed by correcting the error weight E3 = -1g up to the previous time, and E4 = E3 + X1 + X2 + X4 + Eject the applicable items.

At this time, the number of pieces discharged up to the fourth time was 19 in total, error weight E4 = -16g, total weight 1500gX19+E4
=28484g.

Next, the 5th measurement result is X,, X2, X3, X4, X,, X6, X7, X8
+24g, +34g, +18g, +2g, -
23g, -51g, -47g1-8g.

Here, 3 combination code calculations (56 ways) are performed by correcting the error weight E, = -16g up to the previous time, and E 5 = E, +X1 + X4 + XB = -16 + 24 + 2-8 = +2g is the fifth or final The minimum error weight will be up to,
Dispose of the corresponding items in the same way.

At this time, the total number of pieces discharged until the fifth time, that is, the final time, is 22 pieces, and the final error weight E, = +2g1 total weight is 150 pieces.
0gX22+E5 = 33002g.

As a result, the number of items packed in one box is 22, and the total weight of each box is 33.
002g, resulting in an error of +2g.

Also, each error weight (E1), (E2) up to the 4th time
, (E3), and (E4) are within the initially set intermediate tolerance weight ±20 g, and the final error weight (E5) is also within the range of the total tolerance weight +10 g, −Og.

In the above embodiment, the positive side and negative side registers 22
．． Although the storage capacity of 23 is 4 each, making a total of 8, the number is not limited to this number.

Further, although the error weight with respect to the average unit weight X is stored in both registers 22 and 23, the unit weight may also be stored.

At this time, a division circuit is incorporated in the arithmetic circuit 24, and the total weight obtained by each combination code calculation is divided by the number of pieces at that time to calculate the average unit weight at that time, and the original average unit weight set in the sorting circuit 19 is calculated. The calculation circuit 24 calculates the error in the average unit weight of each time obtained by the calculation circuit 24 for X, and the sum of this error and the total error weight up to the previous time stored in the second register 60 is calculated as the first The comparison circuit 54 may compare the intermediate allowable error weight or the total allowable error weight set by the intermediate allowable error weight setting circuit 4T or the total allowable error weight setting circuit 48.

As explained above, according to the present invention, variations in the unit weight of items do not affect the measurement accuracy, and it is possible to carry out weighing of a predetermined number, weight, or closest to a predetermined weight with extremely high accuracy, and to Since the error weight in the previous calculations is taken into consideration in the next calculation, that is, corrected, the weighing error can be minimized even if the number of combination code calculations increases.

Furthermore, since the register that stores the unit weight error or unit weight of the item is provided with a shift function, a plurality of items can be weighed one after another with one weighing device, and the device itself can be manufactured at a low cost.

Furthermore, even if the weight of the item is linearly biased, the plus line,
Since each item is stocked on a negative line conveyor, there is no problem with calculations.

Furthermore, even if the predetermined number of units is large, the calculation is performed in multiple steps, so the electric circuit and mechanism can be manufactured easily and at low cost.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of a weighing system to which the present invention is applied;
The figure is a block circuit diagram of the present invention, and FIG. 3 is an operating waveform diagram. FIG. 4 is a table showing the relationship between the number of boxes and the number of combination code operations. 22...Positive side register, 23...
・Minus side register, 24... Arithmetic circuit,
25... Packing number setting unit, 26... Combination code operation number setting circuit, 21... 5 combination code operation number control 28...4 Individual combination code operation number control unit, 29...3 combination code operation number control unit, 41...Intermediate allowable error weight setting circuit, 48...Mother allowable error weight setting circuit , 54...first comparison circuit, 51...
second comparison circuit, 59...first register;
60... Second register, 61...
Code storage register.

Claims (1)

[Claims] 1. Sequentially weigh bulk articles with varying unit weights using one weighing machine, and sequentially store a predetermined number of errors or measured values for the average unit weight of the articles obtained by this weighing, and A measuring method characterized in that the stored data of numbers is combined and calculated according to all combinations of set numbers, and the value of the combination calculation result is a set value or a combination of values closest to the set value.