JPS5842560B2 - Kioku System Noera - Seigiyohoshiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an error control method for a storage system, particularly in a storage system consisting of a main memory, an intermediate buffer storage, and an internal buffer storage. The present invention relates to an error control method for a storage system in which a large-capacity main storage device can be used without maintenance for a long period of time by transferring the data to a buffer storage device.

The capacity of the main memory of electronic computers has increased, and with advances in semiconductor technology, the degree of integration of the memory chips that make up the main memory has also improved, and the entire main memory is now constructed on a single wafer. There is a possibility.

As described above, with the increase in capacity and integration, it becomes economically disadvantageous to replace memory chips when a defect occurs.

An object of the present invention is to enable a large-capacity main storage device to be used for a long period of time without maintenance even if a defective block with an error occurs in a part of the main storage device.

Examples will be described in detail below. As electronic computers become larger and faster, storage systems consisting of large-capacity main storage devices and high-speed buffer storage devices are being adopted.For example, as shown in FIG.
An internal buffer storage device IBF is provided between the main storage device MM and the main storage device MM.
A configuration in which an intermediate buffer storage device MBF and an intermediate buffer storage device MBF are arranged, or a configuration in which the intermediate buffer storage device MBF is omitted is adopted.

The present invention comprises a main memory device MM and an intermediate buffer memory device IV.
In a storage system consisting of an IBF and an internal buffer storage device IBF, for a defective block in the main memory device MM, an area DM and an area DM for storing the contents of the defective block are provided in the intermediate buffer storage device MBF as shown in FIG. , an area ADM for storing the address of the defective block and an area EDM for indicating the presence of a defect are provided, and when accessing a defective block, the main memory is not accessed, but the intermediate buffer memory is accessed. Furthermore, when selecting an empty block in the intermediate buffer storage device, selection of a defective block is prohibited.

The intermediate buffer storage device has a smaller capacity than the main memory device, and has a smaller capacity than the main memory device MM and the central processing unit CPU.
When the central processing unit needs information, if the information exists in the internal buffer storage device IBF, the information is immediately retrieved and the central processing unit CPU If it is to be used for processing and does not exist in the internal buffer storage IBF, it is taken out from the intermediate buffer storage MBF and stored in the central processing unit CP.
U processes it and moves it to the internal buffer store IBF, and if it is not also present in this intermediate buffer store MBF, it retrieves the block containing the information from the main memory MM and moves it to the intermediate buffer store MBF, and also moves it to the intermediate buffer store MBF. The information will be received by the central processing unit CPU and used for processing.

Also, access from channel CH is made to intermediate buffer storage MBF, and if the information required by channel CH does not exist in intermediate buffer storage MBF,
The block containing the information is moved from the main memory MM to the intermediate buffer memory MBF and the information is transferred to the channel CH.

Generally, for access requests from the central processing unit, 90
Typically, the information is in buffer storage more than % of the time.

For example, if the probability is 90%, the main memory access time is 1 μsec, and the buffer storage access time is 100%,
n sec, the average access time t is t=0.9
X100+0.1X1000=190 (nsec).

By using such a high-speed buffer storage device, the average access time can be shortened.

Control of such a buffer storage device requires two processes: "address detection" and "empty block selection", and various methods have been proposed for this.

The above-mentioned "address detection" means determining whether or not the requested information is stored in the buffer storage device when an access request is issued from the central processing unit. In order to do this, address information is required that indicates from which location in main memory the information stored in the buffer storage device was moved, so the buffer storage device has an address that holds that address information. A region is formed.

If the result of address detection is that the required information is not in the buffer storage, the block containing the requested information must be moved from main storage to the buffer storage.

At this time, which block of the buffer storage device the information is transferred from the main storage device is an important factor that affects the efficiency of the buffer storage device, and as a method for associating the main storage device and the buffer storage device, full associative method,
Direct mapping methods, sector methods, set associative methods, etc. are known.

According to these methods, "free block selection" determines which block in the buffer storage device the information is actually transferred to.
Is required.

This "free block selection" method includes a method of selecting a block that has not been used for the longest time (LRU);
In the present invention, the intermediate buffer storage device M as described above is used.
As shown in FIG. 2, the BF displays a content storage area DM to which a block of the main memory MM is to be transferred, an address area ADM for storing the address of the block, and whether or not the block is a defective block. Defect display area ED
M is provided, and this defect display area EDM
is initially set as having no defects, and if a defect is discovered in the main memory by an error check circuit, etc.
The defective block is transferred to the intermediate buffer storage device, and the defect display area corresponding to the content storage area to which the defective block has been transferred is marked as defective, and the block displayed as defective is selected for free block selection. It is prohibited.

For access to the storage system from channel CH, address detection is first performed, and if the requested information exists in the intermediate buffer storage device MBF, the intermediate buffer storage device MBF is accessed, and even if the type of access is write. For example, the main memory MM is also written at the same time, or if the requested information is not in the intermediate buffer memory as a result of address detection, the main memory MM is accessed.

When a defect is found in the main memory device MM, the contents of the block are transferred to the intermediate buffer memory device MBF, and the defect display area is marked as defective.

It is possible to use an internal buffer storage device IBF as a buffer storage device to assist in the above-mentioned defects in the main memory device MM, but as shown in FIG. The intermediate buffer storage device MBF is used because the access from the central processing unit CPU is less likely to interfere with the access from the central processing unit CPU.

For example, the main memory MM has a capacity of 16 Mbytes, the intermediate buffer memory MBF is set-associative, and the capacity is 6 Mbytes.
4 bytes/block, 4 blocks/set, capacity 256
Assuming that bytes are in the main memory M as shown in Figure 2,
When the central processing unit CPU or channel device CH accesses M, if a defective block is found by the error check circuit, the contents of the block are moved to the content storage area DM of the intermediate buffer storage device MBF, and the address of the defective block is and ``defective'' are written in the address area ADM and the defect display area, respectively.

From then on, by address detection, access by the central processing unit or channel is limited to the intermediate buffer storage MB.
It will be processed correctly in F.

Note that in the set associative method, information in the main memory device MM may be associated with any area of the buffer memory device with the same column number, so in the embodiment shown in FIG. Since each area of the device MBF consists of four blocks, if there are four or less defective blocks in the same column in the main memory device MM, those defects can be compensated for by the intermediate buffer memory device MBF.

For example, if 256 blocks become defective in the main memory MM after a certain period of time and these defective blocks are randomly distributed, the probability that they can be assisted by the intermediate buffer memory MBF is 99%.

FIG. 3 is a block diagram of an embodiment of the present invention, where the same reference numerals as in FIG. 2 indicate the same parts, and PDM is a priority display area;
COR is a priority correction circuit, SEL is a selection signal 5O-s3
UPD is a priority display area update circuit, REG1 to REG3 are registers, CPO to
CP3 is a comparison circuit that outputs a match signal C6-C5 based on a comparison match; Go '3y Go'=Gs', G
, 5o-83 is a gate circuit.

The selection circuit SEL and the update circuit UPD operate under the condition that the match signals C3-C3 are all "0", and the gate circuit G
i and Gi' are the match signal Ci, the gate circuit Si is opened under the selection signal si (i=o, 1, 2, 3), and the gate circuit G is opened under the conditions of the match signals C6-C1, C2, and C3.

When the main memory device MM is accessed from the central processing unit CPU, an address is set in the register REG1, and whether or not the data is transferred from the main memory device MM to the buffer memory device, that is, the address is detected.

This is done by accessing the address area ADM with a set address and comparing it with the block address by the comparator circuit CPo-CF2, and the match signal Ci is
1'', since it has already been written in the buffer storage device, the read data in the content storage area DM is transferred to the register REG via the gate circuit C1' opened by the coincidence signal Ci.
3 and is transferred from this register REG3 to the central processing unit CPU.

If the match signals C3-C3 from the comparison circuits CPo-CF2 are all "0", the contents of the main memory device MM corresponding to the access address have not been transferred to the buffer memory device, so the contents of the main memory device MM are not transferred to the buffer memory device. is accessed, gate circuit G is opened, and read data is set in register REG3.

Since this data may be used repeatedly, it is written to a buffer storage device.

However, since the capacity of the buffer storage device is small, it is necessary to write the data after previously written data with low priority is removed.

For this purpose, a priority display area PDM is provided.

Moreover, as mentioned above, the main memory device MM is located in the defect display area EDM.
After a defective block has been displayed and the contents of the defective block have been written to the content storage area DM, it is prohibited to refer to the contents of the defect display area EDM and perform eviction, as shown in FIG. As shown in the priority display area PD
The fact that the content of column 2 of M is rOJ means that the content storage area D
This indicates that block O in column 2 of M has the lowest priority and may be evicted when selecting an empty block.

However, when "1" is set as a defective block indication in block 01 column 2 of the defect display area EDM, by performing the calculation shown by (COR) in FIG. 4 in the priority correction circuit COR, Block O in column 2 is '100
” and has the highest priority, so “00
1'' is selected, gate circuit S1 is opened by selection signal s1, and data from main memory device MM is written into column 2 of block 1 of content storage area DM.

Then, the update circuit UPD adds 1 to the replacement block number '01' and sets the contents of column 2 of the priority display area PDM to 2, as shown in the lower part of FIG.

Note that the update circuit UPD that updates the contents of the priority display area PDM performs modulo 4 calculation, and if a defective block exists, the processing in the priority correction circuit COR will The defective block has the highest priority and can therefore be prevented from becoming a replacement block due to eviction.

Also in the case of writing from the central processing unit CPU, the register R
Data is set in EG3 and written into the main memory MM, and at the same time, as described above, the block with the lowest priority is selected and written into the content storage area DM.

Although the above embodiment shows the case of the set associative method, even when other methods are adopted, the buffer storage device assists the main memory device MM in which a defective block has occurred, in accordance with the above embodiment. , the large-capacity main memory device MM can be used for a long period of time without maintenance.

As explained above, the present invention provides a storage system comprising a main memory, an intermediate buffer storage, and an internal buffer storage, in which the intermediate buffer storage includes a content storage area, an address area, and a defect display area. writing the contents of the defective block of the main memory to the content storage area of the intermediate buffer storage and displaying the presence of a defect in the defect display area;
Access to a defective block in the main memory is not made to the main memory but to the intermediate buffer memory, and when selecting a free block in the intermediate buffer memory, the defective block is not displayed. When a defective block occurs in the main memory, the defective block is replaced by a block in the intermediate buffer memory, so it is not necessary to replace the main memory. A very economical storage system can be constructed.

Furthermore, since access from the central processing unit CPU is made to the internal buffer storage device IBF, and access from the channel CH is made to the intermediate buffer storage device MBF, by providing the intermediate buffer storage device MBF, the central Access from the processing unit CPU to channel CH
This means that the rate of interference from accesses from
By replacing defective blocks, the above-mentioned effects can be effectively achieved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory block diagram of the storage system, FIG. 2 is an explanatory diagram of the storage area of the embodiment of the present invention, FIG. 3 is a block diagram of the embodiment of the present invention, and FIG. 4 is free block selection. FIG. MM is main memory, MBF is intermediate buffer memory, I
BF is an internal buffer storage device, CPU is a central processing unit,
CH is a channel device, DM is a content storage area, ADM is an address area, EDM is a defect display area, and PDM is a priority display area.

Claims (1)

[Claims] 1. In a storage system consisting of a main storage device, an intermediate buffer storage device, and an internal buffer storage device, the intermediate buffer storage device is provided with a content storage area, an address area, and a defect display area, and the main storage device is provided with an error display area. When a defective block that occurs is detected, the contents of the defective block are written in the content storage area of the intermediate buffer storage device, the address of the defective block is written in the address area, and the presence of the defect is indicated in the defect display area. access to the defective block is not made to the main memory but to the intermediate buffer storage device, and when selecting a free block in the intermediate buffer storage device, access to the defective block is An error control method for a storage system, characterized in that selection of a displayed block is prohibited.