JPH06337815A - Data processor - Google Patents

Abstract

PURPOSE:To obtain a high hit ratio with inexpensive constitution in a space which is physically restricted by constituting a cache memory with DRAM and providing a flag storage means storing a flag showing the validity of data in the cache memory. CONSTITUTION:The cache memory 4 in a cache control unit 1 is constituted by DRAM. When a memory read request is given, real address data 8 and a valid flag 9 are read out of the address array buffer 3 of the cache memory 4. The address data 8 and the valid flag 9 are inputted to a matching detection circuit 10, and they are compared with address data of an address comparison part 5. When the valid flag 9 is '1' (data is valid) and matched address data exists as the result of matching, ROW information 11 which is cache-hit is inputted to a selector 16, and data which is read out of the corresponding ROW position of a cache buffer 2 is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor provided with a cache memory and a cache controller for controlling the cache memory between a main memory and a data processing unit.

[0002]

2. Description of the Related Art Conventionally, in order to improve a transfer rate of data (instruction or data) from a main memory device to a data processing unit, a cache memory is provided between the main memory device and the data processing unit, If the data has been accessed and read out, the read data is transferred to the data processing unit and written into the cache memory at the same time. If the data to be accessed exists in the cache memory at the next access,
There is known a data processing device with a cache memory, which transfers relevant data from a cache memory to a data processing unit without accessing the main storage device.

By the way, in such a data processing apparatus, in order to increase the hit rate to the cache memory, it is necessary to secure a considerable storage capacity. For example, it is desirable to secure a storage capacity of 2 MB or more for online processing.

On the other hand, recently, there has been an increasing demand for a single chip and downsizing of a data processing unit and a cache memory, and it is desired to effectively use the cache memory in a physically limited space.

[0005]

However, in a conventional data processing device with a cache memory, Japanese Patent Application Laid-Open No. 29-29200 is known.
As disclosed in Japanese Patent No. 6541, an SRAM is used as a cache memory. Therefore, DRA
Although the access time is shorter than that of M, it is difficult to secure the required storage capacity in a physically limited space because the integration degree is low and the cost is high. As a result, there is a problem that the hit rate is high in a physically limited space, and it is not possible to construct an effective data processing unit in terms of cost.

An object of the present invention is to provide a data processing device capable of obtaining a high hit rate in a physically limited space and with an inexpensive structure.

[0007]

In order to achieve the above-mentioned object, the present invention provides a recent DRAM access time of 30 ns.
Paying attention to such extremely high speed, the cache memory is composed of DRAM, and the flag indicating the validity of the data in the cache memory is stored in the cache controller for each data access unit. A flag storage unit, a flag setting unit that sets a corresponding flag in the flag storage unit to be valid when the data is accessed, and a corresponding flag is read from the flag storage unit when the data is accessed, and the flag is set to valid or invalid of the access data And output means for outputting as a signal indicating.

Further, a refresh circuit for refreshing the cache memory only in the standby state of the data processing unit is further provided in the cache controller.

[0009]

According to the above means, first, the flag of the flag storage means is "invalid" in the initial state. However, when data is written to an arbitrary cache address, it is set to "valid" by the flag setting means in parallel with this writing operation.

When the cache address corresponding to the flag in the "valid" state is again accessed (read or write operation) within the refresh time defined in the DRAM characteristic table, the refresh circuit refreshes the data. The data is retained by repeating this process after being reactivated. At this time, the flag is also set to the "valid" state again.

However, if there is no access even after the refresh time defined in the DRAM characteristic table has passed, the data at the cache address corresponding to the flag in the "valid" state is automatically erased. Along with this, the flag is set to the “invalid” state.

On the other hand, when the cache memory is accessed, the flag corresponding to the access unit is output.
If this flag is in the "enabled" state,
Since the data to be accessed existed in the cache memory, the read request to the main storage device does not occur. However, when it shows the "invalid" state, the flag itself is used as a read request to the main memory,
The access target data is read from the main storage device, transferred to the data processing unit, and also stored in the cache memory.

That is, in the present invention, the data is maintained if the DRAM is accessed within the refresh time specified in the characteristic table, and the data is automatically erased if not accessed within the refresh time. If the access from the data processing unit is performed within the refresh time specified in the DRAM characteristic table,
It is characterized in that the validity of the data in the cache memory is guaranteed, otherwise the validity is not guaranteed and the access target data is read from the main storage device. Therefore, when the data processing unit is constantly operating, no dedicated refresh circuit is needed. Also,
Under the condition that the cache addresses in the “invalid” state always exist in a predetermined amount or more, a means for discarding old data is not required.

A dedicated refresh circuit is added only when the data processing unit is in a standby state.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a detailed structure of a cache control unit which is an essential part of the present invention is shown.

The cache control unit 1 of this embodiment comprises a cache buffer 2 for storing data,
Address array buffer 3 for storing access address data of data stored in the cache buffer 2
A cache memory 4 composed of and is provided.

The cache buffer 2 and the address array buffer 3 are composed of DRAM. The cache buffer 2 and the address array buffer 3 have 512K columns in the row direction and 4 rows in the column direction (R
OW), 4M in which the data width of each row is 2 bytes
It is set to the storage capacity of bytes. In this case, the columns and rows of the cache buffer 2 and the address array buffer 3 are in one-to-one correspondence, and one row in each column serves as a data access unit.

Further, the cache control unit 1
Is an access address register 5 for storing access address data from a data processing unit (not shown).
Is provided.

Since the access address data from the data processing unit is 32 bits, the access address register 5 is composed of a 32-bit register, of which the bit 1 of the 0th byte to the bit 2 of the 1st byte. It is used as the address comparison unit 6, and the bits 3 to 4 of the lower 1st byte are used as the address search unit 7. That is, the address search unit 7 is used as column address data of the cache buffer 2 and the address array buffer 3, and the upper address comparison unit 6 is used for comparison with the address data read from the 4th row of the corresponding column. .

Here, in ROW0 to ROW3 of each column of the address array buffer 3, the upper 11 bits of the access address data when the main storage device is accessed, that is, the address data having the same configuration as the address comparison unit 6 is a real address. Data (RA) 8 is written, and a valid flag 9 indicating that the data in the corresponding storage position of the cache buffer 2 is valid is written in the lower 1 bit.

Therefore, the address data of the address comparison unit 6 is compared with the address data read from the 4th row of the corresponding column of the address array buffer 3, and when there is the matched address data, the R indicating the ROW position is compared.
OW information 11 and in-cache information 12 indicating that the access target data existed in the cache memory 4.
A real address match detection circuit 10 that outputs (“1” with data) is provided.

Further, a refresh circuit 13 for refreshing the cache memory 4 is provided.
The refresh circuit 13 includes a refresh address generation circuit 14 that outputs refresh address data,
The refresh address data is output at regular intervals only when the system wait signal W indicating that the data processing unit is on standby is "1" or only when the refresh request signal R is "1". There is.

The reason why the refresh address data is output only when the data processing unit is in the standby mode is that cache access frequently occurs when the data processing unit is in operation, and this causes a conflict with the cache access. This is to prevent the performance from decreasing.

On the other hand, on the cache buffer 2 side, based on the in-cache information 12 and the ROW information 11, the data of the cache hit ROW is selected and is output as the read data 15, and the cache hit ROW is selected. A selector is provided.

Further, the in-cache information 12 is inverted, and the not-in cache information Nin is input to the memory control unit 19 as a read request signal to the main storage device (or the memory in the upper hierarchy of the cache memory). When the data to be accessed is read by the read request signal, the read data is input to the register 21 via the instruction control unit 20 and written to the ROW position of the corresponding column of the cache buffer 2 via the selector 17. At this time, the upper 11 bits of the access address are written as the real address data 8 and the valid flag 9 of "1" is written in the ROW position of the column designated by the address search unit 7 of the access address data.

The operation of the above configuration will be described below.

First, when the memory read request is output from the data processing unit, the in-cache information 12 is set in the initial state where no data exists in the cache memory 4.
Becomes "0". Therefore, the not-in cache information N
in becomes “1”.

This not-in cache information Nin is input to the memory control unit 19 as a read request signal to the main storage device (or the memory in the upper hierarchy of the cache memory).

In parallel with this, the upper 11 bits of the access address data input to the access address register 5 are designated by the real address data 8 and the valid flag 9 of "1" is designated by the address retrieval unit 7 of the access address. Written to the ROW position of the column.

On the other hand, the data to be accessed read from the main memory by the read request signal is input to the register 21 via the instruction control unit 20 and written to the ROW position of the corresponding column of the cache buffer 2 via the selector 17. Be done.

Next, when a memory read request is output from the data processing unit, if there is data in the cache memory 4, the address search unit 7 specifies the column position of the address array buffer 3 and the column position is specified. 4 sets of real address data 8 and valid flag 9 are read.

These four sets of real address data 8 and valid flag 9 are input to the coincidence detecting circuit 10 and compared with the address data of the address comparing section 5. As a result of this comparison, if the valid flag 9 is "1" and there is matching address data, the access address is the DRAM.
Since the access has been made within the refresh time, the in-cache information 12 becomes "1" by the valid flag 9 of "1", and the not-in cache information Nin becomes "0", and the memory control unit 19 and the instruction. The control unit 20 is notified of the cache hit. At this time, since the cache hit column is accessed within the refresh time of the DRAM, it is activated to the content of the original address data without special refresh.

At the same time, the cache hit ROW information 11 is input to the selector 16 and the cache buffer 2
The data read from the corresponding ROW position of is selected and input as read data 15 to the instruction control unit 20. In this cache buffer 2 as well, since the column having a cache hit has been accessed within the refresh time of the DRAM, it is activated to the original data content without any special refresh.

Next, when a write request is issued from the data processing unit and write address data is input to the access address register 5, as in the case of reading,
The column position of the address array buffer 3 is designated by the address search unit 7, and four sets of real address data 8 and valid flag 9 are read from the column.

These four sets of real address data 8 and valid flag 9 are input to the coincidence detection circuit 10 and compared with the address data of the address comparison unit 5. If the result of this comparison is that the valid flag 9 is "1" and there is matching data, it means that the access address has been accessed within the refresh time of the DRAM.
The valid flag 9 of "1" causes the in-cache information 12 to become "1" and the not-in cache information Nin to become "0".
9 and the instruction control unit 20 are notified of the cache hit. Then, the ROW information 11 having the cache hit is input to the selector 17, and the write data 21 input through the instruction control unit 20 is input to the cache buffer 2 by the selector 17.
Are written to the corresponding ROW positions of the.

In this case, since the cache hit column of the address array buffer 3 has been accessed within the refresh time of the DRAM, it is activated to the content of the original address data without special refresh.

However, as a result of the comparison in the coincidence detection circuit 10, when the valid flag 9 is "0", the column position is accessed for more than the refresh time of the DRAM and data cannot be guaranteed, or in the initial state. Since it means that there is, the address data of the address comparison unit 5 is written as real address data 8 in the empty ROW position of the column, and the valid flag 9 of “1” is written further below it. On the other hand, the write data 21 is written in the corresponding ROW position of the cache buffer 2.

On the other hand, when the data processing unit enters the standby state and the system wait signal W becomes "1", refresh address data is generated from the refresh address generation circuit 14 at a constant time interval shorter than the refresh time of the DRAM, and the cache buffer is generated. 2 and the address array buffer 3 are sequentially refreshed in column units.

By this refresh operation, the data and address data in the cache buffer 2 and the address array buffer 3 are retained so as not to disappear even in the standby state of the data processing unit.

This is the same when the refresh request signal R is generated.

By the way, in a multiprocessor system or the like, the data in the cache memory may be forcibly erased simultaneously in order to control the coincidence of the data. In the cache memory 4 of this embodiment, the valid flag 9 is used.
Can be realized by setting all of them to "0" all at once, which has the advantage of speeding up.

As described above, in this embodiment, the cache memory 4 is composed of DRAM, and the valid flag 9 indicating the validity of the data in the cache memory 4 is provided in the cache control unit 1 for each data access unit. The valid flag 9 is stored, and the valid flag 9 is set valid each time the data is accessed, and the data is updated only when the valid flag 9 indicates invalid when the data is accessed.

That is, the data is maintained if the DRAM is accessed within the refresh time defined in the characteristic table, and the data is automatically erased if the DRAM is not accessed within the refresh time. If the access is performed within the refresh time specified in the DRAM characteristic table, the cache memory 4
The validity of the data in the storage is guaranteed, otherwise the validity is not guaranteed, and the access target data is read from the main storage device.

Therefore, when the data processing unit is constantly operating, no dedicated refresh circuit is required. Further, there is an advantage that no means for discarding old data is required under the condition that the cache addresses in the “invalid” state always exist in a predetermined amount or more.

Further, the refresh operation is executed only when the data processing unit is on standby,
There is an advantage that the competition with the cache access of the data processing unit is eliminated and the performance is prevented from being deteriorated.

In particular, there is an advantage that a high hit rate can be obtained in a physically limited space and with an inexpensive structure. For example, when the cache memory composed of 256 Kbytes of SRAM is replaced with the cache memory of 4 Mbytes of DRAM, the storage capacity becomes 16 times, and the frequency of no cache hits is significantly reduced. As a result, the overhead at the time of block transfer of data is also significantly reduced. Moreover, the cost is reduced.

Therefore, the cache memory control unit 1 and the data processing unit are combined into a single chip L.
If configured as SI, an inexpensive and high-performance microprocessor can be realized.

In this embodiment, the flag indicating that the data exists in the cache memory and the valid flag indicating whether the data are valid are shared, but they may be separated. When they are separated, it is sufficient to notify that the data is valid only when both flags are "1".

The address search unit 7 may be configured to search the address array buffer 3 by dividing it into two stages of a column address and a class address.

[0051]

As described above, in the present invention,
The cache memory is composed of a DRAM, and a flag indicating the validity of the data in the cache memory is stored in the cache control unit for each access unit of the data, and the corresponding flag is set valid for each access of the data. In addition, since the data is configured to be updated only when the corresponding flag indicates invalid when accessing the data, if the data processing unit is always operating, a dedicated refresh circuit becomes unnecessary and Under the condition that the cache address in the state always exists in a predetermined amount or more, there is an effect that means for discarding old data is not required.

Further, by executing the refresh operation only when the data processing unit is in the standby state,
There is an effect that contention with the cache access of the data processing unit is eliminated and the performance is prevented from being deteriorated.

In particular, it is possible to obtain a high hit rate in a physically limited space and with an inexpensive structure, and it is possible to greatly reduce the overhead at the time of block transfer of data.

Further, if the cache memory control unit and the data processing unit are constructed as a single chip LSI, there is an effect that an inexpensive and high performance microprocessor can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

1 ... Cache control unit, 2 ... Cache buffer, 3 ... Address array buffer, 9 ... Valid flag, 12 ... In cache information, 13 ... Refresh circuit.

Claims (4)

[Claims] 1. A data processing device comprising a cache memory and a cache controller for controlling the cache memory between a main memory device and a data processing unit, wherein the cache memory is composed of a DRAM, and the cache controller is provided in the cache controller. A flag storage unit that stores a flag indicating the validity of data in the cache memory for each access unit of data; a flag setting unit that sets the corresponding flag of the flag storage unit to be valid when the data is accessed; A data processing device, characterized by further comprising: output means for reading a corresponding flag from the flag storage means and outputting the flag as a signal indicating whether the access data is valid or invalid. 2. The data processing device according to claim 1, wherein the data to be accessed is read from the main storage device only when the flag indicates invalid. 3. The data processing device according to claim 1, further comprising a refresh circuit provided in the cache controller for refreshing the cache memory only in a standby state of the data processing unit. 4. The data processing unit, cache memory and cache controller are combined into a single chip L.
4. The data processing device according to claim 1, wherein the data processing device is configured by SI.