JPS5841594Y2 - signal mixing circuit - Google Patents

signal mixing circuit

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Publication number
JPS5841594Y2
JPS5841594Y2 JP135878U JP135878U JPS5841594Y2 JP S5841594 Y2 JPS5841594 Y2 JP S5841594Y2 JP 135878 U JP135878 U JP 135878U JP 135878 U JP135878 U JP 135878U JP S5841594 Y2 JPS5841594 Y2 JP S5841594Y2
Authority
JP
Japan
Prior art keywords
signal
circuit
waveform
mixing circuit
pulse train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP135878U
Other languages
Japanese (ja)
Other versions
JPS54105518U (en
Inventor
俊男 三嶋
Original Assignee
株式会社河合楽器製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社河合楽器製作所 filed Critical 株式会社河合楽器製作所
Priority to JP135878U priority Critical patent/JPS5841594Y2/en
Publication of JPS54105518U publication Critical patent/JPS54105518U/ja
Application granted granted Critical
Publication of JPS5841594Y2 publication Critical patent/JPS5841594Y2/en
Expired legal-status Critical Current

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  • Electronic Switches (AREA)

Description

【考案の詳細な説明】 本考案は構成を極めて簡易にした電子楽器における信号
混合回路に関する。
[Detailed Description of the Invention] The present invention relates to a signal mixing circuit for an electronic musical instrument with an extremely simple configuration.

電子楽器における従来の信号混合回路は第1図または第
2図に示すものが知られている。
As a conventional signal mixing circuit for an electronic musical instrument, the one shown in FIG. 1 or 2 is known.

第1図に示す回路図においてA1.A2.A8は異なる
音を高に対応するパルス列の印加端子を示し、一方C点
に印加された押鍵時のアタック信号を微分・整流し、D
点のエンベロープ波形を得る。
In the circuit diagram shown in FIG. 1, A1. A2. A8 indicates the application terminal of the pulse train corresponding to the high pitch of different tones, and on the other hand, the attack signal applied to point C when the key is pressed is differentiated and rectified, and D
Obtain the envelope waveform of the point.

D点の波形は、B1 t B2 s B3の各点におい
て前記パルス列により変調され、矩形波が断続しながら
減衰する波形となり、これらを混合してE点に示す波形
を得る。
The waveform at point D is modulated by the pulse train at each point B1 t B2 s B3, resulting in a waveform in which rectangular waves are intermittently attenuated, and these are mixed to obtain the waveform shown at point E.

この回路は信号線各々にダイオードが最低2個必要であ
る。
This circuit requires at least two diodes for each signal line.

また第2図に示す回路においてFET1乃至FET3は
PチャネルMO8FETを示し、他は第1図と同様のも
のである。
Further, in the circuit shown in FIG. 2, FET1 to FET3 are P-channel MO8FETs, and the others are the same as in FIG. 1.

第2図においてFETはエンベロープ波形により当初十
分な電流が流れ徐徐に減少して行く。
In FIG. 2, a sufficient current initially flows through the FET due to the envelope waveform, and the current gradually decreases.

したがってFETのドレイン電極において信号を混合す
れば、E点に示す波形が得られる。
Therefore, if the signals are mixed at the drain electrode of the FET, the waveform shown at point E can be obtained.

この回路はパルス列信号入力線各線にFETを接続する
必要があり、信号入力線が多数となれば高価になる。
This circuit requires an FET to be connected to each pulse train signal input line, and if the number of signal input lines increases, it becomes expensive.

また各FETにおいて信号振幅がカットオフ電圧まで降
下してくると振幅は急激に零レベルに落込むから、混合
信号が極めて不自然に聞こえるという欠点があった。
Furthermore, when the signal amplitude drops to the cutoff voltage in each FET, the amplitude suddenly drops to zero level, which has the disadvantage that the mixed signal sounds extremely unnatural.

本考案の目的は極めて簡易化した構成の電子楽器におけ
る信号混合回路を提供することにある。
An object of the present invention is to provide a signal mixing circuit for an electronic musical instrument with an extremely simplified configuration.

以下第3図に示す本考案実施例について説明する。The embodiment of the present invention shown in FIG. 3 will be described below.

異なる音高に対応するパルスがA1 p A2− A3
y点に印加され、一方押鍵時のアタック信号を微分・
整流しエンベロープ波形を得てD点よりFETに印加す
る。
Pulses corresponding to different pitches are A1 p A2- A3
Differentiate the attack signal applied to the y point and when one key is pressed.
A rectified envelope waveform is obtained and applied to the FET from point D.

ゲート素子としての一個のFETはPチャネルMO8型
とし、前記エンベロープ波形の印加前は十分導通状態に
在るよう直流的に制御している。
One FET as a gate element is a P-channel MO8 type, and is DC-controlled to be sufficiently conductive before application of the envelope waveform.

(出力E点にこの時出力信号が生じない)。エンベロー
プ波形の立上りによりFETは−開(OFF)の状態に
なり次いでエンベロープ波形にはゾ逆比例して電流が流
れ始める。
(At this time, no output signal is generated at output point E). The rise of the envelope waveform causes the FET to be in a -open (OFF) state, and then a current begins to flow through the envelope waveform in inverse proportion to the current.

したがってB、 、 B2. B3点における波形は8
4点の横に示す波形図のようにエンベロープ波形で変調
した矩形波となるからこれを混合してE点の波形を得る
Therefore, B, , B2. The waveform at point B3 is 8
As shown in the waveform diagram shown next to the four points, a rectangular wave modulated by the envelope waveform is obtained, and these are mixed to obtain the waveform at point E.

AHy A2 y A3点の数即ち入力パルス列の数を
増加しても抵抗素子とダイオードが若干増加するのみで
、高価なゲート素子を多数要しないから、構成が極めて
簡易である。
Even if the number of AHy A2 y A3 points, that is, the number of input pulse trains is increased, the number of resistive elements and diodes only increases slightly, and a large number of expensive gate elements are not required, so the configuration is extremely simple.

ゲート素子は適当な直流バイアスをかけることによりバ
イポーラトランジスタを使用することも可能である。
It is also possible to use a bipolar transistor as the gate element by applying an appropriate DC bias.

FETを使用することによりエンベロープ波形印加端子
り点から見た入力インピーダンスを高く保持することが
でき、ドレイン端子を接地しているので、従来の回路に
生じたようなカットオフ電圧による波形に段差を生じる
こともない。
By using a FET, the input impedance seen from the envelope waveform application terminal can be maintained high, and since the drain terminal is grounded, there is no step in the waveform caused by the cutoff voltage that occurs in conventional circuits. It never happens.

このようにして本考案によれば、極めて簡易化した構成
の信号混合回路が安価に得られ、そして入力のパルス波
形の信号線が多数本になってもゲート素子を増加させる
必要がないため、回路の調整が簡易に済み、且つ従来例
を示す第1図では回路の入力インピーダンスが低下し波
形歪を発生することがあったが、本考案ではその恐れが
なく、良好な混合波形が得られる効果を有する。
In this way, according to the present invention, a signal mixing circuit with an extremely simplified configuration can be obtained at low cost, and even if the number of input pulse waveform signal lines increases, there is no need to increase the number of gate elements. The circuit can be easily adjusted, and in the conventional example shown in Figure 1, the input impedance of the circuit would drop and waveform distortion would occur, but with the present invention, there is no such risk and a good mixed waveform can be obtained. have an effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は従来の信号混合回路を示す図、第3図
は本考案実施例を示す回路図である。 AHm A2 p A3・・・・・・パルス列印加端子
、C・・・・・・アタック信号印加端子、E・・・・・
・信号混合回路出力端子。
1 and 2 are diagrams showing a conventional signal mixing circuit, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. AHm A2 p A3... Pulse train application terminal, C... Attack signal application terminal, E...
・Signal mixing circuit output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子楽器における押鍵時のアタック信号より得られたエ
ンベロープ波形によって異なる音高に対応するパルス列
信号をゲート回路で変調しその後混合する回路において
、前記ゲート回路は単一のFET素子で構成し、そのゲ
ート電極に前記アタック信号を印加し、ドレイン電極は
接地し、ソース電極は前記パルス列の各信号線混合用抵
抗の中間点と各々非可逆性素子を介して接続されること
を特徴とする信号混合回路。
In a circuit in which a gate circuit modulates pulse train signals corresponding to different pitches according to an envelope waveform obtained from an attack signal when a key is pressed in an electronic musical instrument, and then mixes the signals, the gate circuit is configured with a single FET element, and Signal mixing characterized in that the attack signal is applied to the gate electrode, the drain electrode is grounded, and the source electrode is connected to the intermediate point of each signal line mixing resistor of the pulse train through each irreversible element. circuit.
JP135878U 1978-01-10 1978-01-10 signal mixing circuit Expired JPS5841594Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP135878U JPS5841594Y2 (en) 1978-01-10 1978-01-10 signal mixing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP135878U JPS5841594Y2 (en) 1978-01-10 1978-01-10 signal mixing circuit

Publications (2)

Publication Number Publication Date
JPS54105518U JPS54105518U (en) 1979-07-25
JPS5841594Y2 true JPS5841594Y2 (en) 1983-09-20

Family

ID=28803438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP135878U Expired JPS5841594Y2 (en) 1978-01-10 1978-01-10 signal mixing circuit

Country Status (1)

Country Link
JP (1) JPS5841594Y2 (en)

Also Published As

Publication number Publication date
JPS54105518U (en) 1979-07-25

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