JPS5840977U - Frequency stabilization circuit - Google Patents
Frequency stabilization circuitInfo
- Publication number
- JPS5840977U JPS5840977U JP13558981U JP13558981U JPS5840977U JP S5840977 U JPS5840977 U JP S5840977U JP 13558981 U JP13558981 U JP 13558981U JP 13558981 U JP13558981 U JP 13558981U JP S5840977 U JPS5840977 U JP S5840977U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- circuit
- input
- stabilization circuit
- frequency converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006641 stabilisation Effects 0.000 title claims description 3
- 238000011105 stabilization Methods 0.000 title claims description 3
- 230000000087 stabilizing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Superheterodyne Receivers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の周波数安定化回路のブロック図、第２図
は本発明の実施例のブロック図である。
１：周波数ずれ検出回路（例えばＡＰＣ回路）、２：直
流増幅器、３ ：ＶＣＯ１４：周波数変換器、５：″上
限電圧設定回路、６：下限電圧設定回路、Ｖｃ二制御電
圧、Ｖ工：制御下限電圧、ｖＨ二制御上限電圧。FIG. 1 is a block diagram of a conventional frequency stabilization circuit, and FIG. 2 is a block diagram of an embodiment of the present invention. 1: Frequency shift detection circuit (for example, APC circuit), 2: DC amplifier, 3: VCO14: Frequency converter, 5: Upper limit voltage setting circuit, 6: Lower limit voltage setting circuit, Vc2 control voltage, V: Control lower limit Voltage, vH two control upper limit voltage.
Claims (1)
数の信号を出力とする周波数変換器と、上記第１の入力
の周波数のずれを検出する回路と、′該回路により検出
した信号にもとづいて出力信号の周波数を変化させ該出
力信号を上記周波数変換器の第２の入力として供給する
電圧制御発振器とを備え上記周波数変換器の出力周波数
を安定化する回路において、上記電圧制御発振器の入力
回路に直流電源からダイオードと可変抵抗器の直列回路
を並列に接続した上限および下限電圧設定回路を設けた
ことを特徴とする周波数安定化回路。 、a frequency converter having first and second inputs and outputting a signal having a frequency of the sum or difference of the two human powers; a circuit for detecting a frequency deviation of the first input; A voltage controlled oscillator that changes the frequency of an output signal based on a detected signal and supplies the output signal as a second input of the frequency converter, the circuit stabilizing the output frequency of the frequency converter, A frequency stabilization circuit characterized in that an input circuit of a voltage controlled oscillator is provided with an upper and lower limit voltage setting circuit in which a series circuit of a diode and a variable resistor is connected in parallel from a DC power supply. ,
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13558981U JPS5840977U (en) | 1981-09-14 | 1981-09-14 | Frequency stabilization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13558981U JPS5840977U (en) | 1981-09-14 | 1981-09-14 | Frequency stabilization circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5840977U true JPS5840977U (en) | 1983-03-17 |
Family
ID=29928947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13558981U Pending JPS5840977U (en) | 1981-09-14 | 1981-09-14 | Frequency stabilization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840977U (en) |
-
1981
- 1981-09-14 JP JP13558981U patent/JPS5840977U/en active Pending
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