JPS5840752B2 - graphic display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for displaying rectangular figures using a cathode ray tube, and in particular, it is possible to display a plurality of rectangular figures on the screen of the cathode ray tube based on given side position information. This is what I did.

Conventionally, most graphic display devices have been stroke-type graphic display devices that use storage tubes, and raster scan-type graphic display devices that use normal cathode ray tubes have been limited by the size of the storage device, the structure of the storage device, and There are drawbacks to the reliability and price of the graphics generation hardware.

However, the stroke-type graphic display device is also expensive, and it is desired to realize an inexpensive graphic display device.

On the other hand, there are some fields where only a rectangular display function is effective, such as in IC layout design or printed circuit board design on which ICs are mounted.

In view of the above-mentioned fx points, the present invention classifies the display screen into grid point pixels that can be specified manually and interlattice pixels that cannot be specified by input, and provides a grid point memory for displaying the grid point raster and the interlattice raster. and an interlattice memory, a first display register that holds display data read from them, and a second display register that holds the data of the first display register with a delay of one pixel. , in which a rectangular figure whose space between the top and bottom sides is the display data of the grid point memory and whose space between the left and right sides is specified by the first and second display registers is displayed along with its interior. It is.

Hereinafter, the present invention will be explained based on illustrated embodiments.

FIG. 1 is a block diagram of essential parts of a raster scan type rectangular graphic display device having a resolution of 128×64, which is an embodiment of the present invention.

In the figure, 1 is a grid information register that has side information of each rectangle on the rask, and this register has bit positions corresponding to grid point pixels on the left and right sides of the rectangle on the front screen that are 1".
This is a 128-bit memory, and the data is updated every time the side information of each rectangle changes by an external computer or the like.

Reference numeral 2 is an interlattice memory which is a storage means for holding data for displaying a grid point raster, and 3 is a grid point memory which is a storage means for holding data for displaying a grid point raster. It's memory.

Each is a 128-bit memory configuration.

8, 9, and 10 are impark gates that invert the data of the lattice point memory 3, interlattice memory 2, and lattice information register 1, respectively; 4 is a NAND AND gate; and 6 is a NAND gate.
is an AND gate, and 7 is an OR gate.

FIG. 2 shows a rectangular pixel configuration, and in this embodiment, lattice point rasters and inter-lattice rasters occur alternately.

A rectangle is displayed by grid point pixels and inter-grid pixels on a grid point raster, and by inter-grid pixels on an inter-grid raster.

Next, 128-bit data transfer including edge information will be described with reference to FIG.

Data transfer from the grid information register 1 to the interlattice memory 2 corresponds to the display operation of the interlattice raster R3T2, and data transfer from the interlattice memory 2 to the grid point memory 3 corresponds to the display operation of the grid point raster R8T1. Each is done synchronously.

That is, the lattice point memory 3 is sequentially read out by the display operation of the lattice point raster, and the data at the corresponding bit position of the interlattice memory 2 is written into the bit position of the read data.

Data transfer from the lattice information register 1 to the lattice memory 2 is also performed in the same manner in synchronization with the display operation of the lattice raster.

On the other hand, the data transferred to the lattice point memory 3 from the lattice information register 1 is ORed with the data in the lattice point memory 3.
and written into the lattice point memory 3 during lattice raster display operation.

That is, the information 1111+ in the lattice information register 1 and the lattice point memory 3 is inverted by the inverter gates 10 and 8 and applied to the NAND gate, so that the information written to the lattice point memory 3 becomes 1''.

This is to display the lattice raster corresponding to the lower side of the rectangular graphic display and to prohibit the display of inter-lattice rasters.The lattice information register 1 contains (
Side information corresponding to each raster up to the lower side position -1) is sequentially given.

FIG. 3 shows the above-mentioned data transfer.

Now, in FIG. 1, reference numeral 11 denotes a first display register that converts data sequentially read out from the lattice point memory 3 into display data.
'' to the next even-numbered data ``1'' are held as pixel display data.

A second display register 12 holds the output data of the first display register 11 with a delay of one pixel.

This second display register 12 is for displaying pixels on the right side of the rectangle, and the grid point memory 3 stores left side position information and right side position information of each rectangle as side information.

Reference numeral 13 denotes an OR gate that combines the data of the first display register 11 and the second display register 12 to produce display data.

14 is an AND gate for sampling display data output from the OR gate 13, and 15 is a cathode ray tube.

A signal generating circuit 16 generates a clock signal Φ5 to be applied to the first display register 11, a clock signal Φ2 to be applied to the second display register 12, a sampling signal SMP, and the like.

17 is a column counter that specifies the memory addresses of the lattice point memory 3 and the interlattice memory 2, and 18 is a row counter that specifies the lattice point raster R8T 1 and the interlattice raster R8T 2.

FIG. 4 is a time chart showing the relationship between the lattice point memory 3 and display data.

Although the purpose of this embodiment is monochrome display, it is also possible to display a rectangle in multiple colors by providing a plurality of interlattice memories, grid point memories, first display registers, second display registers, etc. Furthermore, by providing a color priority circuit for display data, it is also possible to display overlapping rectangles in multiple colors.

As is clear from the above description, the present invention classifies the display screen into grid point pixels for which input can be specified and interlattice pixels for which input cannot be specified, and uses grid point memory to display the grid point raster and the interlattice raster. (a first storage means) and an interlattice memory (a second storage means); By providing a second display register that holds the display data of the display register with a delay of one pixel, the upper and lower sides can be specified by the grid point memory, and the left and right sides can be specified by the first and second display registers. It is configured to display the inside of a rectangle, and by providing side information, it is possible to easily display a rectangular figure with a simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a rectangular pixel configuration in the embodiment, FIG. 3 is a diagram showing data transfer in the embodiment, and FIG. The figure is a time chart of the same embodiment. 1... Lattice information register, 2... Inter-lattice memory, 3... Lattice point memory, 4...
・NAND gate, 5゜6.14...AND gate, 7,13...OR gate, 8,8,10
...Inverter gate, 11...1st
display register, 12... second display register, 15... cathode ray tube, 16... signal generation circuit, 17... column counter, 18...・・・・・・
- Row counter.

Claims (1)

[Claims] 1 This is a raster scan graphic display device in which the display screen is composed of mXn grid point pixels that can be manually specified and kmXkn (k is an integer) grid point pixels that cannot be specified by input. First and second storage means each having a number of bits of m for displaying a grid point raster and an interlattice raster, and a first display register that holds display data read from the first and second storage means. and a second display register that holds the data of the first display register with a delay of one pixel, and the area between the upper side and the lower side is specified by the display data of the first storage means,
A graphic display device characterized by displaying a rectangular graphic whose length between the left side and the right side is specified by the display data of the first and second display registers.