JPS5839367A - Quantity control system - Google Patents

Abstract

PURPOSE:To accurately store the time when the stock has run out by updating the previously stored quantity according to input operation, and then storing the time just when the updated quantity reaches a prescribed value. CONSTITUTION:The mode switch of an input part 2 is placed at the set mode side and the total stock of each department is set. Then, the mode switch is placed at the registration mode position and registration processing operation is started. Namely, data on each department which corresponds to an operated departmentalized key is read out of a memory 3 to a CPU through a data bus DI according to the key operation of the input part 2. Then, the CPU1 performs the registration processing operation to update the total stock. Then, departmentalized data stored in the CPU is sent out to a data bus DO, and then stored in the memory 3 and also inputted to a total stock detecting circuit 4. On detecting the stock having run out, the circuit 4 permits a write control circuit 5 to output gate opening and closing signals FR and TM, and consequently a sold-out flag 1 is written in the memory 3, and the current time is also written.

Description

[Detailed Description of the Invention] This invention is a method for increasing the number of products such as the number of items in stock.
Regarding Vi Gakubanshiki.

Conventionally, when managing the number of products in stock, the number of items in stock is set for each department on the electronic register, and when the number of items in stock reaches 90 or a specified failure occurs, the operator is asked to print or display the number of items in stock. was. however,
When checking the stock quantity later, it is impossible to determine when the stock quantity of the out-of-stock item was sold out, so it is difficult to determine whether the stock-out occurred at an appropriate time just before closing.
It was not possible to determine whether the item was out of stock at the correct time.

This invention was made based on the above-mentioned circumstances, and its purpose is to update the number stored in advance according to an input operation, and to store the current time when the updated number of 115 reaches a predetermined number. An embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 shows a circuit configuration diagram of the main parts of this invention. In the figure, 1 is a CPU, and this 0PUI outputs a timing signal KP to the input section 2. Signal KP is selected according to - during operation, key manual power II! It is input as the number KI. Also, 0PUl is sent to memory 3 via address bus AB.
Address No. 1N is output to the memory 3, and the data read from the memory 3 is inputted via the data bus DI. Also,
0PUI performs various processing such as arithmetic operations according to the input data, and outputs the processed data to the memory 3 and the inventory quantity detection circuit 4 via the data bus DO. Further, at the same time as the inventory quantity data is output, the inventory quantity detection circuit 4 outputs a reset pulse PR and a set signal PS indicating that the inventory quantity data is being outputted. Further, the KOPUI outputs display data and print data corresponding to a display section and a print section (both not shown), and receives control signals from the print section. The inventory a detection circuit 4 receives the input reset pulse P.
The 0 write control circuit 5 generates a control signal a based on R and the set signal PS and outputs it to the write control circuit 5. The 0 write control circuit 5 generates a control signal a based on the input control signal aK and outputs the gate opening notes FR and TM to the three-state buffer 6, respectively. Output to the gate terminal of .7. The input side of this three-state buffer 6 is always Q
2 ft-salt'1'' signal is input, and the 3rd date h7a70 input 4 is ti1g1w!r8
The output sides of these three-state buffers 6.7 are connected to the data bus DO, to which current time data measured by the three-state buffers 6.7 and 6.7 are always inputted.

The input section 2 includes a numeric key, a department key, and a structure/'V4 key.
In addition to the keys, there are mode switches for specifying various modes such as ``setting,''``registration,'' and ``inspection.'' (9) The memory 3 is provided with departmental memories corresponding to the plurality of departmental keys, and each departmental memory stores data for that department, status data indicating the input limit number of digits, etc. Storage area, storage area to store unit price data of products in that department, sales of products in that department 11M
A storage area to store the number of products in stock, a storage area to store the current inventory quantity of the product in that department, a flag storage area to store a flag indicating that the inventory quantity is sold out.2% Memory to store the sold-out time of the inventory quantity. area is provided.

Figure 5g2 shows the inventory quantity detection circuit 4 and write control circuit 5.
4-bit parallel data inputted to the inventory quantity detection circuit 4 via the data bus DO is inputted to the AND circuit 402 via an OR circuit 401. The input set signal PS is input to an AND circuit 402 and an inverter 403, and the output of the AND circuit 402 is applied to R8.
The output of the inverter 403 is input to the AND circuit 405, respectively.
It is input to the @ input terminal, and its Q output is input to the AND circuit 405. The output from this AND circuit 405 is sent to the delay circuit 501 constituting the write control circuit 5 as the control signal a.
．． 502 and an AND circuit 503, respectively. And M#.

The circuit wI501 delays the input control signal a by one bit time and outputs it to the inverter 504& and the AND circuit If6505.
Enter in 03. On the other hand, the delay circuit 502 delays the input control signal a by a predetermined time required to transfer the current time and outputs it to the inverter 506.
The output of 6 is input to the AND circuit 505, and the gate opening signal F'R%TM is outputted from the AND Ig1w & 503.505, respectively.

Next, the operation of this invention will be explained. First, before starting registration, the mode switch of the input unit 2 is designated to the "setting" mode, and the number keys, department keys, etc. are operated to set the number of products in stock for that department. Thereafter, the mode switch is designated to the "registration" mode, and in this state, the operation according to the flow shown in FIG. 3 is also performed.

That is, in step S1, the process waits until the key operation for the input $2 is executed, and when it is determined that there is human power on the key, the process moves to step S2. In step S2, it is determined whether or not the operated key is a departmental key. In step 8s, various processes corresponding to the operation keys are executed with UP and Ul, and then the process returns to step S1. Said step 8
If it is determined in step S2 that the department key has been operated 4f, the process moves to step S4. In step S4, each department data of the 11 number, price, stock quantity, sold-out flag, and sold-out time of the department memory corresponding to the operated department key of the memory 3 is sequentially read out to 0PU1 via the data bus DIt''. Next, the process moves to step 8s, where it is determined at 0PUI whether or not a light-out flag is stored in the flag area F. If it is determined that there is no sold-out flag, it is assumed that there is a quantity in stock, and the process moves to step S6. Step 8
115a according to the nine departmental data entered in 6.
, a registration error 4IIb operation that adds up to the performance data is executed. Next, the process moves to step S7, and an operation in which "1" is subtracted from the current 4-year-old data is performed in L) PU1. If it is determined in the step S@ that there is a sold-out flag in the flag area F, it is assumed that there are no rhinos present, and the process moves to step S8. In the execution of step S8, "l" is added to the current inventory quantity data, and this added data is 0P as data on the number of requests by customers to approve the products of the department.
Stored in the UI. After execution of either step S7 or S8, the process moves to step S.9.0 Department data such as the inventory a data stored in PUl is sent to the data bus DO, and is stored in a predetermined section of the corresponding departmental memory of the memory 3. The information is stored in the storage area, and then the process returns to step 81.

In step S, the inventory quantity data is sent out via the data bus DO, as shown in FIG. 4(A). At this time, the set signal P8 shown in FIG. Number detection circuit 4
The AND circuit 402 is connected to the [I
If the K data is [0], the output from the AND circuit 4402 is black when the set signal P8 is input, so no set signal is input to the S4 clip-flop 404. Therefore, the I11'' signal is output from the Q output terminal of the S-type clip-flop 404 to the AND circuit 405. On the other hand, since the set 1 signal PS is manually input to the AND circuit 4405 via the inverter 403, Figure (I
As shown in J, there is no output of control signal a. After the inventory quantity data "0" is output, the output of the set signal Pa is stopped. Then, "1" from the inverter 403
Since the signal is input to the AND circuit 405, the control signal a is output and input to the delay circuits 501, 502 and the AND circuit 503. At this time, as shown in FIG. Therefore, the signal 0 is output from the inno (-) 504 as shown in the figure (ladder), and as a result, the AND circuit 4503 is output as shown in the figure 0.
The gate opening signal FR is output from the gate opening signal FR. Then, there is a 1-bit time delay after the control signal a is output, and the delay circuit 5
As a result, the output of the signal C and the gate open signal FR is stopped.However, since the gate open signal PR is output, the three-state buffer 6 is opened during this time, and the memory 30 division The expiry 7 lag'''1@ is stored in the corresponding flag storage area of another memory.During this time, the control signal a continues to be output, and therefore the signal S also continues to be output.At this time, the delay circuit 5
Since there is no output from 02, the signal d continues to be output from the input circuit 506 as shown in FIG. During the output of this gate open signal TM, the gate of the three-state buffer 7 is opened, and the current time data stored in the hour hand circuit 8 is transferred to the corresponding section memory of the memory 30 as sold-out time data. It is written to the storage area. Note that the step S
In step 9, if inventory quantity data that is not "0" is output from 0PU1, this data is sent to BS type 7 lip-flop 404 via OR circuit 401 and AND circuit 402.
Since this is set, there is no output from the Q output terminal, and therefore the control signal a cannot be output, and the above-mentioned writing operation of the sold-out flag and sold-out time is not performed.

Also, set the mode switch to “inspection” mode and
When the fjm key is operated, the contents of the memory 3 are read out one carpet at a time, and the number of stocks in each department is set to "0" by visually checking the rounding printed on the recording paper in the printing section.
You can know the sold out time. Furthermore, in this embodiment, it is convenient to be able to know not only the time when the light runs out, but also the number of customer requests for the sold-out product.

In the above embodiment, the existing MD is stored as the preset number in the departmental memory of the memory 30, but the present invention is not limited to this, and the number of each type of pond, such as the planned sales quantity, may be stored.

Furthermore, in the embodiment described above, the inventory quantity data is detected when it reaches rOJ, but the present invention is not limited to this, and detection may be performed when the inventory quantity data reaches a specific value.

In addition, in the above embodiment, if the sold-out flag 72 is stored in the corresponding departmental memory of the memory 3, the stock quantity is updated to +IL, and if there is no sold-out flag, the stock quantity is updated to -l. However, IILJ#r can be incremented by +1 or -1 depending on the plants of the 1-iiL data set in advance in this way.

Further, in the embodiment described above, the current time is stored as the PAviIl time, but the current time may be stored as the date without sleep.

As explained above, according to the present invention, a preset number is stored, the number is updated according to the input operation, and when the number reaches a predetermined number, the current time is read out from the clock circuit and stored. For example, the time when an item is out of stock is clearly memorized,9 and it is possible to check whether that time is appropriate as the out-of-stock time.As a result, future product updates can be checked. It can be used as effective data for determining the number of purchases.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention. Part circuit diagram,
FIG. 2 shows detailed circuits of the existing LIE number detection circuit and integrated control circuit of the same embodiment. I-groove configuration diagram, Figure 3 is 70 of the same example.
-char), dX4 is a time chart explaining the operation of the inventory quantity ejection circuit and the write control Lgl path of the same embodiment. l......OPU, 2......Human Resources Department, 3...Memory, 4......
・・Circuit in 4 states, 5・・・1-inclusive # circuit, 6.7・・・・・・・3-state h7a,
8・・・・・・・・・Clock circuit O Fang 2 illustration tlWJ

Claims (1)

[Claims] A clock circuit that measures the current time, a first storage device that stores a preset number, and a second storage device that stores the time.
a storage means for updating the number according to an input operation; a detection means for detecting whether the updated number has reached a predetermined number Ks; A number management system comprising: control means for reading time and writing it into the storage means.