JPS5838751B2 - Periodic signal synchronization detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization detection method for monitoring periodic signals.

The synchronization detection method described here uses a first counter that counts the number of pulses of the input signal, and after synchronizing the input signal with an internal reference signal, a second counter that counts the number of synchronized pulses of both signals. The synchronization difference is detected by comparing the contents of these two counters. Before making the comparison, set the count number of the counter in advance, compare the results counted for each set number, and if they match, the counter This is a new method that allows the frequency of out-of-synchronization to be detected by resetting the counter and stopping the counter if there is a mismatch.

FIG. 1 shows an embodiment of the present invention, in which Zl is a periodic signal,
Z2 is a reference pulse signal that has the correct period that the periodic signal Z1 should originally have, 1, 4, 9゜L12, 13 are NAN
D circuit, 2, 5, 14-17 are inverters, 3, 18 are D type flip-flops, 6 is a JK type flip-flop, 7 is a first counter, 8 is a second counter, 1
0 is a 1 pulse circuit.

The operation will be explained below with reference to the timing chart of FIG.

In FIG. 2, the reference signal 〆2 is synchronized to generate a pulse approximately at the center of the first pulse Z1□ of the periodic signal 〆1, and thereafter is a pulse signal that repeats at a constant period.

Pulse Z10 of periodic signal Z1. 〆121. ”131〆1
4 are out-of-synchronization pulses indicating that they are input at different timings from the reference signal 2.

As is clear from FIG. 1, the first counter 7 is Zll.

〆1□, 113. In contrast, the second counter 8 is counted up by any pulse of signal C in FIG. Counts up by pulse generation.

In other words, in Fig. 1, the periodic signal Z1 and the reference signal 〆2 are NA.
The logical product is taken by the ND circuit 1 and applied as a clock input T to the JK flip-flop 6 via the NAND circuit 4.

However, this clock input is D type flip-flop 3.
According to the timing of the signal B shown in FIG. 2, the logical product is calculated and controlled.

Furthermore, since the JK flip-flop 6 continues to output the input signal only when a clock is applied to the signal B at the timing like the signal A, the signal C that causes the counter 8 to count up is output only at the timing of the pulse 11. Occur.

The D-type flip-flop 3 and the JK-type flip-flop 6 are reset by a signal generated by the 1-pulse circuit 10 at the trailing edge of the input signal 〆1.

The count number of the first counter 7 can be set arbitrarily.
The contents of the counter and the second counter 8 are the NkND circuit 9.
When a match is found, both counters 7.8 are reset by signal E.

If both counters 7 and 8 cannot match, the counter is not reset by signal E, but the input of periodic signal 11 and reference signal 2 is prohibited at the timing shown in Fig. 3, and the synchronization error signal J is sent at the same time. It is.

In the explanation of this embodiment, it is detected that the signal 〆1 has a constant phase with respect to the reference signal 〆2 as shown in 〆11 in Fig. 2. ,
This detection method can be implemented by arbitrarily selecting one.

As described above, according to the present invention, it is possible to detect synchronization deviations of periodic signals and also detect the frequency of synchronization deviations.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing an embodiment of the method of the present invention;
2 and 3 are timing charts explaining the operation of FIG. 1. 〆1...Periodic signal, 〆2...Reference signal, 3゜18...D type flip-flop, 6
...JK type flip-flop, 7...
...First counter, 8...Second counter.

Claims (1)

[Claims] 1. Count the number of pulses of a manually generated periodic signal with a first counter, synchronize the periodic signal with an internal reference signal having the correct periodic pulse, and count the number of synchronized pulses with a second counter, The counts counted by the two counters are compared for each count value set in advance in the first counter, and if the two counts match, the two counters are reset, and if they do not match, a mismatch signal is sent. 1. A method for detecting a synchronization shift of a periodic signal, characterized in that the synchronization shift and the frequency of synchronization shift are detected by transmitting the synchronization signal and stopping the operation of both the counters.