JPS5837811A - Digital recorder and reproducer - Google Patents

Abstract

PURPOSE:To set both mixing and dubbing levels, by providing a reference signal generating circuit which can produce plural reference signals having the levels equivalent to a prescribed degree of attenuation. CONSTITUTION:A digital recorder/reproducer is provided with a digital attenuator DAT18 which is connected to the mixing side of a digital mixing circuit 17 and performs the prescribed level control along with a digital attenuator switch S2; and a reference signal producing circuit 20 which is connected to the input side of a recording system and can produce the reference signals F1 and F2 having the maximum level of an analog signal delivered from the reproducing system and a level attenuated equivalently to the attenuation degree of the DAT18 respectively along with a digital attenuator switch S1. Then an analog converting signal between the signals F1 and F2 can be delivered selectively in accordance with the ON and OFF of the switch S2 and when the switches S3 and S1 are turned on. Thus both mixing and dubbing levels can be set.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides digital signal processing such as PCM (PulsI).
The present invention relates to a digital recording and reproducing apparatus suitable for a system that records and reproduces audio signals converted into C@d@Medal Hataket1 and L) using a home VTR (Video Recorder).

Recently, in the field of audio equipment, a PCM sickle sound reproducing device using PCM technology has been developed.

Such a PCM sound playback device converts an audio analog signal into a -H digital signal during recording to generate a magnetic chi! This is realized based on the principle of recording digital signals on a magnetic chip and converting the digital signals reproduced from a magnetic chip into audio analog signals during playback.

Specifically, an audio analog signal is sampled at a predetermined period, and this sampled audio analog signal is quantized (by an analog-to-digital converter, for example) and then This digital signal is converted into an NTSC standard television signal after being subjected to an error correction code, an error detection code, and interleaving processing during recording. Superimposed video recorder (
The NT8C standard television signal played back from this video recorder (hereinafter referred to as VTR) is demodulated and the extracted digital signal is subject to dinterleap, false signal detection and false signal detection. The original audio analog signal is converted into a quantized digital signal by performing processing such as correction. This digital signal is
The original audio analog signal is restored by a digital-to-analog converter, which operates in the opposite manner to the analog-to-digital converter described above.

In addition, by converting audio analog signals into digital signals and recording them, we are able to overcome the technical limitations associated with conventional cassette and tote recorders, such as the physical maximum magnetization level of the magnetic tape used as the recording medium. Among the characteristics, it is possible to perform high-fidelity recording and playback by eliminating the adverse effects on acoustic characteristics caused by mechanical precision.

Therefore, in such a PCM@-Iir playback device, when performing a digital return sound, the digital signal that has been converted from the analog signal is added to each other, and the digital signal is added to the digital signal. can be executed.

However, such a digital binary circuit is
For example, when two's complement addition is performed, when additions of the same sign, such as positive and positive or negative and negative, are performed, an overflow may occur in which the calculation result is reversed. This kind of overflow can have a big negative impact on the playback sound! Therefore, it is necessary to set the mixing level to an appropriate level. Therefore, there has been a strong desire to develop a nine-PCM recording and reproducing device that allows accurate and easy mixing level settings.

This invention was made in view of the above points, and in particular has a digital attenuator and a maximum level of the analog signal output from the reproduction system, as well as a level that is attenuated equal to the attenuation amount of the digital attenuator. 1st
Furthermore, it is an object of the present invention to provide a digital recording/reproducing apparatus that is capable of setting a mixing level and a dubbing level by providing a reference signal generation circuit that can provide a second reference signal.

An embodiment of the present invention will be described in detail with reference to the sections below.

That is, as shown in FIG. 1, the recording input terminal INL is supplied with the audio analog signals of the left and right outer channels.
+INl is correspondingly connected to the respective input terminal of the amplifier 11.11. Each output terminal of these amplifiers @11.11 is connected to a pair of input terminals of a mixing circuit 15 having a sample hold circuit or the like, for example, through a low-pass filter fi13.14 with a cutoff frequency of 20 kHz. Connected to child.

The output terminal of the O mixing circuit 15 is connected to the input terminal of the digital 2-mixing circuit 17 on the side to be mixed via an analog-fh Zotal conversion circuit (hereinafter referred to as ADC) 16. In addition, the input terminal on the mixing side of this digital mixing circuit 12 has f″&p//I-7, tenet 1111
The output terminal of J+ is connected.

The output J terminal of the ζoryp power dP render circuit IF,
It is connected to one of the human power end/fal of Mayu 10wJ Kaidanro IP. Another input terminal b1 of this first switching circuit 19
is connected to the output terminal Km of the reference signal generating circuit 2o.

The output terminal of the ζOO12 switching circuit 19 is connected to the input terminal of the second switching circuit 22 via the recording processing lI circuit 21. The other output terminal S is connectable to the video input terminal of an external VTR (not shown) via the terminal Xvl.

The video output terminal of the VTRJ J is connected to one input terminal staggered 1 of the third switching circuit 140. 3rd of jin
The other input terminal of the 0 switching circuit 24 can be connected to the video output terminal of an external VTR via the terminal XV, and the output terminal is connected to the playback processing circuit l! #tKj when connected to the digital attenuator 1#O input terminal via 25
114- switching 1gl circuit 1#0-δ human power terminal -4Km
Let's unify.
t) The human power converter 4 is connected to the upper IL1 first Miaizono ltv output horn, and the output terminal is connected to the f1'' analog R conversion circuit (hereinafter referred to as DAC) 2°ro input terminal. It is connected to the level display value 110 terminal.

The output terminal of this ODACJ F is a separation circuit xit.

A pair of output terminals are each connected via an amplifier 30° Sl to a respective input terminal of a Lois filter 32, 33 with a power and turn-off frequency of 20 kHz. The output terminals of these low-pass filters sz, ss are correspondingly connected to the output terminals 0UTL, QU〒mK.

By the way, the first switching circuit 19 and the reference signal generation circuit 20 are configured so that they are not driven via means not shown in response to the output signal of the first switch drive circuit 34 whose input terminal is grounded via the switch S1. It has become.

The digital attenuator 18 is driven by means not shown in response to the output signal of the second switch drive circuit S5 whose input terminal is grounded via the switch 81, and receives the value indicated by the digital signal supplied to the input terminal. It is designed to output a digital signal having a round value. At the same time, the reference signal generation circuit 20 generates the first and second switch drive circuits according to the output signal of the second switch drive circuit J5.
The standard signal is switched and output. Further, the fourth switching circuit 26 has an input terminal as a switch S,
The switch is driven in accordance with the output of the third switch drive circuit S6 which is grounded via the switch drive circuit S6.

In addition, the above 1. Second. Third switch drive circuit 14.
85.36 is composed of a chattering prevention circuit, a T-type flip-flop circuit, etc., and each non-locking switch 81e B@e 8m alternately changes the level of each output terminal with each operation. high level(
It is designed to switch between a high level (hereinafter referred to as an H level) and a low level (hereinafter referred to as an L level).

In addition, the first switching circuit 19 is connected to the first switching circuit 19 as described above.
This first switch drive circuit 54 drives the first switch drive circuit 54.
The output terminal of the switch drive circuit 34 selects the signal supplied to the input terminal &breath when it is at L level, and selects the signal supplied to the input terminal b1 side when it is at H level.

The second and third switching circuits 22 and 24 are driven by means not shown, respectively, and can independently select the output terminal ASLL and the input terminal 3 side or the output terminal BL side and the input terminal 1SS@. It looks like this.

When the output terminal of the second switch drive circuit 15 is at H level, the digital attenuator 1# is driven and outputs a digital signal in which the value indicated by the digital signal supplied to its input terminal is set to A, for example. When the ATTO output terminal of the second switch and drive circuit is at the L level, the digital signal supplied to the input terminal is output as is.

The reference signal generating circuit 20 generates the first control input terminal C1, which will be described later, by setting the first control input terminal C1 to H level. Second
If the second control input terminal C3 is at L level, the first reference signal is output, and if the second control input terminal is at H level, the second reference signal is output. It is designed to generate a reference signal.

The first reference signal is a signal that can increase the maximum level of the analog signal output from each output terminal 0υTL0UTl to 4, and the second reference signal is, for example, a signal that can increase the maximum level of the analog signal output from each output terminal 0υTL0UTl.
, A is the maximum level of analog erasure outputted from 0UTi.
This is a signal that can be given every day.

In addition, each of the above amplifiers I J , 'l 2, low-pass 24
Luke signal-3, 14, mixing circuit 15, ADC' 1 g
, the recording processing circuit 2 constitutes the recording system of the PCM 7"ryce,?), the above-mentioned reproduction processing circuit 25, and the DAC 27.
, min 1Ili circuit 29, amplifier 3σ, 8! , low pass 2
4 LUQ JJ and JJ constitute the reproduction system of the PCMf Rossette. Both the recording system and the reproducing system are integrated to form the icMf rosé and f-.

That is, the above 1. Second. Third. Fourth switching circuit 19
．． In the normal mode in which 21, 24, and 215 select their respective input terminals (or output terminals) 'l e al I al+a4, both the left and right channels (in total two systems ) is connected to the amplifier 13.14 via the input terminal INXNm correspondingly.
When supplied to the input terminal of the audio analog signal, the audio analog signal is amplified by amplification 911.12) and is passed through a low-pass filter with a cut-off shoulder frequency of 20 kHz.
, in respectively to a pair of input terminals of the mixing circuit 1j.

Each signal supplied to this mixing circuit 11C is alternately supplied at a predetermined period! It is ringed (sampled) and multiplexed and supplied from the output terminal of mixing circuit 15 to the input terminal of ADC 1#. ADC1# converts the multiplexed nine audio analog No. 1 into an analog-to-digital converter (hereinafter referred to as conversion) into, for example, a 14-pit digital signal, and this digital signal (referred to as a sampling word). is serially transferred and continuously supplied to the input terminal of the recording processing circuit 210 via the digital mixing circuit 1r and the first switching circuit 111.

Then, the recording processing circuit 21 treats three consecutive sampling words (six for two systems) for each system of both left and right channels as one data group, and applies two types of error correction codes (such as Matron 14bi.

Interleave processing is performed on each sampling word and each error correction code, and an error detection code (code length: 16 bits, g) for detecting erroneous signals is added. Furthermore, the digital data consisting of these seven sampling words, error correction code, and error detection code is superimposed by the recording processing circuit 21 into one horizontal scanning period of, for example, an NTSC standard television signal (hereinafter referred to as (referred to as a video signal) is supplied to the video input terminal of the VTR 2J via the second switching circuit 22.

Note that the above interleaving process involves superimposing each sampling word and each error correction code constituting the data group in separate horizontal scanning periods, for example, by correspondingly passing through a plurality of delay lines having different delay times. It is designed to be distributed accordingly. Sampling words of six different data groups and error correction codes are superimposed on one horizontal scanning period of the video signal.

As a result, the sampling words successively output from the ADC 16 are converted into magnetic chi! These are recorded at nine positions apart on the top, and are designed to compensate for burst errors.

In contrast to the recording system for the above-mentioned audio analog signal, the video signal line and reproduction system reproduced from the vTR2J restore the original audio analog signal.

That is, the reproduced video signal is transferred to the third switching circuit 2.
4, the signal is demodulated by a reproduction processing circuit 25, and various synchronization signals are extracted together with the digital data described above. This digital data is subjected to processing such as dinterleap processing, which is the opposite of the interleave processing described above, detection of erroneous marks using an erroneous mark detection code, and correction of erroneous marks using an erroneous mark correction code, in the reproduction processing circuit 25. The y'h zotal signal is converted into a continuous sampling word and is supplied to the input terminal of the DACJ 7 via the fourth switching circuit 2C.

The DACj F performs digital-to-analog conversion (hereinafter referred to as D) of the serial digital signal output from the reproduction processing circuit 25.
/A conversion) and then supplied to the separation circuit 29 as a multiplexed analog signal.

The separation circuit 29 separates the multiplexed analog signal into two audio analog signals for both left and right channels in synchronization with the DACJ F, and outputs the signals from a pair of output terminals to an amplifier 30 correspondingly.
．． 31 and low/math filters sx and is, respectively, to output terminals 0UTL and OUT.

However, in this case, the digital attenuator 18 is reset by means not shown, and the output terminal is set to the L level so as not to output a signal to the digital mixing circuit 111/C.

By switching the switching circuits 11 and 24 of M7'j, $12, and jlI3 to the output terminal b3 side and the input terminal S, respectively, video signals can also be recorded and played back to an external VTR (not shown) connected externally. I can do it.

next,? Explain about medium sing recording. For reproduction, a digital signal derived from, for example, an externally connected VTR (not shown) (hereinafter referred to as an external VTR) via a reproduction processing circuit 25 and a digital attenuator 18 is input to an input terminal INL.

The audio analog signal supplied from IN is converted into a digital digital signal by the converting circuit JFK.
y) are mixed and recorded on the VTRJ I via the wiring processing circuit 21. In this case, 1. Second. Third. Fourth
The switching circuits 1G and 21゜14.16 each have an input terminal (or output terminal) island 1pal +k)l
eb4 is selected. therefore,
The output signal of the digital mixing circuit 11 is the DACJ7
, the separation circuit 29, the amplifiers 30 and 31, and the low-pass filters sz and is.

It is designed to be output from OUT. The digital attenuator 18 is configured to supply the output of the reproduction processing circuit 25 as it is to the mixing side input terminal of the digital mixer circuit 1r.

In addition, on the contrary, it is also possible to mix a digital signal obtained by converting an audio analog signal with a signal reproduced from a VTRI & and record it on an external VTR. In this case, the second. The third switching circuits 22 and 24 each have an output terminal 1.
) I, the input terminal al side is selected.

ζNow, when the switch S is operated and the output terminal of the second switch drive circuit J6 is set to H level, the digital attenuator j8 changes the value indicated by the output signal of the reproduction processing circuit 25 to A.
This digital signal is supplied to the mixing side input terminal of the digital mixing circuit 17. Therefore, depending on the mixing level setting, the input terminals INL, INB
If the maximum level of the audio analog signal supplied to is suppressed to below the maximum level A of the analog signal output from the output terminals OUT, , 0UTl, then A
It is possible to avoid overflow in the digital adding circuit 11 that adds the output signal of the DC 16 and the output signal of the digital attenuator 18.

Furthermore, if the second and third switching circuits 22 and 24 are configured to select the output terminal, bs side, and input terminal aB side, respectively, the signals recorded on the VTRJ JK and the recording input terminals INx and vINH are supplied. A signal obtained by subconverting an audio analog signal into a digital signal can be placed in an external VTR via a medium simulator recording processing circuit 21.

Note that digital dubbing, in which digital signals recorded from one side to the other are copied between V'rRj J and an external VTR, is performed by operating the switch Sl to set the output terminal of the second switch drive circuit 36 to the L level and setting the digital attenuator 18 to the L level. The signal supplied to the input terminal is supplied as is to the mixing side input terminal of the digital mixing circuit 1r, and the audio analog signal supplied to the input terminal INL e INK is set to 0, or by means not shown. This can be realized by setting the output terminal of the ADC 115 to always maintain the L level. In this case, the second and third switching circuits 22
．． 24 selects the output terminal a3 side and the input terminal bs side respectively, digital dubbing from an external VTR to VTRJ J becomes possible, and output terminal b*
If the 14s input terminal 13 side is facing the VTRJ
Digital dubbing to an external VTR is now possible.

Next, setting of the mixing level will be explained.

In other words, the mixing level is set by setting the maximum level of the audio analog signal supplied to the input terminals INL*INK to the output terminals 0UTL and oty as described above.
The maximum level of the analog signal output to the 'rl (maximum level at which recording and playback is possible) is limited to A or less. Third switching circuits 22, 24 respectively connect the output and input terminals to 11.
11 side or btebsll, and operate the switch 8, which is the %ζ middle single switch, so that the 40th switching circuit 24 selects the input terminal a4 side. Then, when the switch 8i is operated, the first
When the output terminal of the switch driving circuit J4 becomes H level, the reference signal generating circuit 'xo is driven, and at the same time, the first switching circuit 19 is driven and the first reference signal is sent to the storage processing circuit 2.
1 will be supplied. Here, when the switch S3 serving as the reference signal generation circuit switch is operated, the output terminal of the second switch drive circuit J5 becomes H level, and the reference signal generation circuit 35 outputs the second reference signal. be.

The first reference signal is a signal that can give the maximum level that can be recorded and played back by the PCM recording and playback device, and the second reference signal is a signal that can give the maximum level of the first reference signal. This is a signal that can be used to increase the level of cancer.

As a result, the second reference signal is generated by the reference signal generation circuit 20.
from the VTR 23 (or external VTR) via the first switching circuit 19, the storage processing circuit 21, and the second switching circuit 22.
) is supplied as a video signal to the video input terminal of . At this time, VTRj! (Or external WR
) is in a state other than the playback device, the signal supplied to the video input terminal is output to its 11 video output terminal, and the video signal superimposed with the second reference signal is sent to the playback processing circuit. 25 into a digital signal, which is supplied to each input terminal of the DACj F and the level display device 2# via the fourth switching circuit 26.

The level display device 28 converts the second reference signal (digital signal) supplied to the input terminal into an analog signal and displays the analog signal on a built-in level meter.

Further, by next operating the switch 81, the first switching circuit 19 is switched to select the input terminal a1, and the level light display device 28 is connected to the input terminal IN,
, IN, will display the level of the audio analog signal supplied to , IN.

Therefore, the operations described above are repeated, and while comparing the level of the second reference signal a, the level of the input terminal! Ns-+
Mixing settings are made by adjusting the level of the audio analog signal supplied to the INIB.

The first reference signal is used when setting the dubbing level, and for example, the first reference signal is used when setting the dubbing level. Analog style chi like Lefuu! When dubbing to a recorder, output terminal 0
By converting it to an analog signal and outputting it to UTI and OU'ra, the recording input terminal becomes the output terminal 0UTL,
This makes it possible to easily set the optimum recording level for the analog tape recorder connected to OUTm that serves as the dubbing side.

Next, the specific configuration of the main parts of the apparatus shown in FIG. 1 will be explained using FIG. 2. Note that the same parts as in FIG. 1 are designated by the same reference numerals, and the explanation thereof will be omitted.

That is, the ADC device 40 constituting the ADCJ g
is composed of, for example, an IC, a 14-bit analog-to-digital converter, and its input terminal is connected to the output terminal of the mixing circuit 15 via the terminal IN. This AD
Each of the 14-bit parallel output terminals of the C device 40 is connected to the corresponding 14-bit input terminal of the parallel/serial conversion circuit 41C), and the digital signals obtained by the conversion are serially ( serial) is converted to a digital signal.

The output terminal of the 2-rel/serial conversion circuit 41 in the above example is
Full adder 4 configuring the digital adder circuit 11
It is connected to the mixing side input terminal of No.2. The output terminal of this full adder 42 is connected to the serial//4 parallel conversion circuit 43.
1 and the parallel/serial conversion circuit 43b,
The order in which serial digital signals are transferred
It is connected to an input terminal of an L8B7'MSB conversion circuit 430 that inverts the L8B7'MSB (original array). The output terminal of this LSB/MSB conversion circuit 41 constitutes the first switching circuit 19 and becomes the input terminal a1 of the AND/OR y-) 44.
It is connected to the. The output terminal of this ANDOR f-)4J is connected to the input terminal INd of the recording processing device 450 constituting the recording processing circuit 21, for example, and to the input terminal b4 of the fourth switching circuit 260. Teru. The output terminal Ov of this recording processing device 45 is the terminal O
UT, and is connected to the input terminal of the second switching circuit 220 (not shown).

A read-only memory (hereinafter referred to as ROM) 48 constituting the reference signal generation circuit 20 has two address input terminals A1, M3, . . . An connected to a counter 41c? Each output terminal Q*e Ql*=*Qn is connected correspondingly. and a data output terminal Dr.

Drl..., Dry are parallel input terminals 1hl*Igt of the first shift register 48 of parallel input serial output type
+...IJ* Correspondingly connected to Iax.

In this shift register 48, a serial input terminal 81J is grounded, and a serial output terminal Qll is connected to the first switching circuit 190.
It is connected to the second input terminal 2 of the AND-OR DART 44, which serves as the input terminal bl.

The output terminal of the third switching circuit i4 (not shown) constitutes the regeneration processing circuit 25 via the terminal ■Nv, for example, I
It is connected to an input terminal Iv of a reproduction processing device 49 consisting of C. The output terminal Od of this reproduction processing device 4# is connected to the input terminal a4 of the fourth switching circuit 26. This fourth switching circuit 26 has an output terminal connected to a serial/notarized converter circuit 500A output terminal constituting the DAC 2m, and is also connected to an input terminal of the level display device 200. This serial/parallel conversion circuit 50 has each parallel output terminal connected to each parallel input terminal of a DAC device 51 consisting of a digital-to-analog converter.

The serial/total serial conversion circuit 50 converts the serial JJ'h serial #(
Convert to i1/2 level digital signal and use DAC
K is provided to supply the device 51 and the display device 52. The analog signal output terminal of this DAC device 51 is connected to the input terminal of the separation circuit 29 (not shown) via a terminal OUT.

The dezotal tenator 18 is an 8-pin serial input parallel output type second tenator. third shift register sz,
ss and 8-bit parallel input serial output type 4th. Fifth
The shift registers 5-4 and 155 are configured as shown in FIG.

That is, the serial input terminal INF of the second shift register 52 serves as the input terminal of the digital input terminal 18.
s r INII is commonly used with the above-mentioned regeneration processing device 4fl.
It is connected to the connection midpoint between the O output terminal 011 and the Kugata terminal b4o of the fourth switching circuit. This second shift register, parallel output terminal Qes TQds t...Qhl
is the parallel input terminal Ig4 of the fourth shift register 54
r Ifa * + Ie4 * Ib4 is connected correspondingly, and Qbs is the serial input terminal IN□ of the third shift register 53.

It is also commonly connected to IN■.

This third shift register 53 has a parallel output terminal Qhl
I Qes *..., Qh, are the parallel input terminals of the fifth shift register 55 Ihi r III p "" +
If, Qhs is connected to the input terminal Ialm of the fifth shift register 55, and the output terminal Qas is connected to the input terminal Ia of the fourth shift register 54.
Connected to 4.

- The fifth shift register 55 has a serial input terminal sx
wm is grounded, and the serial output terminal QH is connected to the serial input terminal 81) 14 of the fourth shift register 54. The serial output terminal QHa of this shift register 54 serves as the output terminal of the input terminal 18, and is connected to the input terminal of the full adder 42 on the mixing side.

By the way, the recording processing device 4.5 and the reproduction processing device 49 have clock input terminals WBC and WBC, respectively.
BCp is a terminal C to which the output terminal of a clock signal generation circuit that generates a clock signal (not shown) is commonly connected. connected to t. This terminal CIN is connected to the second and third (D shift registers s2, sx) through an inverter 56.

The input terminals CK, , CK, and IC are connected together with the input terminal CK- of a sixth shift register 57 of serial input and parallel output type for generating various control signals.

This sixth shift register 57 has each output terminal Qa.
Qh is a NAND circuit 58 and an exclusive OR circuit 59
The output terminals Q... are connected to one input terminal of the AND circuit 60, and the output terminals 9 are connected to the AND circuit 6 via the impurity 61.
0 is connected to the other input terminal, and the output terminal Qf@ is in/? - is connected to two input terminals of a NAND circuit 63 via a terminal 62, and also to an address input terminal A of the ROM 4g. The output terminal of the AND circuit 58 is connected to the fourth. It is commonly connected to the shift/load terminals 8L and 418L of the fifth shift registers 54 and 55. The output terminal of the exclusive OR circuit 59 is connected to the shift/load terminal SLI of the first shift register 48. The output terminal of the AND circuit 60 is 3
It is connected to a first input terminal of the driver AND circuit 64. The output terminal of the NAND circuit 63 is connected to the counter 47.
is connected to the clock input terminal CK of.

By the way, the recording processing device 45 converts the black and white signals supplied to the clock input terminal into, for example, IA and 1/1.
Terminals Cdo and C divide the frequency into 6 and output it.
dl, and Cd· is a pair of series input terminals of the sixth shift register 57! N1* is commonly connected to IN·3, and Cdl is connected to the other input terminal of the NAND circuit 63 and the second input terminal of the three-person AND circuit 64.

In addition, the sixth shift lever, Zostar 57, has an output terminal Q.
a is commonly connected to the respective first input terminals of the pair of three-man-powered NOR circuits 1i5, 66, and the output terminal Qb is connected to the pair of three-man-powered NOR circuits 65.
66 second input terminals. The third input terminal of one of the three-manpower NOR circuits 65 is connected to the output terminal of a 20th holding circuit σI, which will be described later. The output terminal of this second holding circuit 67 is also connected to the inverter 6
9 to the third input terminal of the other three-man power NOR circuit 11 &.

The output terminals of the pair of three-person circuits 65 and 66 are respectively connected to one input terminal of the pair of NOR circuits 69 and 71, respectively. The other input terminals of these NOR circuits ro and rt are connected to the output terminal of the input node f-56. The output terminal of the NOR circuit 70 is commonly connected to the input terminal "K4 1 CKB" of the upper fit[4, fifth shift register 54, 56. The output terminal of the other NOR circuit 11 is , above J
It is connected to the clock input terminal CKI of the No. 11 shift register 45.

On the other hand, the output terminal of the first holding circuit 12, which will be described later, is connected to the third input terminal 3 of the AND/OR circuit 44 and the other input terminal of the OR circuit 14 via an inverter 73, and is also directly It is connected to the fourth input terminal 4 of the AND-OR-DIRT 44 and the reset terminal CL1 of the inverting input of the first shift register 71480.

Further, the third input terminal of the three-person AND circuit 64 is unified to the data output terminal Drγ of the ROM 4 g,
An output terminal is connected to the other input terminal of the OR circuit 14. The output terminal of the OR circuit 74 is connected to the reset terminal CL of the upper counter 4r.

Also, the above 1. The second holding circuit 12, 611, the first. The second switch drive circuits 34 and 35 are composed of, for example, a chattering prevention circuit and a TW flip-frog, each of which has input terminals connected to resistors R1 and R.

is connected to the power supply V□ via the switch 81p.
Sm is grounded, and the output terminals are respectively connected via resistors R8pR4 to the anodes of generation diodes DLI+DLI whose cathodes are grounded.

Furthermore, the above 1. 4th. fifth shift register 4g,
64.56 inhibition, terminal INH1゜INH,,I
NH, and input terminal 1h of the fourth shift register 54
4 are each grounded.

No. 2 above. The reset terminal CL**CL@ of the inverting input of the third shift register 52, 53 is connected to a control circuit (not shown) via the terminal C11, and is set to H level during the above-mentioned excitation recording and dubbing playback, for example. K is set so that it is set to L level in other cases. Reset terminals CL4 and CL of the inverting inputs of the fourth and fifth shift registers 54 and 55, and reset terminals CL of the inverting inputs of the sixth shift register 57.
- are CL4. CL and common terminal CI.

The intervening stone 1 is connected to a control circuit (not shown) via a terminal CI, and after the power switch is turned on and the various power supply voltages are stabilized, the level is changed from the L level to the H level.

By the way, No. 1. 4th. Fifth shift register 4B, 6
4 and 65 have the same configuration and the same function), and each shift/load terminal 8L1 * 8L4
, 8L@ is at L level, each parallel input terminal CK1CK4 p CKB i) 1 rises from L level to H level, respective parallel input terminal "1 * I
b1 + “” r Ihl and In2.

'b4 s "" * Ih4 and Ia@e Ib
The load mode is such that the level of ``g e ・'' + Ikg is loaded into the corresponding internal memory.In this case, the level is loaded from each input terminal IJ r Iha + Ihi of each of the shift registers 4B and 54.55. The contents are output to the respective serial output terminals.

On the other hand, each of the above shift/load terminals SL4 y SL4
If +BLs is Hv-4, each shift register 41
1.54.55 are respective input terminals Ia1.

IJ e・”e Ibl and In2*Ib4
+ =・*Ih4 and “I y Ib, ,・・
・The contents loaded into the respective storage units in the order corresponding to rIbH are sequentially transferred to each clock input terminal CKI, C
A shift mode is set in which output is output from each serial output terminal QHs v QH4*QHs every time the level of K, , CK- rises.

In addition, in the above case, each terminal CLI, CL,
.

It is assumed that CL is at H level.

Atsushi 2 above. Third. 6th shift register 52゜ss,s
v is the black input terminal CK, , CK, .

Each time CK- rises, for example, each pair of input terminals lN11*
lN■ and In31 e INs and IN@1
+INFs by shifting the logical sum of the signals supplied to each output terminal Ql! ＃Qbsl"'
*Qhs and Q&@rQb@e・”#
Qhs and Qa@e Q's r ''・+Qhs are output correspondingly.

The AND-OR dart 44 is composed of two AND circuits and one OR circuit, and the level of the output terminal is indicated by a variable y, and the first, the second, and the second... Third. If the levels of the fourth output terminals are respectively represented by &1 b 1 @ e ', the logical formula is shown as y=*a I@+b''. Therefore, the above AND/OR c-t 441a , if the third input terminal 3 is at H level and the fourth input terminal 4 is at L level, L8B/M8B
The signal at the output terminal of the conversion circuit 43 is selectively supplied to the input terminal of the recording processing device 450. The first AND-OR (r-) 44 selectively outputs the output signal of the first shift register 48 when the second and 40th input terminals 2 and 4 are at L level and H level, respectively. The signal is supplied to the input terminal INd of the recording processing device 450.

As shown in Figure #I3, the ROM 4g stores a digital value corresponding to the level when the reference signal is a sine wave, for example, at a predetermined interval in the axial direction, that is, data 2J. If the sampling frequency is set to, for example, 44,056 kHz, the sine wave is sampled every 22.6 voices S.

That is, the data corresponding to each level of the sampled sine wave at each time t., tl, . . . tk-1
1 is stored in the ROM d & as described later, and among them, the positive and negative peaks of the above-mentioned sine WtO (the maximum width of t9) - VB and V1m are the recordings of the PCM brass sound reproducing device. The maximum and minimum values (01,111,111,111,111 and 10,000,000,000,000) that can be expressed in binary numbers (14 bits) correspond to the maximum playable level. ), provided that m- is /4.

The r-data is stored in the storage area designated by the input from the address input terminals M, A1, . . . M of the ROM 41j.

That is, as shown in FIG. 4, each data v-1vl,
..., Vk is the upper 8 pins, G and lower 6 pins, respectively.
The data is divided into four parts and stored in the ROM 4g. Here, to explain data Vt at time 12 as a representative, the ROM 4 # stores the upper 8 bits of data Vt at address 2, data Vt@, Vt1 .
..., Vtv tld ROM 41 Of”
fi flti power terminal Dr., Dry,..., Dr
The lower 6 bits are stored at address 2t+1,
Data of Vjs; Vje, Vta, Vtb
, Vje, vLd are stored in correspondence with the data output terminals Dr6, Drl, . . . , Drg of the ROM dlj.

tl, the above ROM d6 stores each data V at an even address.
or Vte...r Vk-t (The upper s bits of D are stored, and each data V., vl is stored at an odd address.
,...

The lower 6 bits of Vk-1 are stored. In addition, in the above ROM 4g, the lower two bits and bits of the storage area at each odd number address are not used, so these are given the binary value O.
The lower 6 bits of the final data (Vk-t) are stored, and the lowest bits are stored in the storage area at addresses 2 and 11, and the lower six bits of the final data (Vk-t) are stored. The value 1 is specially stored.

Next, the second section described above and shown in FIG. 3rd °f, 4.
The operation of the digital attenuator 18 constituted by the shift registers p52.5B and 54°55 of @5 will be explained with reference to FIG.

In addition, in this case, the second. third shift register sz,s
The reset terminal of the 4th. Reset terminals CL4, CL, of the fifth shift register 54°55
and a reset terminal CL of the sixth shift register 51,
are set to H level by a control circuit (not shown) through terminals C1 and CI, respectively.At the same time, the output terminal of the third switch drive circuit j6 shown in FIG. 1 is set to L level. level, and the fourth switching circuit z6 selects the input terminal am@. In FIG. , and Cd
(C) is the clock signal supplied to the terminal CIN, (d) is the output signal of the inverter 56, Cox) Each output terminal Qa, +Qbst... of the sixth shift register 51
+Qh@respective output signals, (f) is the output signal of the NAND circuit 58, -) is the output signal of the NOR circuit 10 when the output terminal of the second holding circuit 61 is at H level. a! (h) is the output signal of the serial output terminal QH4 of the fourth shift register 54 when the output terminal of the second holding circuit C8 is at H level, and (1) is the output signal of the second holding circuit 67. is the output signal of the three-man NOR circuit 65 when the output terminal of is at the L level, and (j) and (a) are the output signals of the OR circuit 10 when the output terminal of the second holding circuit 68 is also at the L level. (1) is the output signal of the output terminal Ov of the reproduction processing device 49. 9, 9, and 1 indicate, for example, the period during which digital signals corresponding to the left channel and the right channel are output from the output terminal of the AND-OR-DART 44.

That is, the sixth shift register 57 has a black input terminal CK- supplied with an inverted black signal via an input terminal CK-, and a pair of input terminals IN11 and
The IA frequency-divided signal is supplied to a1Nm5 from the frequency-divided clock terminal Cd of the recording processing device 450. Accordingly, the 60th shift register 57 performs a shift operation every time the clock input terminal CK falls, and each parallel output terminal Qas e Qb.
's is the frequency-divided clock terminal Ca of the recording processing device 45.
The phase of the output signal is π/16, 3π71 each +
5t'/16 srt/16, '9wA6,
l1g/16, 13g/16, x5g/16(r
ad) A delayed signal is output. (Refer to No. 5aQ(・1), (・1)+..., (・S)) At this point, the output terminal Od of the playback processing device 49 outputs the VTR signal every time the black signal rises. 231) Or external V
The serial digital signal power of 14N, which is the sampling word recorded in the TR, is monitored in order from upper bit to bit (tb) as shown in Figure 5 (1).
The signals are output in the order of SSS, and the L level (logic 0) is output for two cycles of the subsequent black and red signals. This 14
The bit digital signal is generated every time the output terminal (56C) rises (that is, every time the clock signal falls).
Second. The second . Third shift register S I t
53 parallel output terminals QCs + Qds r...Qh
s = Q turtle @ +Qb s t... Output from Qhs, the most significant bit B corresponds to the output terminal Qhs, and the least significant bit Bts corresponds to the output terminal Qes. There is.

The lowest pitch of the above digital signal) Bll f) E 2nd
When the sixth shift register 51 is output from the output terminal Ql of the shift register 520, the output terminal Ql,
Both Q- become L level (Fig. 5 (・1), (*a'
)) The shift/load terminals 5L4 + of the 4th and 5th shift registers 54 and 55 are connected via the NAND circuit 58
Both 8Ls are set to L level and each shift register 54#5g
Set to load mode.

By the way, in this case, the output terminal of the three-man powered NOR circuit 65 is set to the υL level by the second holding circuit 68, so the fourth
．． In the fifth shift register 54, each black and white input terminal CK4 e CKS is black, and the red signal is in/eta 5I.
t is supplied via I and NOR circuit 10. (See FIG. 5(x)) Therefore, when the clock signal rises next, the sixth shift register 57-711 shifts, and the fourth shift registers 54 and 55 of tAs shift each shift.)/E! code terminal gL
4 r SLI power! The signal is set to H level via the NAND circuit 58, and the shift mode is set again.

At the rising edge of the clock signal 9, the fourth and fifth shift registers 64 perform a shift operation, and 14 bits,
The digital signal of the bottom ring Bts is output.
Below, black, the eccentric force i rises 4iK. fourth and fifth shift registers 64;

55 performs a shift operation, and the 14-bit digital signal from the serial output terminal QHa of the fourth shift register 54 is 181! +B11p”., Bl, B・.

B, are output in this order. (Refer to Figure 5) On the other hand, the parallel/serial conversion circuit 41 opens its output terminal at the falling edge of the frequency-divided clock terminal Cd and maintains an L level (logic O) for two periods of the signal. After outputting, the 14-pit digital signal converted by ADC 40 is clocked.

Since the signal is output from the least significant bit to the mixed input terminal of the full adder 42 in synchronization with the rising edge of the signal,
The signal output from the fourth shift register 54 is shifted downward by one pin with respect to the signal output from the parallel/serial conversion circuit 41.

Accordingly, if it is assumed that the output of the ADC 40 is a digital value of O, the signal output from the LSB/MSB conversion circuit 43 will be A compared with the value of the digital signal output from the reproduction processing device 49. It is what is done.

By successively performing a series of actions like this,
The value indicated by the output signal output from the reproduction processing device 49 is A.
A 7'' digital signal having a value of 0.001 can be supplied to the mixing input terminal of the full adder 42 constituting the digital mixing circuit 12.

Next, switch and Te8, which will be the digital attenuator switch.
．． When the output terminal of the second holding circuit 68 is set to L level by operating , the output terminal of the three-person circuit 65 is set to the L level and the output terminal Qb of the sixth shift register 51 is set to L level and H level, respectively. When it reaches level, it becomes H level.

As a result, the fourth. Fifth shift register 54° iso clock input terminal CK4. The clock signal pulse supplied to CK is the output terminal Qa of the sixth shift register 5r.
- and Qb- are pulled out only during the period when they are at L level and H level, respectively.

Therefore, the digital signal supplied from the output terminal Od of the reproduction processing device 49 is divided by the frequency divided by 450,
Terminal Cd falls and becomes black.

After two cycles of the signal have elapsed, the fourth shift register 5
4 output terminal QHa to Bll + B11+ '・
. . , B. are output in this order in synchronization with the black and white signals.

Figure 5) Refer to Figure 5. The output signal of the reproduction processing device 49 is supplied to the mixing input terminal of the full adder circuit 42 that constitutes the digital mixing circuit 17 without the value indicated by the signal being changed to W. It is.

Next, the reference signal generation circuit 2 formed by crushing the ROM 4B
The operation of 0 will be explained with reference to FIG.

In this case, the reset terminal CL of the sixth shift register 51 is set to H level by a control circuit (not shown) via the reset terminal CI.

The output terminal of the first holding circuit 72 is set to H level by operating the switch S1. Also, in Figure 6,
(-) and (b) are the output signals of the frequency-divided clock terminals Cd and Cd of the recording processing device 450, and (d) is the output signal of the inverter 56, 6J, (・*), (・S).
,..., (・Hata) are the respective output signals of the parallel output terminals Qa, rQb-*..., Qh of the sixth shift register 57, and (f) is the output signal of the exclusive OR circuit 59. It is the output signal, (ω is the output signal of InEatalo 20 and L (
h) is the output signal of the NAND circuit 63, (1) is the RO
L(j) is the output signal of the OR circuit 74 when the output terminal Dry of M4g is at H level and 9, and L(j) is the output signal of the OR circuit 21 when the output terminal of the second holding circuit 68 is at L level and 9.
Similarly, To4) and Oc) are the output signals of the serial output terminal QH1 of the first shift register 48 when the output terminal of the second holding circuit 68 is at L level, and (1) is the output signal of the three-person circuit 66 when the output terminal of the second holding circuit 67 is at H level, and (C) and (n) are the output signals of the same second holding circuit 68.
The output signal of the NOR circuit 11 when the output terminal of is at H level and the serial output terminal Q of the first shift register 4g
This is the output signal of Hs. t, periods Tml and Tms
For example, the first or second channel for the left channel and the right channel are connected to the output terminal of the AND-OR gate 44, respectively.
This is the period in which the reference signal is output, and the period Tm@#
Tml l Tml e Tml and Tm4 each have ROM46 of 21.2t+1.21.2t+1.21
+2 (where t is an arbitrary integer) This is the period during which the data at the address is output.

That is, as described above, since the output terminal of the second holding circuit 61 is set to the H level, the input terminals S and 4 of the AND-OR gate 44 are set to the H level, and the serial output terminal QHI of the first shift register 48 is set to the H level. The output signal is sent to the input terminal INd of the recording processing device 45 via the AND-OR gate 44
It is now being supplied to

At the same time, since one input terminal of the OR circuit 57 is set to the fiL level by the inverter 7S and the other 6 terminals are set to the fiL level by the three-person AND circuit 5#, the reset terminal CLt-L of the counter 41 The counter 41 is reset as a level, and the state is released.

The column output terminals Qas e Qh@ are both set to H level, and the shift/load terminal 8Ll of the first shift register 48 is set to L level via the exclusive OR circuit 59, and the
When the signal rises, for example, the ROM 4 II O parallel output terminal Drg t Drl + "" + or.

Data To of address θ specified by storm counter 47
, Vol, . . . IVoy are output, and these data are loaded into the first shift register 4117/C. (See FIG. 6(f)) As a result, the serial output terminal QH1 of the 10th shift register 48 has the ROM 4
Data V・γ output from parallel output terminal Dr・
K is set so that it is output.

At the next falling edge of the clock signal, the sixth shift register 51
Since a shift operation is performed, the first shift register 411 (Q shift/load terminal 8L1) is tossed at the H level via the exclusive OR circuit II. 48 is ROM
46 parallel output terminals Dr 1 , Dr Hl...,
Data loaded from Dry V@1, Vow
,...+V@? is now output from the serial output terminal QHI as a serial digital signal.

By the way, the output terminal Qf of the sixth shift register 51
When the data Vog is output to the serial output terminal QHs of the first output shift register 41, the pulse rises from the L level to the H level when the pulse falls. ? :,
Since the address input terminal M of the ROM4σ is set to H level via the inverter 62, the data Vo@HVow, . . . , Vod at address 1 is outputted to the data output terminal Dr@.

Output to Drl,..., Drg. In addition, as mentioned above, the parallel output terminal Dr? of the ROM 46
In this case, data VO, is output to the serial output terminal QH1 of the first shift register 48, and the clock signal is output in good condition.
When the f pulse falls, the sixth shift register 51 executes a shift operation, brings both its parallel output terminals Qas s Qb- to the L level, and passes the exclusive OR circuit 59 to the first
The shift/load terminal SL of the shift register 4a is set to L level again. When the black and red signals rise here, the first shift register 48 is loaded with the outputs of the respective parallel output terminals Dr., Drl, . . . , Dry of the ROM 46, and the serial Every time the black signal rises from the output terminal QHt, the data (V), Vow
r...r V@d and 2-bit L level signals are output.

Further, when the clock signal falls while the tenth shift register 48 is outputting the data V.1s, the sixth shift register 57 outputs the output terminal Qf from the innoeater #.
The address input terminal M of the ROM 46 is set to L level through the input terminal 2. As a result, the ROM 4 If stores the r-data vO. stored at address 0 in each parallel output terminal Dr@a Drl..., Dry.

■@East, .-, V@Ma are output again. Next, when the serial output terminal QMt of the first shift register 48 is outputting the data v01 loaded from the output terminal Dry of the ROM 4g, when the black signal falls, the sixth shift register 5r, both parallel output terminals Qa. and Qh. are set to H level. As a result, the first shift register 48 enters the load mode.
At the next rising edge of the clock signal, the data Vo@, Vol, . . . , Toy at address O in the ROM 46 is loaded internally. The following nine data V are loaded as described above.
凰.

Vow, .

Further, as in the above case, in the state where the data V.S is being outputted, the sixth shift register 51 sets the parallel output terminal Qf- to the L level and outputs it to the inverter 62 (j).
The address input terminal of the ROM 46, child A, is set to H level.This causes each parallel output terminal Dr of the 9 ROM 46 to
. . , Drl 1 . . . , Dry are outputted with a signal corresponding to the data output terminal I Vo write e .

These data Vos e Vow +..., V・
The L level signals of d and the lower two bits and g are serial digital signals, and are outputted again from the serial output terminal QHI of the first shift register 48 every time the clear signal rises.

Similarly to the above case, when the clock pulse falls while the lowest bit bit VoB is being output from the serial output terminal QHs of the first shift register 41, the ROM
Address input terminal A.4g is brought to L level again. At this time, one input terminal of the NAND circuit 63 is set to H level by the inverter melo 2, and the other input terminal is set to H level by the black signal supplied from the divided clock terminal Cd of the recording processing device 45. Since it has been
From clock input terminal CKtH level of counter 4r
lower the level.

As a result, the counter 41 counts up by +1, so that each parallel output terminal Dr. of the ROM 4g.

Dry, . . . The data stored at address 2 is outputted to Dry, and is outputted from the output terminal QHs of the first shift register 48 as in the previous case, and then transferred to the ROM 4.
#31jli! data is stored in the first shift register 4g
is output from the serial output terminal iHi.

After the data stored at addresses 2 and 3 are output again from the serial output terminal QHs of the first shift register 48, the data at addresses 4 and 5 are read out alternately twice and This is output from the serial output terminal QHs of the shift register 48 of No. 4.

Thereafter, similar operations are repeated; generally speaking, the th data Vt, that is, Vt·.

vAi # = p VLd is twice ROM46 (D2
Oh! The next data VZ+1 is read from address 2(t+1) and output as a serial digital signal from the serial output terminal QHI of the first shift register 48.
+1) address and 2(t+1)+1 address and output in the same way.

By the way, when the final address (in most cases, addresses 2 and 11) at which data is stored in the ROM 4g is read out at the second address, the rotor output terminal Dry of the ROM 46 is set to H level. , the third input terminal of the three-man power AND circuit 64 is set to H level.

In this state, when the sixth shift register 57 sets the parallel output terminals Qb and QC6 to H and L levels, respectively, the output terminal of the AND circuit 60 becomes H level. Therefore, in the three-man power AND circuit 64, the first input terminal is set to H level by the AND circuit #O, and the second input terminal is the 1/16 clock supplied from the divided clock Cdl of the distribution processing device 41. Since the pH level is set by the frequency divided signal, the output terminal is set to the H level, and the reset terminal CLf of the counter 41 is set to the H level via the OR circuit 14, and the counter 41 is reset.

As a result, the serial output terminal Q of the first shift register 48
From HI to the last digit of the final address of ROM 46 (v(
When the clock signal falls with k-1) d) being output, the ROM 46 outputs the address input terminal A@sm1.
, . . . , An are all set to L level, and the data at address 0 is output to the data output terminal Dr@+Drl r =・e Dry. In this way.

The signal R corresponding to one single signal stored in the ROM 4 II is repeatedly output from the serial output terminal QHs of the first shift register 48.

By the way, since the output terminal of the first holding circuit 72 is at H level, the digital signal output from the serial output terminal QH1 of the first shift register 48 is
It is supplied to the recording processing device 450 input terminal INd via the AND-OR-DART 44.

In this way, the digital signal serving as the first reference signal is superimposed on the NT8C standard television signal and
It is now possible to record on a DVD player or an external VTR.

Incidentally, the VTRl J and the external VTR are designed to output the input signal from the video input terminal as it is from the video output terminal in a state other than the playback state. Therefore, the video signal on which the first reference signal is superimposed is subjected to various processing by the reproduction processing device 49, and the first reference signal, which is the same as the digital signal output from the AND-OR-DIRT 44, is reproduced. It is output from the output terminal Od of the processing device @49.

The first reference signal output from the reproduction processing device 49 is converted into a p-multiplexed analog signal by the serial/not parallel conversion circuit 50 and the DAC device 51 that constitute the DACJ 9 via the fourth switching circuit 26. terminal (OUT
) to the separation circuit 29. Thereafter, the multiplexed analog signal is separated by the separation circuit 29 as described above, and is then separated by the amplifier 30.31 and the low-pass filter 37.
33 to each output terminal 0UTL, O
This is the maximum level analog signal that is output from the UTm.

As a result, when dubbing from each output terminal 0UTL and OUTm to an analog tape recorder such as a cassette tape recorder, it is possible to extremely easily set the optimum vowel level of the tape recorder on the dubbing side.

Furthermore, the first reference signal output from the reproduction processing device is
The signal is also supplied to the level display device 28 via the fourth switching circuit xi, and the level is displayed, so that the display of the level display device 28 can also be calibrated.

Next, switch S which becomes the digital attenuator switch
1 to set the output terminal of the second holding circuit 68 to H level, the output terminal of the three-person circuit 66 becomes L level and the output terminal Qb of the sixth shift register 51 becomes L level and H level, respectively. When it reaches level, it becomes H level.

As a result, the fourth. The pulse of the clock signal supplied to the clock input terminals CK41 and CKH of the fifth shift register 54 and 55 is the output terminal Q of the sixth shift register 51.
A. and Qb@ are pulled out only during the period when they are at L level and H level, respectively.

With this, the digital signal output from the serial output terminal QH1 of the first shift register 48 is transmitted to the recording processing device 4.
For example, 2 of ROM 4g is stored at address 2 for two cycles after the frequency division clock of 5 falls, and the 9th highest bit is stored.
Data VZ1 r Vl-@ *..., Vt,
will be output.

(See Figure 6 (n)) Comparing Figure 6 body) and the same figure axis), Figure 6 6) is quite similar to the same figure axis), and the ri signal is in one cycle. At this time, the first shift register 48
The signal outputted from the serial output terminal QH1 is compared with the first reference signal, and the value indicated by the digital signal is the same, and becomes the second reference signal.

As a result, the second reference signal is sent to the DAC 27 via the recording processing circuit 45, VTRx J (or external VTR), playback processing device 49, and fourth switching circuit, as in the case of the first reference signal. It is supplied to each input terminal of the constituting /4 parallel/serial conversion circuit 50 and the level display device 28, and enables setting of the imxing level as described above.

In addition, in FIG. 2, the LBH7MSB conversion circuit 43c,
2nd, 3rd. 4th. Fifth shift register sx,is
, si, and ss, and can be constructed using a series input parallel output type shift register and a parallel input serial output type shift register like the tenator 18. The fourth switching circuit 2# can be constructed using an AND/OR (r-) and an in/f-inter.

Further, although a sine wave is used as the first and second reference signals, for example, a square wave or a triangular wave may be used (, R
It is designed so that the waveform of the reference signal can be easily changed by replacing OM1#. It should be noted that various other modifications and applications are possible without departing from the gist of this document. Not until now.

As described above, according to the present invention, the maximum level of the anamada signal output from the digital attenuator and the reproduction system as well as the level obtained by attenuating this maximum level equal to the attenuation amount of the digital attenuator are provided.
Based on the basis of g2, it is possible to provide a digital recording/reproducing device that allows setting of the dubbing level at the same time as setting the mixer level.

[Brief explanation of drawings]

91 is a configuration diagram of a digital recording/reproducing device according to the present invention, FIG. 2 is a circuit connection diagram showing the configuration of the main parts of the device of FIG. 1, and FIGS. 3 and 4 are the read-only memory of FIG. 2. The figures used to explain the data stored in the circuit, FIGS. 5 and 6, are tie-building charts used to explain the operation of the circuit shown in FIG. 11.12-Amplifier, 11.14...Low/4 filter, 15-Mixing circuit, 16...Analog-digital conversion circuit (ADC), IF...Digital mixer circuit, 11-... Digital attenuator, 19-first switching circuit, 20-reference signal generation circuit, jl...
Recording processing circuit, 22... second switching circuit, 1l-ef
Otegu vx-da (VTR), 24...Third switching circuit, zi-...Reproduction processing circuit, 26...Fourth switching circuit, 27...Digital-analog conversion circuit (DAC
), 28... Level display circuit, 29... Separation circuit,
730.31...Amplifier, sz, ss...Lonos filter, 34.35...Swi9fllA operating circuit, 8
1F8m...Switch, 40...ADC equipment f, 4J
...Parallel/serial conversion circuit, 41...Full addition circuit, 43a...Serial/not parallel conversion circuit, 4
3b--i4 parallel/serial conversion circuit, 4 J-L
S15/MSB conversion circuit, 44.-7nY 1st P-)%
4#--recording processing device, 46--read-only memory (ROM), 47--counter, 48--first shift register, 49---playback processing device, 50...
Serial/・parallel conversion circuit, 51-・ADC device,
52--second shift register, 53--third shift register, 54-- fourth shift register, si-
...Fifth shift register, 56...IyΔ-ta, 5
7...Sixth shift register, 58...NAND circuit, 59...Exclusive OR circuit, go...AND circuit, 61.62...In/exchanger, 63... NAND circuit, 64...AND circuit, 65.66...3-manual NOR circuit, 67...IN-GUTTER, 68...Second holding circuit, 69...IN-NO-TERR, 70.77...NOR circuit, 72...First holding circuit, 73...Inverter, 74...Innotor.

Claims (1)

[Claims] A recording system that converts analog signals into digital signals and records them on magnetic tape; a reproduction system that converts the digital signals reproduced from this magnetic tape back to the original analog signals;
Digital mixing circuit and digital mixing switch t-t PCM! Rose V Suni Part 1 C) VTR
internally connected and a second VTR externally connectable, the output terminal is connected to the input terminal of the digital mixing circuit O1, and the first t9 receives the reproduction signal of one of the second VTROs. A digital attenuator, a tenator switch, and a digital attenuator switch that are attenuated by a predetermined level and output from the playback system are connected to the input side of the recording system and output from the playback system, and this level is set to the digital attenuator. a reference signal generation circuit and a reference signal generation circuit switch capable of providing first and second reference signals having a level attenuated equal to the attenuation amount of the digital mixing switch and the reference signal generation circuit switch, the digital mixing switch and the reference signal generation circuit switch being both turned on In this state, the second
By selectively outputting the analog converted signal of the first reference signal from the reproduction system, the mixer level can be set and! (A digital recording and reproducing device characterized by being able to set the recording level.