GB2284967A - Multiplexers and demultiplexers - Google Patents
Multiplexers and demultiplexers Download PDFInfo
- Publication number
- GB2284967A GB2284967A GB9425195A GB9425195A GB2284967A GB 2284967 A GB2284967 A GB 2284967A GB 9425195 A GB9425195 A GB 9425195A GB 9425195 A GB9425195 A GB 9425195A GB 2284967 A GB2284967 A GB 2284967A
- Authority
- GB
- United Kingdom
- Prior art keywords
- frequency
- input
- output
- multiplexer
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/04—Distributors combined with modulators or demodulators
- H04J3/047—Distributors with transistors or integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
A multi-stage multiplexer takes a plurality of time multiplexed input signals and converts them into half as many time multiplexed output signals each having twice the bandwidth. Similarly, a demultiplexer takes a number of time multiplexed input signals and converts them into twice as many time multiplexed output signals each having half the bandwidth of the input signals. When a plurality of identical multiplexing or demultiplexing units are arranged in series, it is necessary to provide re-ordering means to change the order of signal samples output from or input to each of the multiplexer or demultiplexer units respectively. <IMAGE>
Description
MULTIPLEXERS AND DEMULTIPLEXERS
This invention relates to multiplexers and demultiplexers and particularly to multi-stage multiplexers and demultiplexers made up of a plurality of discrete multiplexing or demultiplexing elements.
A multi-stage frequency multiplexer is shown in Figure 1, this frequency multiplexes 2N input signals into a single output signal by employing N layers of discrete 2:1 multiplexer units 1. Each multiplexer unit 1 having as its two inputs the outputs of two of the multiplexer units 1 in the preceding layer. As a result a total of 2N-1 discrete 2:1 multiplexing units 1 are required.
Clearly if each input signal has a bandwidth B the final single output signal must have a bandwidth of 2N times B. As is well known, the sampling rate required to fully represent a signal is proportionally related to the bandwidth of the signal (Nyquists rule) and as a result it is necessary for the sampling rate of the output signal from each 2:1 frequency multiplexer unit 1 to be sampled at twice the frequency of each of the inputs and it is necessary for the output from the multiplexer as a whole to be sampled at 2N times the rate of each of the input signals.
This produces the problem that either the multiplexer units 1 in each stage of the multiplexer must have different sampling rates, which is commercially undesirable because of the very large number of different types of multiplexer units that would be required, or if identical multiplexer units are used throughout the multiplexer the multiplexer units 1 in the earlier stages of the multiplexer will be greatly underutilised because they will be sampling the signals at many times the required sampling rate. In the most extreme case the first stage multiplexers would be sampling the input signals at 2N times the necessary rate.
Referring to Figure 2 a multi-stage frequency demultiplexer is shown made up of a plurality of 1:2 frequency demultiplexer units 2. The 1:2 frequency demultiplexer units 2 are arranged in N layers to demultiplex a single input signal having a bandwidth of 2N times B into 2N output signals each having a bandwidth B. Clearly the same problems would be encountered in this demultiplexer as in the multiplexer of Figure 1 except that it is the later stage demultiplexer units which will be oversampling the signals rather than the earlier stage multiplexer units 1.
This invention was intended to provide a multi-stage frequency multiplexer or demultiplexer overcoming the problems described above. at least in part.
In a first aspect this invention provides a frequency multiplexer unit having an input and an output each comprising a series of samples representing input and output signals respectively and including multiplexing means arranged to convert a plurality of time multiplexed input signals having a set bandwidth into half as many time multiplexed output signals having twice the bandwidth and further including means to re-order the signal samples output by the multiplexing means into time order to provide the output of the frequency multiplexer unit.
In a first aspect this invention further provides a frequency multiplexer comprising a plurality of such frequency multiplexer units arranged in series with the output of each frequency multiplexer unit in the series providing the input to the next.
In a second aspect this invention provides a frequency demultiplexer unit having an input and an output each comprising a series of samples representing input and output signals respectively and including demultiplexing means arranged to convert a number of time multiplexed input signals having a set bandwidth into twice as many time multiplexed output signals having half the bandwidth and including means to re-order the input signal samples such that pairs of time sequential samples of each input signal in turn are supplied to the demultiplexing means.
In a second aspect this invention further provides a frequency demultiplexer comprising a plurality of such frequency demultiplexer units arranged in series with the output of each frequency demultiplexer unit in the series providing the input to the next.
Frequency multiplexers and demultiplexers employing the invention will now be described by way of example only with reference to the accompanying diagrammatic figures.
Figure 1 shows an example of a known multi-stage distributed frequency multiplexer;
Figure 2 shows an example of a known multi-stage distributed frequency demultiplexer;
Figure 3 shows a multi-stage distributed frequency multiplexer according to the invention;
Figure 4 shows a multi-stage distributed frequency demultiplexer according to the invention;
Figure 5 shows a frequency multiplexer unit according to the invention suitable for use
in the distributed frequency multiplexer of Figure 3; and
Figure 6 shows a frequency demultiplexer unit according to the invention suitable for usc in a distributed frequency demultiplexer as shewn in Figure 4, similar parts having the same reference numerals throughout
This invention is based upon the realisation that the overall sampling rate for each < tage in the multi-stage multiplexer or demultiplexer is the ame since the sum of the number of parallel signals and their individual bandwidths, or alternatively the sum of the number of parallel signals and their sampling rates, is always the same. This is the case in both the multiplexer and the demultiplexer.
As a result it is possible to construct a multi-stage multiplexer from a plurality of identical frequency multiplexer units each of which takes in M time multiplexed signals each of bandwidth b and produces as an output M/2 time multiplexed signals of bandwidth 2b. A multi-stage distributed frequency multiplexer 30 made up of a plurality of such multiplexer units 3 arranged in series is shown in Figure 3. The multi-stage frequency multiplexer 30 having N stages and having as an input a signal comprising 2N time multiplexed signals each of bandwidth
B and producing as an output a single signal of bandwidth 2N x B requires N multiplexer units 3.All of the frequency multiplexer units 3 in the frequency multiplexer 30 can be identical because they all have the same required sampling rate and as a result the high level of redundancy found in the prior art is avoided.
Similarly in Figure 4 a multi-stage distributed frequency demultiplexer 40 is shown formed by a plurality of identical frequency demultiplexer units 4 arranged in series. The demultiplexer units 4 are the reverse of the multiplexer units 3 and have as an input M time multiplexed signals each of bandwidth b and generate an output of 2M time multiplexed output signals each of bandwidth b/2. The multi-stage frequency demultiplexer 40 has N stages and a single input signal of bandwidth 2N x B produces as an output 2f time multiplexed output signals each of bandwidth B and requires N demultiplexer units 4.
It will be realised that the frequency multiplexer 30 and frequency demultiplexer 40 could equally be well referred to as time demultiplexers and time multiplexers respectively. For clarity the terms multiplexer and demultiplexer will be used to refer to frequency multiplexers and demultiplexers throughout this specification.
The multiplexer units 3 of Figure 3 are each supplied with an input consisting of a series of digital samples of fixed size representing a number of time multiplexed signals each having a set bandwidth. Where there are n time multiplexed signals this input can be represented as X11,X21, X3" ...in" X12, X22, ...Xn2 etc. Where X11 and X12 are the first and second samples of the first time multiplexed signal respectively, XA the first sample of the second time multiplexed signal and so on.
The multiplexer units 3 include frequency multiplexing elements which combine successive input signal samples representing different signals having a bandwidth to produce output signal samples representing a single signal and having double the bandwidth.
It has been realised that simple multiplexer units 3 as described above will not work when arranged in series to produce a multi-stage distributed frequency multiplexer 30 because the output samples produced will not be in time order and as a result the output signal will not be a conventional time multiplexed signal. As well as preventing operation of a multi-stage distributed frequency multiplexer this is generally a problem when it is desired to process the output of a multiplexer unit.
This problem occurs because when two input signal samples representing two signals each having a bandwidth are combined to form a single output signal having twice the bandwidth, by Nyquists rule the output signal requires twice the sampling rate of either input signal and as a result the output signal requires two signal samples to represent it. This is to be expected since all the information in the two input signals is carried by a single output signal so the same number of samples are needed to carry this information.
An illustrative example is for a frequency multiplexer unit 3 with four time multiplexed input signals. The input signal samples will be X11, X21, X31, X41, X12, X22, X32, X42, ... this will be converted to an output; Yell, Y12, Y2l, Y22, Y13, Y14 .....
where Y11 and Yl2are derived from X11 andX2, and Y2, and Y22 are derived fromX3, and X4,
This clearly is not in proper time order since Y12 comes before Y2I.
In order to overcome this problem a frequency multiplexer unit 5 as shown in Figure 5 is used. The frequency multiplexer unit 5 has a frequency multiplexer element 6 to which input signal samples are supplied and which feeds its output to a memory 7. The samples generated by the frequency multiplexer element 6 are written into the memory 7 in order and are then read out of the memory 7 in a different pre-set order along an output line 8 to provide an output signal for the unit 5 in proper time order. The read out order of the memory 7 is set by a further memory 9 which stores the read out order instructions.
The output signal samples are read out of the memory 7 in the sequence; Y11, Y2i, Y12, Y22, ....
which is in proper time order.
If we write the input order to the memory 7 as 1, 2, 3, 4 the output order is 1, 3, 2, 4.
The memory 7 in this example must be large enough to store four output samples in order to allow the re-ordering of the 2 time multiplexed output signals to take place. In general the size of memory 7 required is sufficient to store 2N signal samples where N is the number of time multiplexed output signals.
The change in order of the signal samples between the order in which they are read into the memory 7 and the order in which they are read out of the memory 7 is also dependent on the number of time multiplexed signals present in the output of the frequency mutliplexer unit 5.
In order to allow a single type of multiplexer unit 5 to be used to produce a multielement distributed frequency multiplexer, and also in order to provide as much freedom as possible to use the frequency multiplexer units 5 in other situations, the memory 7 is made large enough to contain 2N signal samples for the largest value of N which the frequency multiplexer unit 5 is intended to deal with. This will set a limit on the maximum number of inputs that a multielement distributed frequency multiplexer using the frequency multiplexer units 5 can deal with.
In use the memory 9 has the appropriate read out instructions for the number of time multiplexed output signals that the frequency multiplexer unit 5 is intended to produce loaded into it.
Alternatively the appropriate read out order instructions for all numbers of time multiplexed output signals which the frequency multiplexer unit 5 is capable of producing could be permanently stored in the memory 9 and the frequency multiplexer unit 5 could be merely instructed which of these numbers applied in use.
Clearly either of these approaches will result in the memory 7 being larger than necessary in many uses of the frequency multiplexer unit 5 and an alternative would be to produce the frequency multiplexer units 5 with memories 7 of the minimum necessary size to allow them to handle the number of time multiplexed output signals which they were intended to generate and in this case the read out sequence could be fixed and the need for the memory 9 removed.
However the requirement to produce a very large number of different types of frequency multiplexer units 5 each intended to produce a different number of time multiplexed output signals and the resulting loss of flexibility in their use would generally make this an undesirable option.
It is convenient to think of the memories 7 and 9 as being separate but they could of course be integrated into a single memory unit.
The multiplexer element 6 can be conveniently formed by a multi-tap symmetrical filter having all even numbered taps except for the central tap equal to zero.
It has also been realised that simple demultiplexer units 4 as described with reference to
Figure 4 will not work when arranged in series to produce a multi-stage distributed frequency demultiplexer 40. In this case the problem is caused by the fact that the input samples supplied to each simple multiplexer unit 4 will be in time order and as a result frequency demultiplexing is not possible. Clearly this is a problem.
This problem occurs because in the demultiplexer units 4 input signal samples representing a signal having a bandwidth are combined and processed to form samples representing 2 time multiplexed output signals each having half the bandwidth of the input signal. Since the input and output sample rates are the same it is necessary to combine two input samples representing consecutive parts of the same input signal to generate two output signal samples representing the 2 time multiplexed output signals. This is to be expected since all the information in the two output signals is carried by a single input signal so the same number of samples are required to provide this information.
In the special case where there is only one input signal rather than a plurality of time multiplexed input signals there is no difficulty but this condition only occurs at the first stage of a multi-stage distributed frequency demultiplexer 40 and is generally very limiting in other uses so it is highly desirable to produce a frequency demultiplexer unit 4 which will operate with a plurality of time multiplexed signals.
An illustrative example is for a frequency demultiplexer unit 4 with 2 time multiplexed input signals. The input signal samples will be X11, X;, X12, X22, ... and it is necessary to convert this to an output;
Y11, Y21, Y31, Y41, Y12, Y22, Y32, Y42, ...
where signals Y1 and Y2 are both derived from signal X1 and signals Y3 and Y4 are both derived from signal X2.
The difficulty i that in order to generate output signal samples Yl, and Y2, it is necessary to provide the frequency multiplexing circuits with input signal samples X1 1 and X l 2 simultaneously and these two input signal samples are not consecutively placed in the time multiplexed input to the demultiplexer unit 4.
In order to overcome this problem a similar approach to that described above for the frequency multiplexer unit 5 is used and a frequency demultiplexer unit 10 employing the invention is shown in Figure 6. The frequency demultiplexer unit 10 is supplied with input signal samples in time order along an input line 11 and these input signal samples are written into a memory unit 12 in order. The input signal samples are then read out of the memory 12 in a different preset order to provide an input to a frequency demultiplexer element 13. The samples generated by the frequency demultiplexer element 13 provide the output of the frequency demultiplexer unit 10. The read out order of the memory 12 is set by a further memory 14 which stores the read out order instructions.
In the example the input signal samples are read out of the memory 12 in the sequence; Xll, X12, X21, X22, ... which is out of time order so that samples X1, and X12 are supplied consecutively to the frequency demultiplexer element 13 so that they can be used together to generate output signal samples Y1, and Y2,.
If the input order to the memory 12 is written as 1, 2, 3,4 the output order is 1, 3, 2, 4, note that this is the same output order as was required in the corresponding multiplexer example.
The memory 12 in this example must be large enough to store four input samples in order to allow the re-ordering of the 2 time multiplexed input signals to take place. In general the size of memory 12 required is sufficient to store 2N signal samples where N is the number of time multiplexed input signals.
The change in order of the signal samples between the order in which they are written into the memory 12 and the order in which they are read out of the memory 12 is also dependent on the number of time multiplexed signals precedent in the input to the frequency demultiplexer unit 10.
In order to allow a single type of demultiplexer unit 10 to be used to produce a multielement distributed frequency multiplexer, and also in order to provide as much freedom as possible to use the frequency demultiplexer units 10 in other situations, the memory 12 is made large enough to contain 2N signal samples for the largest value of N which the frequency demultiplexer unit 10 is intended to deal with This will set a limit on the maximum number of inputs that a multi-element distributed frequency demultiplexer using the frequency demultiplexer units 10 can deal with. In use the memory 14 has the appropriate read out instructions for the number of time multiplexed input signals that the frequency demultiplexer unit 10 is intended to process loaded into it.Alternatively the appropriate read out order instructions for all numbers of time multiplexed input signals which the frequency demultiplexer unit 10 is capable of processing could be permanently stored in the memory 14 and the frequency demultiplexer unit 10 could be merely instructed which of these numbers applies in use.
Clearly either of these approaches will result in the memory 14 being larger than necessary in many uses of the frequency demultiplexer unit 10 and an alternative would be to produce frequency demultiplexer units 10 with memories with the minimum neceesary size to allow them to handle the number of time multiplexed input signals which they are intended to deal with and in this case the read out sequence could be fixed and the need for the memory 14 removed. However the requirement to produce a very large number of different types of frequency demultiplexer units 10 each intended to deal with a different number of time multiplexed input signals and the resulting loss of flexibility in use would generally make this an undesirable option.
It is convenient to think of the memories 12 and 14 being separate but they could of course be integrated into a single memory unit.
The demultiplexer element 13 can be conveniently formed by a multi-tap symmetrical filter having all even numbered taps except for the central tap equal to zero.
It will be realised that the multiplexer and demultiplexer applications of this invention are mirror images of one another in that input samples to the demultiplexer and output samples from the multiplexer have to be re-ordered in a similar manner. Although it is convenient and simple for clarity to visualise the memories used to allow this re-ordering as discrete elements separate from the actual multiplexing and demultiplexing elements it would be possible in practice to form both functions in a single integrated circuit or even to carry out all stages of a distributed multi-stage multiplexer or demultiplexer within a general purpose or dedicated computer.
Claims (10)
1. A frequency multiplexer unit having an input and an output each comprising a series of
samples representing input and output signals respectively and including multiplexing
means arranged to convert a plurality of time multiplexed input signals having a set
bandwidth into half as many time multiplexed output signals having twice the bandwidth
and further including means to re-order the signal samples output by the multiplexing
means into time order to provide the output of the frequency multiplexer unit.
2. A frequency multiplexer unit as claimed in claim I in which the multiplexing means is
a multi-tap symmetric filter.
3. A frequency multiplexer unit as claimed in claim 2 in which all even taps of the filter are
equal to zero except for the central tap.
4. A frequency multiplexer unit as claimed in any preceding claim in which the means to
re-order the signal samples output by the multiplexer means comprise a memory which
the signal samples written into and then read out of in a different order.
5. A frequency multiplexer comprising a plurality of frequency multiplexer units as claimed
in any preceding claim arranged in series with the output of each frequency multiplexer
unit in the series providing the input to the next.
6. A frequency demultiplexer unit having an input and an output each comprising a series
of samples representing input and output signals respectively and including
demultiplexing means arranged to convert a number of time multiplexed input signals
having a set bandwidth into twice as many time multiplexed output signals having half
the bandwidth and including means to re-order the input signal samples such that pairs
of time sequential samples of each input signal in turn are supplied to the demultiplexing
means.
7. A frequency demultiplexer unit as claimed in claim 6 in which the demultiplexing means
is a multi-tap symmetric filter.
8. A frequency demultiplexer unit as claimed in claim 7 in which all even taps of the filter
are zero except for the central tap.
9. A frequency demultiplexer unit as claimed in any one of claims 6 to 8 in which the
means to re-order the input signal samples comprise a memory which the input signal
samples are written into and then read out of again in a different order.
10. A frequency demultiplexer comprising a plurality of frequency demultiplexer units as
claimed in any one of claims 6 to 9 arranged in series with the output of each frequency
demultiplexer unit in the series providing the input to the next.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9425195A GB2284967A (en) | 1993-12-10 | 1994-12-12 | Multiplexers and demultiplexers |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB939325305A GB9325305D0 (en) | 1993-12-10 | 1993-12-10 | Communication system |
| GB9425195A GB2284967A (en) | 1993-12-10 | 1994-12-12 | Multiplexers and demultiplexers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9425195D0 GB9425195D0 (en) | 1995-02-08 |
| GB2284967A true GB2284967A (en) | 1995-06-21 |
Family
ID=26304002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9425195A Withdrawn GB2284967A (en) | 1993-12-10 | 1994-12-12 | Multiplexers and demultiplexers |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2284967A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2166327A (en) * | 1984-10-08 | 1986-04-30 | Gen Electric Co Plc | Data communication system |
| GB2195516A (en) * | 1986-09-20 | 1988-04-07 | Stc Plc | Multiplexing arrangement |
| GB2229610A (en) * | 1989-03-10 | 1990-09-26 | Plessey Telecomm | Pcm communication system |
-
1994
- 1994-12-12 GB GB9425195A patent/GB2284967A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2166327A (en) * | 1984-10-08 | 1986-04-30 | Gen Electric Co Plc | Data communication system |
| GB2195516A (en) * | 1986-09-20 | 1988-04-07 | Stc Plc | Multiplexing arrangement |
| GB2229610A (en) * | 1989-03-10 | 1990-09-26 | Plessey Telecomm | Pcm communication system |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9425195D0 (en) | 1995-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4821223A (en) | Two-dimensional finite impulse response filters | |
| KR900001449B1 (en) | Multiplexed real-time pyramid signal processing system | |
| US5339264A (en) | Symmetric transposed FIR digital filter | |
| CA2355528A1 (en) | Multi-stream merge network for data width conversion and multiplexing | |
| US5477543A (en) | Structure and method for shifting and reordering a plurality of data bytes | |
| US3829670A (en) | Digital filter to realize efficiently the filtering required when multiplying or dividing the sampling rate of a digital signal by a composite integer | |
| Bates et al. | FPGA implementation of a median filter | |
| JPH0284689A (en) | Video memory device | |
| KR920004965A (en) | Fast Pure Conversion Processor in Pipeline Configuration | |
| US4893265A (en) | Rate conversion digital filter | |
| US5101445A (en) | Method and apparatus for filtering digital data by concatenating preprocessed overlapping groups of the data | |
| GB2284967A (en) | Multiplexers and demultiplexers | |
| US5453743A (en) | Two-dimensional symmetric thermometer matrix decoder of digital/analog converter | |
| US5928314A (en) | Digital filter having a substantially equal number of negative and positive weighting factors | |
| EP1040575B1 (en) | Digital signal filter using weightless neural techniques | |
| US5053984A (en) | Memory for programmable digital filter | |
| EP0373410B1 (en) | Memory for programmable digital filter | |
| KR970008103B1 (en) | 2-dimensional digital filter | |
| KR100196603B1 (en) | Dynamically configurable signal processor and processor arrangement | |
| Mendelsohn | Packing a square lattice with a rectangle-free set of points | |
| CA2298999A1 (en) | Digital channelizer having efficient architecture for cyclic shifting and method of operation thereof | |
| JPS58146082A (en) | Memory circuit | |
| JP3070618B2 (en) | Alignment circuit | |
| JPS61242497A (en) | Multiple time switch | |
| JP3099955B2 (en) | Multiplexer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |