JPS5837759A - Electronic desk top calculator with melody - Google Patents

Electronic desk top calculator with melody

Info

Publication number
JPS5837759A
JPS5837759A JP56135110A JP13511081A JPS5837759A JP S5837759 A JPS5837759 A JP S5837759A JP 56135110 A JP56135110 A JP 56135110A JP 13511081 A JP13511081 A JP 13511081A JP S5837759 A JPS5837759 A JP S5837759A
Authority
JP
Japan
Prior art keywords
output
frequency
key
circuit
scale
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56135110A
Other languages
Japanese (ja)
Inventor
Norio Sudo
須藤 憲男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56135110A priority Critical patent/JPS5837759A/en
Publication of JPS5837759A publication Critical patent/JPS5837759A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/02Digital computers in general; Data processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators
    • G06F15/0216Constructional details or arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Calculators And Similar Devices (AREA)
  • Electrophonic Musical Instruments (AREA)

Abstract

PURPOSE:To keep musical scale to a prescribed frequency while a key is depressed, by storing a musical scale setting ROM output to a latch during the depression of the key and switchingly controlling an oscillating frequency of an oscillation circuit through the detection of this latched output. CONSTITUTION:In an electronic desk top calculator with melody, a phenomenon that a musical scale is changed through the change from a high frequency during operation into a low frequency of post processings on the way if a key is kept depressed, is prevented. When the key is depressed, an output IC1 of ROM for musical scale setting is outputted and a tone scale frequency corresponding to entry keys is set. This output IC1 is stored in a latch circuit I1. The output of the I1 is detected at a detection circuit 9 and an oscillation circuit 3 is oscillated in a high frequency. While the tone is given, an output of a NOR circuit NR4 of the circuit 9 goes to ''0'', and even if an operation display switching signal goes to ''1'', the output of an AND circuit AG remains ''0'' and the oscillation frequency of the oscillator 3 remains to the high frequency, then the musical scale can be kept to a prescribed frequency during the depression of the key.

Description

【発明の詳細な説明】 本発明はメロディ付電子卓上計算機に関する。[Detailed description of the invention] The present invention relates to an electronic desktop calculator with a melody.

近年、メロディが弾ける電子卓上計算機(以下単に電卓
と略す)が市場に出廻っている。これらの電卓祉、殆ん
どのものが置数キー(n〜図)と小数点キーを用いて各
々のキーに割当てられた音階が圧電プデーによシ鳴るよ
うになっている0例えばキー口は低いツ(L、a)、1
11は低いシ(B1)、■はド(Do)、IIDはしく
Re)、DH高いしくう)という具合に割当てられ、各
各のキーを押すことによってメロディを弾けるようにし
ている。
In recent years, electronic desktop calculators (hereinafter simply referred to as calculators) that can play melodies have been on the market. Most of these calculators use numeric keys (n to figure) and decimal point keys, and the scale assigned to each key is sounded by a piezoelectric pad.For example, the key opening is low. Tsu (L, a), 1
11 is assigned as low B (B1), ■ is assigned as C (Do), IID is assigned as Re (re), and DH is assigned as high (re), and the melody can be played by pressing each key.

ところで、これらの音階轄絶対音階ではなく、電卓の基
準クロックによシ音階(周波数)は変動するが、それぞ
れの音階の差鉱一定である。
By the way, these scales are not absolute scales, and the scales (frequency) vary depending on the reference clock of the calculator, but the difference between each scale is constant.

また、音長についてはキーを押す時間によって決定され
、長い音を鳴したい時はそのキーをずっと押しているこ
とが必要である。
Furthermore, the length of a note is determined by the length of time a key is pressed, and if you want to play a long note, you must hold down that key for a long time.

一方、電卓自身については、ローパワー化の次め演算中
は高周波で処乏し、表示中になると低周波にして消費電
力を減少させる周波数切換方式が主流を占めている。従
って従来の電卓において置数を考える時、第1図に示す
ように置数処理は高周波で処理し、後処理は低周波にて
処理して表示するが、ここでキーが押されていたら後処
理にて次のキーとの区別のためにキーが離されるまで後
処理ルーチンを回っていることとなる。つまシ、キーを
押しfcままだと後処理中にて低周波表示が行なわれる
ことになる。このことは、例えにいま従来のメロディ付
電卓で長い音を鳴らす時、ある置数キーを押した11に
するのであるが、音階の設定は演算結果前の設定及び演
算速度のため演算中の高周波にて設定し、キーを押した
ままにしていると途中から後処理(表示中)の低周波に
変化してしまい、音階が狂ってしまうという欠点かあ−
)た。
On the other hand, for calculators themselves, the mainstream is a frequency switching system that reduces power consumption by switching to a high frequency during calculations and then switching to a low frequency when displaying to reduce power consumption. Therefore, when considering numbers on a conventional calculator, as shown in Figure 1, the number processing is processed at high frequency, and the post-processing is processed and displayed at low frequency. During processing, the post-processing routine continues until the key is released in order to distinguish it from the next key. If the thumb and key are held down and the fc key is held down, low frequency display will be performed during post-processing. For example, when playing a long note on a conventional calculator with a melody, it is set to 11 by pressing a certain numeric key, but the scale is set before the calculation result and during calculation due to the calculation speed. If you set it to a high frequency and hold down the key, it will change to the low frequency of the post-processing (displaying) midway through, causing the scale to go out of order.
)Ta.

本発wAは上記の欠点を解消するためになされたもので
、キーが押されている間は音階設定用ROM出力を森持
するラッチ手段と、このラッチ手段の出力を検出して音
階指定期間を検出する手段を設け、この検一手段の検出
出力によって発振回路の発振周波数を切換え制御するこ
とによって、キーが押されている間は音階を一定周波数
に保りて音階の狂いをなくし得るメロディ付電子卓上計
算機を提供することを目的とする。
The present wA was made to eliminate the above-mentioned drawbacks, and includes a latch means that holds the scale setting ROM output while the key is pressed, and a latch means that detects the output of this latch means and waits for the scale specification period. By providing a means for detecting this, and controlling the oscillation frequency of the oscillation circuit by switching the oscillation frequency of the oscillation circuit based on the detection output of this detection means, the melody can be created so that the scale can be maintained at a constant frequency while the key is pressed, eliminating any deviations in the scale. The purpose is to provide an electronic desktop calculator.

以下、図面を参照して本発明の一実施例を説明する。第
2図は本発明のメロディ付電子卓上計算機の基本的な置
数70−を示しており、ステップS1のキー待ち、ステ
ップSsの前処理における置数キーを押した時には低周
波にて動作し、ステップ8Iの置数処理である演算中は
高周波で動作し、この時点で現在の置数キーに対応し良
音階が設定される。これによp音を鳴らし、ステップε
の後処理2に移行するが、ここで中−が押されたままで
あると、高周波で処理されるステップS4の音階設定処
理に戻し、再度高周波にて音階を設定し、ステラfB、
の高周波の後処理1を通じてまた高周波のステップ8I
の音階設定KjIるという動作の繰シ返しとなる。従っ
て、キーが押されている間はこのステップ84e8gを
繰夛返し、キーが離された時点でステップSsの後処理
1から低周波の後処理2であるステップS・に制御動作
は移行する。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Fig. 2 shows the basic number 70- of the electronic desk calculator with melody of the present invention, which operates at a low frequency when the number key is pressed during the key wait in step S1 and the preprocessing in step Ss. , during the calculation which is the numeric value setting process in step 8I, it operates at a high frequency, and at this point a good tone scale is set corresponding to the current numeric value key. This produces a p sound and steps ε
The process moves to post-processing 2, but if the middle key is still pressed here, the process returns to the scale setting process in step S4, which is processed using high frequency, and the scale is set using high frequency again, Stella fB,
through the high frequency post-processing 1 and also the high frequency step 8I
The operation of setting the scale KjI is repeated. Therefore, steps 84e8g are repeated while the key is pressed, and when the key is released, the control operation shifts from step Ss post-processing 1 to step S. which is low frequency post-processing 2.

上述した基本動作を実現した要部回路をwJ3図に示す
0図において、11〜1マはクロックドインバータCI
I  IC1,及びノア回路NR。
In Figure 0, which shows the main circuit that realizes the basic operation described above in Figure wJ3, 11 to 1 are clocked inverters CI.
I IC1, and NOR circuit NR.

にて構成されるラッチ回路で、このラッチ回路11〜1
1社それぞれ図示しない音階設定用のROM (リード
オンリメモリ)の出力IC1〜ICFを音のスタート信
号φ1とインノf−タ!lにて反転された反転スタート
信号φ1に同期して取り込む、このスター)信号φ1は
フローにて音を鳴らし始める時に出る信号で、新たな音
の開始時に順次出力される信号である。このラッチ回路
11〜1丁は音の終シの信号SRと信号hc。
This latch circuit 11-1 is a latch circuit composed of
Each company uses the output IC1 to ICF of a ROM (read-only memory) for setting scales (not shown) as a sound start signal φ1 and an innotator! This star signal φ1, which is taken in in synchronization with the inverted start signal φ1 inverted at step 1, is a signal that is output when a sound starts to be played in the flow, and is a signal that is sequentially output when a new sound starts. These latch circuits 11 to 1 receive a signal SR and a signal hc at the end of the sound.

を入力するナンド回路NA、によpそのラッチ動作が制
御される。2は基本クロック発生回路であシ、抵抗RI
IB露、容量C1インI4−タ1l−In及び伝達r 
−) T Gにより形成される発振周波数切換可能°な
発振器3と、この発振器3の出力を受けて基本クロック
XTを形成するフリッグフロッグイとで構成されている
。6は上記発生回路2からの基本クロックXTを分周し
て設定された所定音階の周波数fを得る分周回路で、こ
の分JliiI21路5には前記音階設定用ROM O
出力l0=f 〜IC7に対応して7個のリセット優先
付フリップフロップ61〜61と、このアリラグフロラ
!61〜61のリセット端子虱にそれぞれ接続されるリ
セット用ノア回路NR,と、これら7リツプフロツプ6
1〜6テの各出力を入力するノア回路NR,と、このノ
ア回路NR,の出力を入力し前記基本クロックX!にて
動作するフリップフロッグ1と、このフリップフロップ
1の出力を入力し前記所定の音階周波数fを得るフリッ
プフロップ1とを有している。なお、上記各リセット用
ノア回路NRIには、前記各ラッチ回路11〜11の出
力と7リツプフロツグ1の出力信号が供給されて−る。
The latch operation is controlled by the NAND circuit NA, which inputs p. 2 is the basic clock generation circuit, resistor RI
IB dew, capacitance C1 in I4-ta l-In and transmission r
-) It is composed of an oscillator 3 formed by TG whose oscillation frequency can be switched, and a flip-frog which receives the output of this oscillator 3 and forms a basic clock XT. Reference numeral 6 denotes a frequency dividing circuit that divides the basic clock XT from the generation circuit 2 to obtain the frequency f of a predetermined scale.
Output l0=f ~ Corresponding to IC7, 7 flip-flops 61 to 61 with reset priority, and this Arilag Flora! Reset NOR circuits NR connected to the reset terminals 61 to 61, respectively, and these seven lip-flops 6.
A NOR circuit NR inputs each output of 1 to 6 TE, and the output of this NOR circuit NR is inputted to generate the basic clock X! The flip-flop 1 is provided with a flip-flop 1 which operates at a frequency f, and a flip-flop 1 which inputs the output of the flip-flop 1 to obtain the predetermined scale frequency f. Note that the outputs of the respective latch circuits 11 to 11 and the output signal of the 7 lip-frog 1 are supplied to each of the reset NOR circuits NRI.

tた、−は上記ラッチ回路11〜1フの出力を受け、音
階が設定されている関(キーが押されている関)を検出
するノア回路NR4を有する検出回路、10は周波数切
換回路で、上記ノア回路NR,の出力信号と演算か表示
かを切換える演算表示切換信号とを入力するアンドゲー
トAG、およびこのアンドr −) A Gの出力を反
転するインバータ!暮を有している。
t, - are detection circuits having a NOR circuit NR4 which receives the outputs of the latch circuits 11 to 1 and detects the key for which a scale is set (the key is pressed), and 10 is a frequency switching circuit. , an AND gate AG which inputs the output signal of the NOR circuit NR, and a calculation/display switching signal for switching between calculation and display, and an inverter which inverts the output of the AND gate AG! I have a life.

こO切換回路10からの発振周波数切換信号によって前
記発振器3の伝達ダートτGをオン動作させ、発振器3
の発振周波数を定数J+C1により設定される周波数か
ら定数R1* R露 *C1によ!l設定される周波数
に切換えるようKしている。
The transmission dart τG of the oscillator 3 is turned on by the oscillation frequency switching signal from the O switching circuit 10, and the oscillator 3
The oscillation frequency of is determined from the frequency set by the constant J+C1 by the constant R1*R*C1! It is set to switch to the set frequency.

次に、上記メロディ付電卓の回路動作を簡単に説明する
。今、あるキーが押されると、対応する音階設定用RO
Mの出力、例えばICfが出力されて、この音階設定用
ROMの出力ICJK基づいて置数キーに対応した音階
周波数が設定される。このROMの出力ICIは音のス
タート信号φ1によりてラッチ回路11に記憶される。
Next, the circuit operation of the calculator with melody will be briefly explained. Now, when a certain key is pressed, the corresponding scale setting RO
The output of M, for example ICf, is output, and the scale frequency corresponding to the numeric key is set based on the output ICJK of this scale setting ROM. The output ICI of this ROM is stored in the latch circuit 11 in response to the sound start signal φ1.

このラッチ回路1*Id、記憶したROMの出力ICJ
を次の新たな音のスタート信号φ1が出る壕で、あるい
はその音の終多信号SRが出るまで保持する。このと亀
、検出回路9のノア回路NR4の出力は、音階設定時F
i”o’レベルであるので切換回路10のアンドp −
) A Gの出力は@01となる。従って、発振@3は
高周波数で発振している。フリップフロッグ4から発生
した高JlilIILの基本クロックXTは分周回路5
にてROMの出力ICIに対応した音階にて分周され、
置数キーに対応した音階周波数fを得る。
This latch circuit 1*Id, the output ICJ of the stored ROM
is held until the start signal φ1 of the next new tone is output or until the end signal SR of that tone is output. In this case, the output of the NOR circuit NR4 of the detection circuit 9 is F when the scale is set.
Since it is at the i''o' level, the AND p − of the switching circuit 10
) The output of A G will be @01. Therefore, oscillation@3 is oscillating at a high frequency. The high JliilIIL basic clock XT generated from the flip-flop 4 is sent to the frequency divider circuit 5.
The frequency is divided by the scale corresponding to the output ICI of the ROM,
Obtain the scale frequency f corresponding to the number key.

ここで、この音階設定用ROMの出力は音階を設定する
ときは必ず1つは11ルベルが指定されているので、音
が鳴っている間は検出回路9のノア回路NR4C)出力
は″″0#0#レベル、演算表示切換信号が@1#レベ
ルとなってもアンドグートムGの出力社10#レベルの
ままであ多、発@@go発振周波数は高周波のままであ
る。押されていゐキーが離されて音の終シを示す信号1
1が“1#となると、あるいは次のキーが押されて新た
な音のスタート信号φ、が1#となると、ラッチ回路1
!に保持されてい7’j ROMの出力ICIがクリア
され、ノア回路N RA Om力B @s ’レベルと
なる。従って、切換回路10のアンドr−)AGは、″
l”レベルの演算表示切換信号とによシその出力は“1
#レベルとカリ、この切換回路10C)出力信号によっ
て発振器3の伝達グー)、TGをオン動作させ、この発
振器SO発振周波数を高周波tλら低周波に切換えて後
処理を実施すゐ。
Here, when setting the scale, one of the outputs of this scale setting ROM is always specified as 11 levels, so while the tone is sounding, the output of the NOR circuit NR4C of the detection circuit 9 is ""0. #0# level, even if the arithmetic display switching signal becomes @1# level, the output of AND GOTO G remains at 10# level, and the oscillation frequency remains high. Signal 1 indicating the end of the sound when the pressed key is released
When 1 becomes "1#" or when the next key is pressed and the new sound start signal φ becomes 1#, latch circuit 1
! The output ICI of the 7'j ROM is cleared, and the NOR circuit NRA Om output becomes the level B@s'. Therefore, the ANDr−)AG of the switching circuit 10 is “
Its output is "1" level calculation display switching signal.
# The output signal of this switching circuit 10C) turns on the TG of the oscillator 3, switches the oscillation frequency of this oscillator SO from the high frequency tλ to the low frequency, and performs post-processing.

このように上記メロディ付電卓では、キーを押したtま
の時、つまp音階が指定されている時は、その状態を検
出して後処理中でも周波数切換えをしないで高周波のt
−iに保持して童、lSI&を一定周波数に保てるので
、キーを長く押し続けても音階の狂いはかくなる。
In this way, with the above-mentioned calculator with melody, when the key is pressed at t, when the tsume p scale is specified, that state is detected and the high frequency t is output without changing the frequency even during post-processing.
By keeping it at -i, you can keep lSI& at a constant frequency, so even if you keep pressing the key for a long time, the scale will be out of order.

以上説明したように本発明によれば、を数キーが押され
ている間L1この置数キーに対応した音階を設定する音
階設定用ROMの出力を保持するラッチ手段と、このラ
ッチ手段の出力を検出して音階指定期間を検出する手段
を設け、この検出手段の検出出力によって発振回路の発
振周波数を切換え制御しているので、キーが押されてい
る間は音階を一定周波数に保って音階の狂いをなくし得
るメロディ付電子卓上計算機を提供できる。
As explained above, according to the present invention, the latch means holds the output of the scale setting ROM that sets the scale corresponding to the L1 number key while the number key is pressed, and the output of this latch means. The oscillation frequency of the oscillation circuit is controlled by switching the oscillation frequency of the oscillation circuit based on the detection output of this detection means, so as long as the key is pressed, the scale is kept at a constant frequency and the scale is played. It is possible to provide an electronic desktop calculator with a melody that can eliminate the confusion.

【図面の簡単な説明】[Brief explanation of the drawing]

第1@は従来のメロデ(付電卓の置数70−チイート、
第2図は本発明のメロディ付電卓のIllアフロ−チャ
ート第3図は本発明のメロディ付電卓の一実施例を示す
喪S回路構成図でおる。 1・・・ラッチ回路、2・・・基本クロック発生回路、
3・・・発t!器、4,6,1.8・・・フリップフロ
ッグ、5・・・分局回路、9・・・検出回路、10・・
・周波数切換回路。
The first @ is the conventional melody (number 70 on the calculator - cheat,
FIG. 2 is an Ill flow chart of a calculator with a melody according to the present invention. FIG. 3 is a block diagram of a mourning S circuit showing an embodiment of a calculator with a melody according to the present invention. 1...Latch circuit, 2...Basic clock generation circuit,
3... Departure! 4, 6, 1.8...Flip frog, 5...Branch circuit, 9...Detection circuit, 10...
・Frequency switching circuit.

Claims (1)

【特許請求の範囲】[Claims] 発振回路の発振周波数を切換えて置数キーに対応した音
階の音を発生するようにしたメロディ付電子卓上計算機
において、前配置数キーが押されている間はこの置数キ
ーに対応した音階を設定する音階設定回路の出力を保持
するラッチ手段と、このラッチ手段の出力によって前記
発振回路の発振出力を分周して押されたキーに対応した
音階の周波数信号を得る分局手段と、前記ラッチ手段の
出力を検出して音階指定期間を検出する検出手段と、こ
の検出手段の検出出力によって前記発振回路の発振周波
数を切換える手段とを具備し、前記キーが押されている
間は音階を一定周波数に保つようにしたことを特徴とす
るメロディ付電子卓上計算機。
In an electronic desktop calculator with a melody that changes the oscillation frequency of the oscillation circuit to generate the notes of the scale corresponding to the number keys, while the front number key is pressed, the scale corresponding to the number key is played. a latch means for holding the output of the scale setting circuit to be set; a division means for dividing the oscillation output of the oscillation circuit by the output of the latch means to obtain a frequency signal of the scale corresponding to the pressed key; and a means for switching the oscillation frequency of the oscillation circuit according to the detection output of the detection means, and the scale is kept constant while the key is pressed. An electronic desktop calculator with a melody that maintains the frequency.
JP56135110A 1981-08-28 1981-08-28 Electronic desk top calculator with melody Pending JPS5837759A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56135110A JPS5837759A (en) 1981-08-28 1981-08-28 Electronic desk top calculator with melody

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56135110A JPS5837759A (en) 1981-08-28 1981-08-28 Electronic desk top calculator with melody

Publications (1)

Publication Number Publication Date
JPS5837759A true JPS5837759A (en) 1983-03-05

Family

ID=15144063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56135110A Pending JPS5837759A (en) 1981-08-28 1981-08-28 Electronic desk top calculator with melody

Country Status (1)

Country Link
JP (1) JPS5837759A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60259088A (en) * 1984-06-06 1985-12-21 Yoshiro Nakamatsu Speaker equipment
JPS6290743A (en) * 1985-10-16 1987-04-25 Ongaku No Tomoshiya:Kk Multifunctional electronic desk calculator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368051A (en) * 1976-11-29 1978-06-17 Sharp Corp Integrated circuit device
JPS5583945A (en) * 1978-12-19 1980-06-24 Ricoh Co Ltd Abnormal action preventing system for unit controlled by microcomputer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368051A (en) * 1976-11-29 1978-06-17 Sharp Corp Integrated circuit device
JPS5583945A (en) * 1978-12-19 1980-06-24 Ricoh Co Ltd Abnormal action preventing system for unit controlled by microcomputer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60259088A (en) * 1984-06-06 1985-12-21 Yoshiro Nakamatsu Speaker equipment
JPS6290743A (en) * 1985-10-16 1987-04-25 Ongaku No Tomoshiya:Kk Multifunctional electronic desk calculator

Similar Documents

Publication Publication Date Title
JPS6219994Y2 (en)
US4354246A (en) Key input indicating tone generating apparatus for small-sized electronic devices
JPH0321920B2 (en)
JPS5837759A (en) Electronic desk top calculator with melody
JPH0527753A (en) Electronic musicla instrument
US4294154A (en) Music tone generating system
JPH0359396B2 (en)
JPH0331273B2 (en)
US4630222A (en) One chip integrated circuit for electronic apparatus with means for generating sound messages
JPH0628718Y2 (en) Stopwatch
JP2819548B2 (en) Electronic musical instrument control information transmission device
JP2661211B2 (en) Sound signal generator, sound signal generation method, and musical sound generator including the same
JPH0587958A (en) Multifunction electronic timekeeper
JPH0215299A (en) Musical sound synthesizing device
JPH0242491A (en) Musical sound synthesizer
JPS6312988A (en) Schedule display device
JPH10187622A (en) Tax calculator and tax calculating method
JPH02134696A (en) Sound generating device
CA1097105A (en) Electronic musical instrument with device for selecting tone clock numbers
JPH0723758Y2 (en) Zero-zero switch mechanism
JPS646557Y2 (en)
JP2513600Y2 (en) Data bank device
JPH0653820A (en) Clock frequency dividing circuit
JPS6231311B2 (en)
JPS601983B2 (en) Frequency divider circuit