JPS583680U

JPS583680U - Video signal processing circuit

Info

Publication number: JPS583680U
Application number: JP9579181U
Authority: JP
Inventors: 内原　利夫; 正弘藤原
Original assignee: 三菱重工業株式会社
Priority date: 1981-06-27
Filing date: 1981-06-27
Publication date: 1983-01-11
Also published as: JPS6241505Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は公知のＩＴＶによる金属表面の目視検査−要領
を示す側面図、第２図は第１図による照度分布図、第３
図は第１図における画面と映像信号を示す説明図、第４
図Ａ、　Ｂは第３・図における走査信号とフィールド信
号の歪を示す線図、第５図Ａ。Ｂは第４図の部分拡大図、第６図は本考案の一実施例を
示すブロック線図、第７図Ａ、　Ｂ、　Ｃ，Ｄは第６図
における各部の出力信号波形図、第８図は第６図による
映像信号波形の自レベルと黒レベルの関係を示す線画、
第９図は第６図の２値化回路の作用を示す説明図である
。Ａ・・・入力映像信号、Ｂ・・・出力映像信号、１３・
・−搬送波除去回路、１４・・・ゲイン補正回路、１５
・・・ピークホールド回路、１６・・・Ｈ・■同期分離
回路、１７・・・２値化設定用比較レベル抽出回路、１
８・・・ＩＨ遅延回路、１９・・・浮動値抽出回路、２
０・・・ゲイン補正回路、２１・・・ＩＨ遅延回路、２
２・・・歪除去演算回路、２３・・・２値化回路、２４
・・・歪波形、＝２゛５・・・浮動設定値、２６・・・
２２の出力波形、２７・・・歪波形、２８・・ゼークレ
ベル■、２９・・・２３の出力波形、３０・・・走査線
信号、３１・・・白レベル、。３２・・・黒レベル、３３・・・ペデッサルレベル、３
４・・・非線形・特性、′３５・・・オフセットレベル
、ｂ。３６・・・近似特性、３８・・・２値化鰻定レベル。Fig. 1 is a side view showing the procedure for visual inspection of metal surfaces using a known ITV, Fig. 2 is an illuminance distribution diagram according to Fig. 1, and Fig. 3
The figure is an explanatory diagram showing the screen and video signal in Figure 1,
Figures A and B are diagrams showing the distortion of the scanning signal and field signal in Figure 3 and Figure 5A. B is a partially enlarged view of FIG. 4, FIG. 6 is a block diagram showing an embodiment of the present invention, FIGS. 7A, B, C, and D are output signal waveform diagrams of each part in FIG. 6, and FIG. The figure is a line drawing showing the relationship between the own level of the video signal waveform and the black level according to FIG.
FIG. 9 is an explanatory diagram showing the operation of the binarization circuit of FIG. 6. A... Input video signal, B... Output video signal, 13.
-Carrier removal circuit, 14...gain correction circuit, 15
...Peak hold circuit, 16...H・■ synchronization separation circuit, 17...Comparison level extraction circuit for binarization setting, 1
8...IH delay circuit, 19...Floating value extraction circuit, 2
0...Gain correction circuit, 21...IH delay circuit, 2
2... Distortion removal calculation circuit, 23... Binarization circuit, 24
...Distortion waveform, =2゛5...Floating setting value, 26...
22 output waveform, 27...distorted waveform, 28...zeke level ■, 29...23 output waveform, 30...scanning line signal, 31...white level. 32...Black level, 33...Pedesal level, 3
4...Nonlinear characteristic, '35...Offset level, b. 36... Approximate characteristics, 38... Binarized eel fixed level.

Claims

[Scope of utility model registration request]

A floating value setting function circuit consisting of a floating value extraction circuit that inputs a video signal and extracts a floating value of its distorted waveform, a gain correction circuit, an IH delay circuit, and a distortion removal calculation circuit, a gain correction circuit that inputs the video signal. , a peak hold circuit, a comparison level extraction circuit for binary setting that outputs a set value corresponding to the magnitude of the output of the peak hold circuit, a binary setting function circuit consisting of an IH delay circuit, and the output of the floating value setting function circuit. and a digitization circuit that inputs the output of the binarization setting function circuit, compares the two, and performs optimal binarization.