JPS5836789B2 - Hyōjikudō Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display drive circuit, and more particularly to a display drive circuit for turning on or off a large number of display elements (lamps, LEDs, etc.) all at once or individually.

Conventionally, for example, in a control device, a large number of indicator lamps (IEDs) have been installed to correspond to the large number of devices to be controlled]
The operating status of each device is displayed by turning on or off these indicator lamps.

Various types of display drive circuits for turning on or off a large number of display lamps have been proposed and implemented.

However, this type of display drive circuit generally has various drawbacks that need to be overcome, such as an increase in the number of lamp drive circuits, an increase in power consumption, and an increase in the number of instruction circuits for turning on or off each display lamp.

Such drawbacks cause the display drive circuit itself to become complicated and to increase in cost.

Therefore, the main object of the present invention is to provide a display drive circuit that can overcome all of the above-mentioned disadvantages with a relatively simple configuration.

In summary, the present invention includes a counter for individually and sequentially addressing a plurality of display elements, means for specifically addressing any one of the plurality of display elements, and a counter for individually and sequentially addressing a plurality of display elements; and a memory for setting and storing lighting or extinguishing of the display elements, and further derives the output of the counter and the output of the specific addressing means in an OR manner, and controls the display elements of the plurality of display elements according to the OR circuit output and the memory output. This is a display drive circuit that turns on or off the light.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 1 is a functional block diagram conceptually showing the present invention.

In the construction precepts, an example is information processing equipment such as computers (
(not shown), a plurality of lamps L1, L2, .
...The coded signal that specifically addresses the lamp to be turned on or off out of Ln is the gate circuit GT.
given to.

At the same time, the information processing device provides a signal indicating whether the addressed lamp should be turned on or off, a lamp-on signal or a lamp-on signal.

The gate circuit GT is opened by this lamp-on signal or lamp-off signal, and at this time, the lamp address code is applied as one input to the OR circuit OR.

The other input of the OR circuit OR is connected to the plurality of lamps L.
An n-ary counter CT output is provided for individually and sequentially (cyclically) addressing 1 to Ln, and the output is provided to decoders DC1# and DC2.

One decoder DC1 receives the output of the OR circuit, decodes this coded signal, and decodes the plurality of lamps L.
The address output corresponding to 1 to hill is given to the memory ME.

This memory ME derives an output indicating whether the lamp at the address should be turned on or off based on the address input from the decoder DC1 and the lamp-on signal or the lamp-off signal.

The driver l)R drives the lamps L1 to Ln all at once to turn on or to a non-driving state based on the output of the memory lJME.

The other decoder DC2 similarly receives the OR circuit output, decodes this coded signal, and activates only the corresponding lamp.

Therefore, the lamps L1 to Ln are individually turned on or off by the driver DR output and decoder DC2 output.

FIG. 2 is a specific rotation block showing a preferred embodiment of the invention according to FIG.

In configuration, this example has 16 lamps L.

t L1 y L2 t...L15 is shown as a display drive circuit for display driving.

The lamp address signal from the information processing device is given, for example, as a 4-bit BCD code, and is sent to each of the NAND gates G1, G2, G3G4 corresponding to each bit via input terminals bl*b2e b3*b4. On the other hand, it is given as human power.

These NAND gates G1, G2, G3, and G4 constitute the gate circuit GT, and the output of the NAND gate G5 is applied to the other input.

Further, the lamp-on signal LMPON'j6 and the lamp-off signal LMP OFF are both given as two inputs to the NAND gate G5, and are also applied to the memory M.
given to E.

The counter CT is composed of, for example, four flip-flops F1 to F4 connected in series. It is a hexadecimal counter, and its reset terminal R is given an inverted output from the inverter 15 of the output of the NAND gate G5.

The OR circuit OR is a wired OR composed of lines A, B, C, and D, for example.

The lines A to D of this OR circuit OR are each pulled up to +5.times.("field") via appropriate resistors.

Furthermore, these lines A, B, C, and D include, for example, 1-2-4-
The NAND gate G1 t G2 is given a weight of 8.
p G3 s G4 output and each flip-flop F1 y F2 y F3 p Inverter I receiving the outputs Q1, Q2, Qa, Q4 of F4
The outputs of 1 y I2 yI3 t■4 are connected.

Therefore, these NAND gates 01 to G4'j6 and inverters 1 to 4 are both configured as open collectors.

Each line A-D of this OR circuit OR has two decoders DC
~Connected to each bit input of DC2.

The decoders DC1 and DC2 are, for example, a multiplex circuit, and decode the input 4-bit A, B, C, and D coded signal input, and output the lamp L.

- Low level that specifies L15 (L (W level)
: rLj) Signal 0, 1, 2...15
Derive.

The rLJ signal o-15 output from the decoder DC1 is
Each address is individually given to each address 0-15 of the card memory ME.

In addition, the "L" signal O~1 output from the decoder DC2
5 is a bill Lamp L.

Separately applied to one end of S-L 15.

The memo IJME is lamp L.

-L15, and each of the 16 addresses is formed with an area in which 1 written by the lamp-on signal LMP ON and 0 written by the lamp-off signal LMP OFF are written.

Therefore, this memo IJME outputs the lamp number addressed by the decoder DC1 and a signal 1 indicating lighting of the addressed lamp or a signal O indicating turning off, which are applied to the driver DR.

Therefore, the driver DR reads 1 from the memo IJIJE.
or high level in response to 0.
l * Outputs "H.l) or "L", 16 lamps L.

~I-'15 in common to each other end.

The operation of the above configuration will be explained below.

In operation, first the lamp L.

Let us consider the case where any one of L15 is turned on or off at +W.

As an example, let us assume that the third lamp L2 is instructed to be turned on.

At this time, the lamp address code input terminals b1, b2,
A coded signal rll00J indicating "3" (corresponding to the lamp L2) in the BCD code is input in parallel bits to t)3yb4.

At the same time, a lamp-on signal LMP ON of rLJ is applied to turn on lamp L2.

This lamp-on signal LMP ON is inverted by a NAND gate G5, and each gate 0 of the gate circuit GT
1 to G4 as well as to the inverter 15.

Therefore, the NAND gates G1-G4 are opened and the address code "1100" is applied to lines A, B, C, and D individually.

On the other hand, at this time, the inverter 15 outputs the NAND
The inverted "L" output from gate G (lamp-on signal) is output.

Therefore, each flip-flop p, A, p of counter CT
, or is reset, and its outputs Q1 to Q4 are "0000"
It is.

Therefore, the inverter that becomes the other human power of the OR circuit
Each output of 1 to ■4 becomes [11 1J, and lines A, B, and C
, D individually.

Therefore, these lines A, B, C, and D become 1, 1, 0, 0, and are applied bit-parallel to decoders DC1 and DC2.

Therefore, since the lines A, B, C, and D are weighted 1-2-4-8, the decoders DC1 and DC2 receive the input OR circuit output "1100" and decode it using a matrix, for example. , rLJ on the third output line
Derive signal 2 of .

Therefore, the third address (corresponding to the lamp L2) of the memo IJME is specified, and the signal 1 corresponding to the lamp-on signal "ON" is written to this address.

That is, this memory ME turns on the lamp (rL) at the address (third address) addressed by the decoder DC1.
J) and store it.

In this way, the fact that the third lamp L2 should be turned on is set and stored in the memory ME.

Therefore, this memo IJME outputs a signal indicating the lighting of the lamp L2, and the driver DR is accordingly energized.

Therefore, the voltage of ■ is output from the drive DR, and the lamp L.

~L15 is commonly applied.

On the other hand, the decoder Dc2 outputs a signal that tosses "L" only the line connected to the lamp L2.

Therefore, only the lamp L2 turns on due to the drive current from the driver DR. be done.

Next, the memo IJME is already on each lamp L.

Let us consider a case where the lighting or turning off of L15 is stored fvIIJ-wise and sequentially addressed by a counter CT, that is, a case of display.

As an example, assume here that the memory ME is set and stored so that only the lamp L1 is turned off and all other lamps are turned on.

Therefore, "o" is written only in the second address (corresponding to lamp L1) of memo IJME, and "o" is written in all other addresses.
1" is written.

In addition, as shown in FIGS. 3a to 3e, the counter CT
is "OOOO" ~ JIII by the clock signal CP.
It is sequentially stepped up to J.

Therefore, the lines A, B, C, and D of the OR circuit OR are inverted by the inverters ■1 to ■4, and the lines A, B, C, and D of the OR circuit OR become rl 11 1j to "O
000".

Therefore, decoders DC1 and DC2 are
As shown in FIG. U, an rLJ signal designating the 16th address to the 1st address is derived in accordance with the increment of this counter CT and therefore the OR output of the OR circuit.

Therefore, addresses from the 16th address to the 1st address of the memory IJME are sequentially addressed (this is synchronous with the clock signal CP),
From this memory ME, a signal "1" or "0" indicating whether to turn on or off is derived for each address.

For example, when the counter CT is ro000J, the decoders DC1 to DC2 are in the first position as shown in FIG. 3f.
Output “15” to specify the 6th lamp L1, (incense)
Derive.

Therefore, the 16th address of the memo IJME (corresponding to the lamp L15) is designated, and "1" (indicating lighting) is derived from this memory ME.

Therefore, the driver DR is energized at this timing,
Only the lamp L15 is turned on in cooperation with the rLJ output of the decoder Dc2 shown in FIG. 3f.

Next, when the counter CT is "ooo1", the decoders DC1 and DC2 move to the 15th block as shown in FIG. 3g.
rLJ output "1" that specifies the th lamp L14 (address)
4” is derived.

Therefore, the 15th address (corresponding to the lamp L14) of the memo IJME is designated, and "1" (indicating lighting) is derived from this memory ME.

Therefore, at this timing, the driver DR cooperates with the rLJ output of the decoder Dc2 shown in FIG. 3g to turn on only the lamp L14.

? Similarly, the counter CT is incremented and the corresponding lamp is lit each time. When the counter CT counts "1110", it is inverted by the inverters I1 to I4 and the OR time R output becomes l'0001J.

Therefore, as shown in FIG.
Derive the output "ding".

Therefore, the second address of the memo IJME (corresponding to the lamp L1) is designated, and "O" (indicating off) is derived from this memo IJME.

Therefore, the driver DR is not energized at this timing.

Therefore, no voltage from the driver DR is applied to any of the lamps LO""""L15.

Therefore, this timing is lamp L.

-L15 is turned off. When the counter CT is further incremented and reaches "111l", the lamp L is turned on.

is lit. Next, the counter CT is again r0 0 0
The state becomes 0J and the above operation is repeated.

In this way, the address of the counter CT and the memory M
Lamp L depending on the memory state of E.

-L15 is turned on or off in a time-division manner.

As described above, according to this embodiment, since a large number of lamps are lit and driven by time-division pulses, only one common lamp driver is required, and the configuration is simple.

Furthermore, since it uses a pulse lighting method, it consumes less power.

In addition, whether each lamp is on or off is individually stored in memory, and this memory is sequentially addressed by a counter, and the memory output is used to instruct (control) each lamp to turn on or off. Is it very easy to configure? The effect is produced.

FIG. 4 is another specific circuit diagram of the present invention.

In construction, this embodiment is substantially similar to the embodiment of FIG. 2, with the following exceptions.

That is, decoders DC1 and DC2 in the embodiment of FIG. 2 are used in common by the decoder DC.

The output of the decoder DC1 is given by inputting the address of the memory IJME, and the corresponding lamp L.

~ Connected to one end of L15.

This lamp L. The other end of each of ~L15 is connected to the output of the driver DR.

The operation of such a circuit is substantially similar to the embodiment of FIG. 2 and will be easily understood.

This embodiment has the effect that the circuit configuration is simpler than the embodiment shown in FIG.

As described above, according to the present invention, a large number of indicator lamps (L
A display drive circuit for controlling the lighting or extinguishment of an LED (ED) etc. can be obtained with a very simple configuration, and the power consumption for the display can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing the concept of this invention. FIG. 2 is a specific circuit diagram of a preferred embodiment of the invention according to FIG. FIG. 3 is a timing chart showing the operation of the embodiment of the present invention. FIG. 4 is a specific circuit diagram of another preferred embodiment of the present invention. In the figures, the same reference numerals indicate the same or equivalent parts, GT is a gate circuit, CT is a counter, OR is an OR circuit, DC1 and DC2 are decoders, ME is a memory, DR is a driver, Lo, L1 to L15, and Ln are It's a lamp.

Claims (1)

[Claims] 1. A plurality of display elements. Means for specifically addressing any one of the plurality of display elements, and an instruction to turn on or off a specific display element addressed by the specific addressing means. means for individually storing the lighting or turning-off state of the plurality of display elements based on the output of the specific addressing means and the output of the turning-on or turning-off instruction means; means for sequentially addressing the specific addressing means output and the sequential addressing means output in an OR manner; A display drive circuit equipped with means for controlling lighting or turning off of a display element.