JPS5836372B2 - Data Process Souch - Google Patents

Description

[Detailed description of the invention] (1) Field of invention The present invention relates to a data processing device.

The data processing device processes the data by
Functions to carry out the operation of a step.

Each step of an operation is called a "program."

Many but the simplest programs can be divided into multiple blocks.

Such blocks often consist of smaller blocks that are themselves smaller, so a complete program consists of many nested (combined) sets of blocks. .

Each program in a program consisting of many blocks.
When executing a block, errors may occur.

To reduce the possibility that such errors will affect the rest of the program, an acceptance test can be performed when one block is completed.

If the acceptance test is successful, the program will proceed to the next block, which may be an outer block that encloses the block that has just been successfully completed.

However, if the acceptance test is unsuccessful, the computer's memory device is restored to the state that existed immediately before entering the unsuccessful block.
It would be desirable to do so.

The acceptance test is a test to determine whether or not a specific program block is executable in that program, or to determine whether a specific program block is executable in the program, or to determine whether a numerical value assigned to a variable representing an information item included in a specific program block or the execution of a counting program. This is a test that is performed to determine whether or not the answer value obtained by If the test result is satisfactory, a "pass" signal is generated; if the test is unsuccessful, that is, the test result is unsatisfactory, a "fail" signal is generated. .

The program portion or program block commanding the acceptance test is included in and forms part of the program of the data process and is inserted after the particular program portion or program block to be tested.

The content of the acceptance test itself, that is, the test operating process, is determined by the program creator when creating a given program, and can take any appropriate form determined according to the content of the given program. .

As a simple example, if a given program block to be tested instructs a counting process to obtain a numerical answer, an acceptance test requires that the numerical value of the answer lies within that range. The upper and lower limit values that must be calculated are set in advance, and the answer value obtained by the commanded counting process is calculated based on these two values.
If the answer value is within the predetermined range, a pass signal is generated, and if the answer value is outside the predetermined range. If it exists out of alignment, a fail signal is generated.

As described above, the acceptance test attached to a large number of program blocks used in the data processing performed by the data processing device of the present invention, which will be described later, can be performed using any method known in the conventional data processing technology. can be used.

(2) Prior art and its problems One way to list the previous state is to copy the state of the first memory device (i.e. a regular memory device) before entering a new program block. equipment.

However, this requires that a copy be made to the set of nested program blocks in the first memory device before entering each successive nested program block; The memory device needs to be several times larger than the first memory device,
This is a significant waste of storage space.

(3) OBJECTS OF THE INVENTION An object of the present invention is to provide a program storage or recovery facility that does not require excessive storage space.

(4) Summary of the Invention The present invention takes advantage of the fact that in many program blocks only a relatively small number of information items change.

The invention provides, in addition to the first memory device, a second memory device in which only the previous state of the information item that changes during each program block is stored for each successive program block. Store program blocks along with indicators that identify them.

Apparatus is provided for generating a pass y' or "fail" signal upon completion of the acceptance test upon exit from each program block.

If a ``fail'' signal is generated, each memory device is operated to restore the state of memory it held immediately prior to entry into the failed program block. It will be done.

The device for restoring the state of the memory device includes a device for diskating each information item stored during the current program block from the first memory device; and an apparatus for transferring the state of an information item of a previous program block disked and stored in a second memory device from the second memory device to the first memory device.

If a ``pass'' signal is generated, each memory device is operated to advance the state of the memory device by descarding each unnecessary information item.

The device for advancing the state of this memory device is
The apparatus includes apparatus for discarding from the second memory device an information item local to at least the immediately preceding program block and an entry for that information item already existing in the immediately preceding program block.

(5) Overview of the Embodiment In practicing the present invention, one or more alternate blocks are used for execution in the event that the primary block fails. It is desirable to provide a block for

By doing this, after the 'fail' signal is generated, an alternate program sequence is provided and a second 'fail' can be achieved by simply repeating the failed program block. ”
The probability that a signal will be generated is reduced.

Preferably, a transfer device is provided for transferring a previous state of an information item from a first memory device to a second memory device when the state of the information item changes in each memory device during a current program block. establish.

Preferably, the transfer device is activated only for the first state change of the information item during the current program block.

For this purpose, a previous state of the information item is stored in the first memory device in order to indicate whether, during the current program block, a previous state of the information item has already been stored in the second memory device. Each information item included in the information item may include an indicator matching device.

The presence of such an indicator prevents the transfer device from operating.

Furthermore, both the first memory device and the second memory device may include a separator device for separating information items in preceding program blocks in the set of nested program blocks. preferable.

Delicious.

(6) Detailed Description of Embodiments Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

A computer program according to the invention for error recovery consists of a number of distinguishable error recovery operations that are divided into smaller programs.

A set of operations grouped to allow recovery from errors is hereinafter referred to as a "recovery block."

Each recovery block must include a primary block and an acceptance test, but may also include one or more alternate blocks above it.

Such a primary or alternate block may itself constitute or include a recovery block including at least one primary hook and an acceptance test.

FIG. 1 shows a recovery block I with an acceptance test I±.

This recovery block includes a primary block 1a and an alternate block Ib, where the primary block Ia has an acceptance test river t, a primary block Ila and two alternate blocks rivers b. and the Recovery Link River consisting of River C and River C.

Honorate block Ib includes two glue recovery blocks I and ■, recovery block l
is from acceptance test I1, primary block la and alternate block Ib, and recovery block ■ is from acceptance test IV.
t and a primary block Na.

In the figure, for convenience of explanation, the range of the recovery block is shown by a vertical double line, and the range of the brimary block and alternate block is shown by a single vertical line.

Each acceptance test forms part of a program that is called upon exit from the primary or alternate block.

This acceptance test determines whether the operation required of the recovery block is executed by enclosing the recovery block or by being accessed by the program that calls the recovery block.
Make the next decision.

There is one acceptance test for each recovery block that is called on exit from the primary block and also on exit of any alternate block if an alternate is requested.

If the primary block among the recovery blocks is rejected, the program executes the alternate block.

When this alternate block finishes, it submits its results to the same acceptance test, and once the acceptance test is satisfied, the results generated by the alternate block are used to advance the program.

If the acceptance test for this alternate block is again not satisfied, further tests are performed for other alternate blocks.

Thus, if all alternate blocks are tested and all blocks do not satisfy the acceptance test, all coverage blocks must be considered to have failed.

In this case, you should reject the enclosing block that calls the recovery block and try an alternate block to the enclosing block instead.

Each information item forming a program block may be a variable, in which case the various states of the information item are determined by the numerical values assigned to those variables.

Since the acceptance test is not in the primary block, it cannot access local variables in the primary or alternate blocks.

There is no reason to make the local declarations in an alternate block the same as the local declarations in the corresponding primary block.

If the acceptance test passes or does not pass,
By discarding local declarations created within a successful or failed block and bringing the systems into the same condition as when the block started, the alternate block may be able to perform a previous execution that the primary block cannot accept. Alternatively, it is possible to write in the conventional manner so that the design of the alternate block is not affected by changes to variable values that cause execution.

Therefore, when the alternate block is entered,
Exactly the same environment as the corresponding fly-y IJ-block that was entered is presented.

Once all operations in the primary block have been performed, the variables modified by the primary block are restored to their previous values.

The conditions necessary for such an error recovery system are described in the paper by Biy Randell, published in January 1974, Newcastle upon Tyne Institute of Computing, Technical Report No. 57, January 1974. It is fully described in the paper ``Research on the Reliability of Computing Systems''.

In the invention, which will be described below with reference to embodiments, means are provided for restoring variables modified in a primary or alternate block to their previous values with reasonable efficiency.

This is done by recording it in a separate storage means, hereafter referred to as a cache store.
The identity of the variable in the store is modified by a primary or alternate block that is associated with the variable value before the first modification.

These identities contain sufficient information to determine which variable's recorded value consists of this variable's address or virtual address.

In embodiments of the present invention, both the main store and the cache store are configured as a stack.

Because we only need to preserve the values of variables on entry to the recovery block, we do not need to preserve intermediate values for variables that change more than once in the recovery block, and we can save the indicators, or pool flags, in the main store. Displays whether the correct value is reserved in the cache store for each word in the cache store.

Figures 2 to 9 show the alternate block I of Figure 1.
3 shows the states of the main store and cache store during the performance of primary block Ia at the start of time b.

A special data rare value of a variable is illustrated.

FIG. 2 shows the situation before the entry of the recovery block ■.

Variable N is declaired and assigned the value 1.

By declairing this variable N, an address is assigned to the garden of the main store 10.

At this time, cache store 12 is emptied.

FIG. 3 shows a situation where primary block Ia is being executed.

The first of all stack marks 14 and 16 is placed in main store 10 and cache store 12, respectively.

These stack marks indicate the beginning of recovery blocks.

Assume that when running the program in primary block Ia, you declare transformation M and specify a value of 2.

This assigned value 2 is placed in the main store at the address of variable M above stack mark 14.

While running the program in block Ia, the variable N
is assigned a new value of 3.

The address and original value of variable N in main store 10 is inserted into cache store 12 at stack mark 16 or higher and the pool flag at the address of N in main store 10 is set (indicated by a star). .

Stack marks 14 and 16 indicate the start of the main store and catch region, respectively, associated with the recovery block.

Entries in either main store 10 or cache store 12 that are above the top stack mark should be activated in the currently executing block.

At the stage during the program execution in the primary block Ia, the recovery block (2) is interpolated.

FIG. 4 shows the situation in primary block Ila.

At the beginning of recovery block H, main store 1
0 and cache store 12 are set to stack marks 18 and 20, respectively, and the variable N stored in cache store 12 has no value above the top stack mark, so the variable N in the main store
The pool flag for is cleared.

In the primary block Ila, the variable J is declared and assigned the value 3.

This allocation value is placed in main store 10 above stack mark 18.

Next, referring to FIG. 5, primary block Il
In a, the value 4 is applied to the variable M.

Since the variable M was dayclaired before the start of the block being executed, the position of the variable in the main store 10 will be below the stack mark 18 that marks the start of the recovery block ■.

Both the address and original value of variable M are placed in cache store 12 above stack mark 20, the local value 4 of variable M is placed in main store 10, and the local value 4 in main store 10 is placed in cache store 12 above stack mark 20. The pool flag (indicated by an asterisk) for address M is set.

FIG. 6 will be explained.

During the execution of the program of primary block 11a, variable N is assigned the value M+1.

The address and immediate value of variable N is placed at the top of cache store 12, the local value of variable N is placed into main store 10, and the corresponding pool flag is set.

Next, FIG. 7 will be explained.

During execution of the program of primary block 11a, variable M is assigned a second local value of 6.

The pre-existence of a pool flag corresponding to the address of variable M in main store 10 indicates that the above operation is not the first allocation in this block.

The new value of variable M is therefore placed in the main store 10, but the previous value is not placed in the cache store.

(Otherwise, the previous value has already been entered.

) Such an entry would be prohibited by the presence of a pool flag at address 17, which of course remains fully set.

Figure 8 shows the acceftance of the recovery block ■.
A condition is shown in which test IIt is performed at the end of the Brimary block la, indicating that the test meets the conditions.

The stack of main store 10 is split at the top stack mark 18, which marks the start of recovery block H, so that local variable J is discarded.

When all flags are cleared, flags are set for variables that have entries between stack marks 16 and 20 of cache store 12.

These cache store entries were created in recovery block I before the start of recovery block I.

As a result, records of variables that were already cached when the currently executed NoriKaba IJ block 1 was entered are re-stored.

All entries in cache store 12 above stack mark 16 are then processed.

Enclose recovery block I variable (e.g. entry M, 2) variable i.e. stack mark 1
Addresses that indicate local to addresses above 4 are discarded.

An address corresponding to a variable of an entry that already exists in the top but one area of cache store 12 indicates that the variable is in the enclosed recovery block I.
(For example, entry N, 3) has already been marked, so it is discarded.

If further entries exist above stack mark 20, these entries are moved down into the top-but-one area of cache store 12, starting at the portion previously occupied by stack mark 20. It should be a continuous word.

Entries that are not de-carded, such as entry N,
For 1, the pool flags corresponding to the variables specified by the actual address are set to record that these variables are cached in enclosure recovery block I.

When a return is made from the currently executing recovery block to the enclosure recovery block I, the top but one area (above stack mark 16) of cache store 12 becomes the top area. become.

When the acceptance test it passes, the program exits from the primary block Ia and performs an acceptance test it. For example, suppose that this test is not unsatisfactory.

This mechanism must re-store the values of the variables even though block Ia has not been executed.

Since variable M is local to block Ia,
Discarded.

Variable N is modified in block Is and the previous value is recorded in the cache store.

This previous value of 1 is re-stored and the flag for variable N is cleared.

Stack marks 14 and 16 are main store 1
0 and cache store 12, respectively, and then the state of stores 10 and 12 shown in FIG. 9 is such that block Ia is not populated, just as shown in FIG.

If acceptance test it does not pass, the program moves to alternate block Ib.

This situation is illustrated in FIG.

Stack marks 14 and 16 are main store 1
0 and cache store 12.

Variable L is dayclaired and assigned the value 7, and the main
It is inserted into the store 10.

The operation then continues in the manner described for primary block Ia.

FIG. 11 shows a so-called cache mechanism that satisfies the above system.

The mechanism is adapted for use in conjunction with an information processing device, such as a central processor 30, and includes a main store 32 that is one word wide, and a main store word that is one bit wide and contains the same number of bits. It has a bit store and a cache store 36 wide enough to accommodate the main store address and main store data words in each catch store word.

Cache store 36 corresponds to cache store 12 of FIGS. 2-10, and main store 3
2 and bit store 84 correspond to main store 10 of FIGS. 2-10.

Each of stores 32, 34 and 36 has three control lines: a READ line that initiates a READ operation, a WRITE line that initiates a WRITE operation, and a line that allows the store to complete a previous READ or WRITE operation. It has a READY line to display what has been done.

Data is transferred between the central processor 80 and the various stores 32, 34, and 36 by a data highway 38, which includes a total of eight data paths of one word each.

Each data path, individual signals P, Q, E, S, F, U
, V and G, and these signals are made available to the six registers R, E, A, H, C and D and the register block G.

To explain FIG. 12, each register R, E, A, H
, C and D consist of one-word, dual-rank (d-type) registers 40.

The input terminals of this register 40 are connected to the output terminals of eight input multiplexers 42, each one word wide input terminal being connected to a respective path of the high-wire 38 (FIG. 11).

The operation of multiplexer 42 is controlled by signals on path 44 from control logic within the device.

This path 44 is connected to clock 4 by AND gate 46.
Generate a control wave combined with the signal sent from 7;
A strobe wave is generated for the register 40.

The leading edge of this strobe wave causes register 40 to read the input signal from multiplexer 42, and the trailing green portion of the strobe wave causes register 40 to generate this new state at its output terminal.

Explaining FIG. 11 again, the register block G is
Data highway 38 similar to multiplexer 42
In addition to this, it consists of five internal remistors CM, CN, CO, CP and CQ, and the signals SELECT CM, SELEC
It has a SELECT input terminal to which T CN, SELECTCO, SELECT CP and SELECT CQ are applied.

The selected register is set when data is being read into register block G, and displays its contents at the output terminal of register block G when data is read out.

Register CM is used to store the address of the highest stack mark in cache store 36;
This stack mark contains the address of the next stack mark below it.

The bottom stack mark contains the address to be identified.

Register CP contains the address of the empty word in cache register 36 immediately above the most significant word currently in use, ie, the next available address in cache store 36.

Register CN, which contains a copy of the previous value stored in register CP, ie, the last used address in cache store 36, is used for the next EXIT operation.

Register CO, which contains the address of a word in the top area of cache 36, is used for a third stage exit operation that scans the top area of the cache, which will be discussed next. explain.

Register CQ contains the address of the most significant word of the available cache register.

Register R holds the data word to be returned to central processor 30 and register E holds the address of the top stack mark in main store 32.

The top stack mark holds the address of the next stack mark, etc., and the bottom stack mark contains the address to be identified.

The A register holds the address of the current main store, and this register addresses the bit store as well as the main store and writes its contents to one of the cache stores.

The output terminals of registers E and A are connected to a comparator 48 which produces an output signal 'QY when the output of register A is greater than the output of register E.

Signal Y therefore indicates that the address of register A is higher than the top stack mark and therefore the variable addressed by the address in register A is local to the currently executing overcover block.

Register H holds data to be written into main store 32.

Register C holds the address used for cache stores.

The output terminal of this register is the control input FUN.
an increment/decrement unit 50 having
This control input FUN is connected to the input terminal of FUN.
receives one of four control signals and generates an output signal associated with input signal C as shown in Table 1.

Register D holds a portion of the data to be written into cache store 36, the remainder of which is in register A.

The output terminals of registers C and D are connected to a quality unit 52 which generates an output signal Z when the values in these two registers are equal.

Register R is provided with an interface to central processor 30, which consists of two data paths P and Q.

The P data path carries the address of the main store that the central processor wants to access, and the Q data path carries the data that the central processor 30 wants to store or put into the registers of the device.

The R data path, consisting of the output terminal of register R, carries data to be sent to central processor 30.

The control logic of this device will be described in detail later.

However, the control logic of the device and the central processor 30
The control signals that pass between the two will be described here.

This device has two
It has two control signals.

The signal READY indicates that the device has completed the operation requested by processor 30;
Signal ERROR indicates an error condition.

Central processor 30 is of conventional design and generates control signals that cause conventional storage means to perform READ and WRITE operations during the execution of instructions.

The processor is also provided with means for generating control signals that cause the apparatus shown in FIG. 11 to perform additional operations associated with the use of the coverage block and acceptance test in the program.

The device therefore receives one of thirteen control signals from the central processor to cause it to perform the next action.

i.e. READ action "to retrieve the value of a read word from the main store by a given correct address"; WRITE action "to record a new value in a variable"; entry temporary ENTR to the recovery block.
Y action; REVERSE operation required when the acceptance test rejects the block; EXI when the acceptance test passes and exits
T (exit) action; RESET (which causes the central processor to reset a new program to a state where it runs)
The control logic for the cache mechanism shown in FIG. 11 is as follows: This will be explained when explaining the state machine based on Table ■.

The state machine table shows each state into which the control logic can enter, and these states are numbered in the left column of the table.

The center column of the table shows the control signals that occur when the control logic is in each state.

Signals that control gate operations to each register are shown as P→A.

This means that data into register A is
and indicates that the corresponding multiplexer generates a signal to select the P input terminal.

The next state assuming control logic is shown in the right column of the representation.

If there is only one number in this column, this number indicates the assumed next state for every state.

If the control logic must enter each state depending on the presence or absence of a senseable signal, this is displayed as shown in the following example.

2→3, 2→2 This means that if signal 2 is true, the next state is state 3, and if signal Z is false, the next state is state 3.

The control logic moves from one state to the next at defined intervals of clock 47 (FIG. 12) such that when the switch is turned on, the control logic represents state l.

State 1 detects 13 control signals from the central processor and initiates predetermined actions.

State 2 is an error state and resets central processor 30.

States 11 and 12 perform read reactions.

The address from central processor 30 is gated into register A during step 11, main store 32 is read and its output is gated into register R during state 12.
He is gated in.

If main store 32 does not respond immediately, control logic returns to state 12 until a response is received.
Stay in.

State 3 is used for many actions that send a READY response to central processor 30 and return to state 1.

States 13-20 perform write actions.

States 13 and 14 read the bit flags of the word to be written and store this word in cache store 36.
When the contents must be held in register b, the contents are placed in register b.

State 15 determines whether the addressed word is local (next state 16) or already cached (
The next state 11) is this recovery
It is determined whether the block is allocated first (the next state 18).

State 18 records the previous value of the oud and the address of cache store 36, increments the value of the cache store pointer, and returns this value to internal register CP in register block G.

States 19 and 20 test the use of the last word of the cache store and can generate an error condition if an error exists.

States 21-24 place values into register block G's internal registers.

Steps 31-31 relate to data exchange with central processor 30.

Step 41 performs a recovery block entry operation.

States 41-42 set the limits of the top area of the cache in registers C and D.

States 43 through 46 are a loop counting up in register C, scanning the top area of the cache, reading the address portion of each cache entry, and reading the bits of each corresponding main store word.
Reset flag.

If there is one bit set entry in the top area of the cache, this resets all bit flags in the bit store 34, since the word only has a pit set.

States 41 and 49 write the current contents of internal register CM into cache store 36, forming the stack mark and leaving the top cache mark (
Generates new values for the addresses of the stack (contained in register CM) and the top of the stack (contained in register CP).

States 51-57 are used to cause the recovery block entry to perform a reverse operation and restore the value of the variable being modified in the recovery block after a failure of the acceptance test.

These states form almost the same loop as states 41-46, but cache store 3
The difference is that the cache values recorded in the top area of 6 are written back into the main store, erasing the effects of the erroneous block.

State 57 is the cache stack (register CP
(stored in ).

States 61-82 perform the exit operation after the acceptance test has passed and completed.

States 61-64 register CP for next use.
and register CM of the current entry in CM
and preserved in a copy of the CO.

States 61 to 64 are stored in register C in register CP.
Set the contents of M to indicate what will be on top of the stack when the top region is removed.

Other states are restricted from the three loops.

States 65 through 68 scan the top kitsch area from the top down and check all flag bits set in bit store 34 of all words cached in the top area of cache store 36. Unset the flag bit.

State 69 reads the cache stack mark between the top two areas of cache store 36, records it as the next cache marker in registers CM and D, and places it at the bottom of the second area of the cache. Display.

States 70-73 continue to scan the second region of the cache downwardly, scanning the flag bits of the word cached in the second region in bit store 34 (i.e., the flags that were removed in the previous entry operation; bit).

States 74-79 scan back up the top area of the cache to determine whether the item stored in this top area is local (indicated by signal Y) or has already been given to the second area (signal (indicated by an

Register CO holds a pointer that is one less than the address of the next entry to be examined in the top area, and register CN holds a pointer that is one more than the address of the top entry in the top area.

If the test in step 79 indicates that the cache entry is not local or not already cached at this level, then in steps 80-82 the address given by the top of the cache stack (register CP) is incremented next. rewrites the cache entry in the cache store 36 of.

The cached word's flank bit is also set.

This state machine was developed by T.C.Party (T. C. Bart
ee) and others, “Theory and Design of Digital Machines (T
heary and Design of Digi
It can be made into equivalent logic hardware as described in the technical book TAL Machine) J.

Apart from this, this state machine control is also controlled by S.
．． S. ``Microprogramming, its principles and applications'' by Mr. Husson)
ngy Principles and Practical
It can also be converted into a microprogram as described in e).

In another embodiment of the present invention, the current "recovery level" or depth of dynamic nesting of recovery programs, or in other words, the caches (separated by stack markers) currently in use. An additional register is provided to store a number indicating the number of regions (in which the area is located).

This register increments or decrements by 1 on each recovery block entry and recovery block exit.

The bit store 34 of the embodiment of the present invention shown in FIG. 11 has been replaced with a cover level store to store a recovery level for each value stored in the main store 32.

Once the variable is in the cache store 36, the recovery
Both the coverage level and the value held in the corresponding word of the level store are the history of the previous time the variable was put into the cache or the history of the time the variable was dayclaired as local. (i.e., storing the variable and its identity in the current top area of cache store 36).

When a variable is declared and assigned to a location in main store 32, it is then inserted into the corresponding portion of the coverage level store.

At any given time, the recovery block is incremented by one and a new mark is placed on the cache.

No action is taken on the data stack in the main store at this time.

When a new value is assigned to a variable, an investigation is performed to see if the variable coverage level in the main store is equal to the current coverage level.

If they are equal, the main store is populated with the new value and
No caching occurs and the recovery level store is immutable.

The variable glue coverage level does not indicate the current glue coverage level and a new entry is placed in the cache.

This cache entry is based on the recovery level
Consists of the previous value of the variable stored in the store, the future coverage level, and the identity.

The next time this main store receives a new value, the recovery level in the recovery level store will be equal to the current recovery level.

Entries in the top area in the cache are processed one by one during acceptance testing, and their values and recovery level fields are stored in the main store storage location and recovery level store specified by the identity. Each will be copied back.

The cache is retracted again, but does not contain the stack mark for this recovery block, and the current coverage level remains unchanged.

The current coverage level register is incremented by one after being accepted by the acceptance test.

Entries in the top area of the cache are processed one by one.

The coverage level in the coverage level store word corresponding to the true address in the entry in the top area of the cache is set equal to the current coverage level.

The entry is then discarded when the cache entry coverage level equals the current coverage level.

If not, the entry is moved down into the next cache area.

FIG. 13 is a block diagram of the apparatus according to the above embodiment using recovery levels;
This is equivalent to the block diagram shown in FIG.

The device shown in FIG. 13 is used in combination with an information processing device such as a central glossette 10.

The device includes a main memory 12 that is one word wide, a level store 14 that is wide enough to hold the number of recovery levels and contains as many words as the main store; - has a cache store 16 wide enough to hold the store address and level number;

Each of stores 72, 74 and 16 has three control lines: a READ line for initiating a READ operation, and a WRITE line for initiating a READ operation.
It has a WRITE line to initiate an operation and a READY line to indicate that the store has completed a previous READ or WRITE operation.

Data is transferred between central processor 70 and each store 72, 74 and 16 by data highway 18, which includes a total of ten data paths, each one word wide.

Each data path includes: - each signal P, Q, S, T, E, F
, U, V, W, and G and send these signals to seven registers R, A, H, E, K, C, D and the input terminals of register block G. , K, C and D are of the type shown in FIG. 12, except that the multiplexer has 10 inputs instead of 8.

The cache need, or variable, is determined by the relative value of the number of coverage levels currently in use and the number of coverage levels of the variable in the question, as described above.

Register E is used to contain the current recovery level number, and the value contained in this register indicates that the device is reset at the beginning of the program portion and that the recovery block entry or Reset to zero when automatically adjusted on exit.

Register K is used to contain the number of coverage levels for a variable in main store 72 or cache store 76 when a decision is made to cache the variable or maintain a cache entry.

The output terminals of registers E and K are connected to an equality unit 80, which is the same as unit 52 of FIG. 11, which outputs a signal when the values stored in registers E and K are equal to each other. Generate Y.

Similar to the device of FIG. 11, register block G has five
two internal registers CM, CN, CO, CP and CO
Contains.

The functions of these registers are the same as those of the corresponding registers in the register block of FIG. 11, and will become apparent from the detailed description that follows.

However, register CO is used auxiliary during reverse operations to hold the value of the current number of coverage levels.

Registers R, A, H, C and D perform the same functions as the corresponding registers in the device of FIG.

That is, register R produces the data word to be returned to the central processor 10, and register A is the main
Register H holds the address of the store, register H holds the data word to write to main store 12, register C holds the address to use for cache store 16, and register D holds the address to use for writing to cache store 76. Retain data.

The output terminal of register C is connected to the input terminal of an increment/decrement unit 82, which is the same as unit 50 of the apparatus of FIG.

This unit 82 has a human control FUN which receives one of four control signals and upon receiving the signal produces an output signal F associated with the input signal C shown in Table I.

Register D holds the data to be written in cache store 36; other data is placed in registers A and K.

The output terminals of registers C and D are connected to an equality unit 84 which generates an output signal Z when the values of registers C and D are equal.

An interface is provided between register R and central processor 70, which consists of two paths P and Q.

The P data path carries the image store addresses accessed by the central processor, and the Q data path carries data that the central processor 10 wants to store or put into the registers of the device.

The R data path formed from the output circuit of register R is
Contains the data being sent to the central processor 70.

The control logic of the cache mechanism shown in the attached drawings is shown in Section I.
The explanation will be based on the state machine shown in the table.

This state machine shows each state that the control port jitter can enter, and these states are:
The left column of the table is numbered.

The center column in the table shows the control signals generated when the control column is in each state.

The signal that controls gate-in to each register is P-A
It is expressed as

This represents gating data into register A and generating a signal that causes the corresponding multiplexer to select the P input terminal.

The right column of Table 1 shows the following states assuming control logic.

A number is shown in this right column, which is the assumed next state number in all cases.

When the control logic must enter different states depending on the presence or absence of a detectable signal, it is shown as follows.

2→3 z→2 This indicates that if signal 2 is true, the next state is state 2, and if signal 2 is false, the next state is state 3.

Similar to clock 41 (FIG. 12) of the pending patent application, control logic moves from one state to the next at regular intervals determined by the clock in conjunction with registers RG.

When the switch is turned on, the control logic is in state 1
It's supposed to be.

States 13 to 19 perform write operations.

State 14 reads the contents of the word to be written and its associated level number into registers D and K, respectively, if the word needs to be retained.

State 15 determines whether the word is to be kept (next state 17) or not (next state 16).

State 18 writes the new value of the word and the number of running levels to the main store and level store, respectively, and writes the previous value and its associated main store
Write the address to the cache store.

The cache store pointer gradually returns to register CP in incremental register block G.

States 18 and 19 test for use on the last word of the cache store and generate an error condition if there is an error.

States 21 to 25 are the values stored in the internal registers of register block G and the recovery level register E during execution.
This is related to the start of the process.

States 31-37 relate to data entering and leaving the central processor.

States 41-46 perform recovery block entry operations.

States 41 and 42 increment the number of recovery levels in progress and set the new values in registers E,K.

States 43 to 46 are internal register CM and register K.
writes the existing contents of the cache to the cache store, forming a cache mark and writing the top cache mark (which goes into register CM) and the top of the cache (which goes into register C
generates a new value for the address of P).

States 51-59 are used to perform the reverse operation and re-store the values of the modified variables in the recovery block after a failure of the acceptance test.

State 51 is the running recovery level register E.
The value of is held in internal register Co.

States 54-51 form a loop that scans the top area of the cache store.

For each word in the top area of this cache store, stage 1-56.
Read the address, its previous value and its previous recovery level into registers A, H and E, and write its previous value and recovery level into the main store and level store respectively.

State 58 is located at the top of the cache stack (
(stored in register CP).

State 59 stores again in register E the value of the recovery level in progress.

States 61-76 perform an exit operation after completion of the acceptance test.

States 61 and 62 gradually decrement the running recovery level register E.

States 63, 64 retain the entries present in register CP in register CN for the next operation.

States 65 and 66 read the back pointer from the top cache mark and place it in register CM as the address held by the top cache mark after the exit operation is completed.

State 61 is the cache after removing the top area.
Place the address that the top part of the store has in register CP.

States 68-76 form a loop that scans the top cache area from the bottom upward.

State 69 reads a word from the top cache area and sets the variable's main store address, its previous value, and previous recovery level in registers A, D, and K.

In state γ0, the previous recovery level in register K is compared with the recovery level that performs the recovery level exit operation, and if the number of recovery levels in registers K and E is equal (as shown by waveform Y), ), the cash entry under inspection is stopped (the next state 16).

If the number of levels are not equal, the cache entry must be moved from the top area to the second area.

Register CO stores the pointer in the cache currently being examined.
The address of the top entry is held in the register CN&t, and the pointer is held at a location in the top area that is one greater than the address of the top entry.

If the test in step 70 indicates that the recovery level of the entry under examination is not equal to the recovery level of the recovery block performing the exit operation, then states 72-74 are executed at the next incremental cache stack top (register Write the contents of registers A, f), K (eg, a copy of the cache entry under examination) into the cache store at the address given by CP).

In state 76, the recovery level of the recovery block performing the exit operation is written into the level store word associated with the variable during the cash entry processing operation, so that the net effect of the recovery block issued on the variable is Records the fact that it is the net effect of the allocation in the recovery block that contains that variable.

This state operating machine is described in the literature tt Theory a
ndDesign of Digital Machine
nes/t (T. C- Bartee et al., 19
See Equalization Logic Hardware, published by McGraw Bill, 1962.

Control of state operating machines is also described in the literature tt Mier
oprogamm-ing, Principle a
nd Practice //(S- S. Huss
The program may be changed to the micro program written by John On, published by Plaintice Hall in 1970).

When using the recovery level, as in the above embodiments, it is necessary to use a larger storage capacity, but it is possible to operate at a higher speed than in the system shown in Figure 11. be.

The apparatus has been described above in terms of assigning values of variables to storage devices.

In this case the above values were recovered simply by reversing the assignment.

Many program operations produce results other than the above assignments, ie, it is necessary to withhold results that may abandon the process operation and be intended for another operation.

Typical examples are operations involving file access, input/output interfaces, total X routines, fault tracing, and user-to-user interfaces.

The nature of such programs is such that error recovery is more complex than automatic reversal of assignments and must provide the program designer with the opportunity to specify appropriate recovery actions.

This problem can be solved by incorporating operations that require specific recovery into procedures (hereinafter referred to as recoverable procedures).

Although this recoverable procedure is not itself a recovery block with acceptance and alternation, it substantially includes one or more recovery blocks.

Such a procedure represents an own variable whose value is not automatically reset by the device according to the invention in case of an error, but can be stored again by a program in a recoverable glossary.

Multiple recoverable procedures can also be combined with each other to sever a set of own variables.

A recoverable glossary has three entry points.

First, a recoverable procedure is called into a recovery block, and the apparatus according to the invention causes the procedure to be entered at its "Save" entry point.

The purpose of the Save entry point is to allow the procedure to retain information that it needs to recover from in the event of an error in the calling recovery block.

The recoverable procedure is then advanced to a "normal" entry point, that is, an entry point whose purpose is to satisfy the functionality required of the glossary by its calling situation.

On the next display of a recoverable gross procedure in the recovery block, this device will cause the procedure to
Normal〃Enter at the entry point.

The third entry point is the so-called reverse, which is intended to enable information recovery.
It is the entry point and is held during the first imposition in the recovery block when the device according to the invention must destroy the recoverable glossary.

One side of the recoverable procedure will be described below with respect to the embodiment of the invention shown in FIG. It can also be used in the same way in combination with devices that operate on .

FIG. 14 shows a recovery block V that includes a recovery block ■ and a recoverable procedure ■.

The recoverable glossary in this case has an own variable W and another recovery block ■.

15-17 are the same as FIGS. 2-10, but show the state of main store 10 and cache store 12 at various points in recovery block V. FIG.

FIG. 15 shows the state of recovery block V at the beginning.

Stack mark 60. 62 are provided in the main store and the cache store, respectively.

In FIG. 16t, when the program enters the range indicating a recoverable procedure (2), a descriptor providing access to the procedure is placed on the main stack as the procedure's own variable W.

Of course, a recoverable procedure may have one or more own variables, in which case the names of all such own variables are inserted into the main store 10 at that point.

In the entry into the recovery block (2), stack marks 64 and 66 are further provided for the main store 10 and cache store 12, respectively.

In Figure 11, we first define the recoverable glossary ■ (
recovery block (■), it is found that the flag corresponding to the word in main store 10 containing the procedure's descriptor should be cleared, indicating that this procedure was not used within this recovery block. It will be done.

Therefore, the cache mechanism sets a flag corresponding to the descriptor (2) in the main store 10 and records the descriptor and its consistency in the cache store 10.

The recoverable procedure then obtains yet another "Save" area of cache store 12 and records its recovery information in this area.

A recoverable gross procedure enters its internal recovery block, which holds recovery information and performs the functions required by the procedure.

A subsequent call on the recoverable glossary in recovery block V finds the flag on the descriptor that has already been set.

The recoverable procedure is then entered through the normal entry point without any special action, but if the program enters another recovery block within the recovery block before recalling the recoverable procedure If so, the flag on that descriptor is cleared and yet another set of recovery information is recorded in cache store 12 to correspond to the new recovery block that requires recovery.

Upon successful exit from the recovery block, the descriptor and its associated save area in the cache store are treated by the cache mechanism like any other variable recorded in the cache store.

They are transported from one cache area to the next and remain on the main stack until they become local or a descriptor is present in that cache area.
Reset the descriptor flag.

In a recovery block within a recoverable procedure,
The glossary's own variables and variables in the save area in the cache store are considered non-local and are re-stored like any other variable on error.

However, if the acceptance test of the recovery block is satisfactory, then during exit from this recovery block, the above variables will become local in the next recovery block, regardless of their position in the main store 10. Therefore, its stored previous value is erased.

That is, exiting from recovery block ■ effectively makes the assignment to the own variable permanent, and subsequent recovery is possible only by the recovery program contained within the recoverable glossary.

However, assignments made to non-local variables by glossaries directly or through some parameter mechanism are processed normally and are therefore not made by the cache mechanism.

The top cache stack area is processed in the normal manner after an error.

Then, after the descriptor for the recoverable glossary is known, the cache mechanism invokes the procedure's reverse end point.

This reverse entry point invokes the recovery block, other glossary calls and recovery blocks, and other processing necessary to restore the own variables to their proper values.

The above description assumes that the various items of information are of the same size as the word length of the main store, but is of course also applicable where the items of information are shorter than a word.

However, in this case, all words are stored by uniform single unit assignment of information.

Furthermore, the invention is also applicable when the item of information is larger than a word, in which case more than one word needs to be stored in order to preserve the value of the information item.

The present invention can be implemented in the following manner.

(1) a transfer device for transferring the state of a previous information item from a first memory device to a second memory device when the state of the information item in the first memory device is caused to change during a current program block; A data processing apparatus as claimed in the claims.

(2) The data processing device according to paragraph (1) above, wherein the transfer device operates only for a change in the nutate of the first information item during the current program block.

(3) storing information in the first memory device to indicate whether a previous state of the information item stored in the first memory device during the current program block is already stored in the second memory device; comprising means for associating a respective indicator with each stored information item;
The data processing device described in item (1) above.

(4) The data processing device according to item (3) above, wherein the presence of the indicator inhibits the operation of the transfer device.

(5) for each of the first memory device and the second memory device, an information item in a previous program block and an information item in a subsequent program block in a nested set of multiple program blocks; The data processing device according to item (4) above, which is suitable for use in data processing that utilizes a nested set of a large number of program blocks, each of which is provided with a separator device for separation.

(6) The indicator also indicates the nesting depth of the current program block in the nested set of multiple program blocks, for data processes that utilize a nested set of multiple program blocks. The data processing device described in item (3) above, which is suitable for use as a data processing device.

7. A data processing device as claimed in claim 1, wherein the first memory device and the second memory device each comprise a stacked storage device.

[Brief explanation of the drawing]

FIG. 1 is a schematic explanatory diagram showing a part of the program structure according to the present invention, and FIGS. 2 to 10 are block diagrams explaining the states of the memory device at various stages during the execution of the program shown in FIG. 1. , FIG. 11 is a block diagram of a data processing device according to one embodiment of the present invention, FIG. 12 is a detailed block diagram of the device shown in FIG. 11, and FIG. 13 is a block diagram of another embodiment of the invention.・Diagram: FIG. 14 is a schematic diagram of the program structure according to the present invention; FIGS.
2 is a block diagram illustrating the state of a memory device at various stages of the illustrated program; FIG. R, E, A, H, C, D...Register, G...
. . . Register block, 30 . . . Central processor, 32 . . . Main store, 34 .
...Bit store, 36...Cache store.

Claims (1)

Claims: 1. A number of nested program blocks in which each program block is accompanied by an acceptance test before entry into a subsequent block or before being returned to an outer enclosing block. used in a data process that utilizes a set of information items, if necessary, if the state of the information items in this block changes during the duration of each program block, the state of the dominant information item at the beginning of this block. a data processing device operable to save the state covered by each of a plurality of information blocks of each program block immediately before the start of the block so that each program block can be restored; a first memory device for storing the current state of each information item of the block;
a device for storing indicators identifying each successive program block and indicating entry into and exit from each program block, and the previous state of each information item in each program block; a second memory device for storing an indicator of the program block in which the state occurred and an indicator of the program block in which the state occurred;
apparatus for generating a signal or a "fail"signal; and apparatus for discarding from a first memory device each item of information stored during the current program block; If the item includes a device for transferring the state stored in the second memory device to the first memory device for a program block immediately preceding the tasted program block, and if a "fail" signal is generated; If so,
a device for restoring the state of each memory device to the state immediately preceding its entry into the current program block; and at least an information item specific to the immediately preceding program block and an entry for it already present in the immediately preceding program block. comprising means for discarding an information item residing in the second memory device from the second memory device; and advancing the state of each memory device if a ゜゛pass'' signal is generated. A data processing device comprising: