JPS5836366B2 - Signal input channel failure detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal receiving apparatus, and more particularly to a failure detection method for an input channel of a periodically received signal.

Conventionally, measures to improve the reliability of serial signal transmission have been established in the field of data communications. There is a double inversion transmission in which "1" and "0" are inverted and transmitted.

However, these methods require data to be sent from the transmitting side to the receiving side at regular intervals, which makes the transmitting side unnecessarily complicated and costly.
It is also undesirable in terms of reliability deterioration due to complication.

Particularly in measurement control systems, it is difficult for the transmitting side to periodically transmit data even if the data is the same as the previously transmitted data.
It is preferable because it is simple in terms of circuitry and also because the status data of the object to be measured can be transmitted in real time.

In such a system, data is sent at a constant cycle, so it is possible to stop the transmission cycle sufficiently from the time constant of the measured point and send data redundantly, and on the receiving side, the received data is constant with the previous value. If the difference is less than a value, it can be determined that the data is reasonable, and that value can be rejected, or it can be determined that the data is rational only when the same data is received two or more times in a row.

In this way, while data errors can be detected relatively easily, if the transmitted data itself is interrupted, old measurement data that does not reflect the actual situation may be retained on the receiving side, causing incorrect control or display. This may cause some inconvenience.

The present invention proposes a method for reliably detecting such signal interruption without providing complicated devices on the transmitting side and the receiving side.

An object of the present invention is to detect, in a serial signal receiving device that periodically receives serial signals with address information, that old data is retained due to interruption of the input signal due to a failure, thereby causing an adverse effect on reliability. A method for realizing a high-performance serial signal receiving device is provided.

In the system according to the present invention, a serial signal having information regarding the received data storage address on the receiving side is transmitted.

The information regarding the storage address is directly interpreted as an address within the receiving buffer area in the receiving device, and
Data transmitted along with the storage address information may be stored in the address within the reception buffer area,
Alternatively, the information regarding the storage address is converted into an address within the receiving buffer area in the receiving device according to certain predetermined rules, and the data transmitted along with the storage address information is stored in the address within the receiving buffer area. There is also a method.

In any of the above cases, the system proposed by the present invention stores a portion of the received data in an auxiliary buffer area that is different from the receive buffer area address that is the object of the present invention. By temporarily storing and transferring the contents of the auxiliary buffer area address to the intended receiving buffer area, and processing and regularly inspecting the contents of the auxiliary buffer area address,
This method detects whether received data is input regularly.

FIG. 1 shows an example of the configuration of a device that implements the method according to the present invention.

The device includes a central processing unit CPU1, a system controller 2, an address converter 3, input channel signal converters 4, 5, 6, 7, a data bus 13, address buses 11, 12, and a request signal line 14a. ~14a.

The input channel signal converters 4 to 7 are determined by the number of channels of input channel signals, and may be one channel or a plurality of channels.

However, if the number of channels increases, the system controller 2, data bus 13, address bus 11, 12
, and considering the limitations due to the throughput of CPU1,
Care must be taken not to run out of processing capacity.

Input channel signals 15-18 are input to preassigned input channel signal converters 4-7.

The input signal is a serial signal and has the signal configuration illustrated in FIG. 2 on the time axis 22.

That is, the frame synchronization signal SYC19 indicating the start of one frame of serial signals is placed at the beginning, followed by address information 20 and data 21.

It is assumed that the frame synchronization signal 19 is assigned address information and a pattern that cannot occur in the data section in advance.

Hereinafter, after the frame synchronization signal ends, the input signal is distributed to the address information section and the data section at fixed time intervals.

FIG. 3 describes an example of a circuit configuration for converting a serial signal into a parallel signal and extracting an address information section and a data section.

The input channel signal 23 is input to the cyst register 40, and the first half and the second half of the cyst register are connected to the address bus 1.
2 and the data bus 13, respectively.

In this way, the serial human channel signals 15 to 18 are
The input channel signal converters 4 to 7 convert each address information section and data section into parallel signals, but when the reception of one frame of serial signals is completed, each input channel signal converter converts the request signal line 14a- d, the system controller 2 reports completion of reception, and signals are placed on the address bus 12 and data bus 13 in accordance with predetermined priorities for each input channel.

Needless to say, this timing is regulated by a synchronization signal.

This priority determination is made by the bus arbiter,
The construction of such parts is well known.

Signals on address bus 12 are translated by address converter 3 and coupled to address bus 11.

The address conversion method, for example, interprets the bit pattern of the address information section of the input channel signal as an address on the storage device in the address converter, interprets the data at this address as the converted address, and then transfers the data to the address bus 11. There are ways to put it on.

In such a system, since the address conversion method is usually determined in advance, it is preferable to store the address conversion information in a read-only memory to prevent a decrease in reliability due to destruction of the stored contents.

The purpose of the address converter 3 can be classified into two.

The first purpose is that the address information section 20 of the input serial signal has redundancy, and the address information section data is interpreted as it is as an absolute address or a relative address within the human output buffer area 8, and the input/output buffer area 8 is In order to prevent this situation, if storing in
It is conceivable to convert the address information section data in advance and store it in the human output buffer area 8 in a state with good memory efficiency.

Furthermore, a storage address may be determined in order to arrange input data so that it can be efficiently processed by a logic program stored in advance in the CPU 1.

The second purpose is directly related to the present invention and corresponds to part or all of the input/output buffer area 8.

The purpose is to set the contents on the storage device in the address converter 3 in order to generate an address different from the final target address in the input/output buffer area 8 for the pattern in the address information section 20.

The pattern of the address information section that does not allocate the final destination address in the crowded cover sofa area 8 differs depending on the degree of severity of input channel failure detection, and the more stringently the check is performed, the more the type is determined. It is preferable to increase it.

However, for example, in input channel data in which all combinations of predetermined address information part patterns each appear one or more times in one input channel data cycle, the predetermined address information pattern The address converter 3 may be set so that only one of them is stored in an address within the input/output buffer area that is not the final destination.

As another example, not all combinations of predetermined address information field patterns appear more than once in one input channel data period, but multiple combinations of the patterns The address converter 3 may be set so that at least one of the selected patterns always appears, and the plurality of patterns are stored at an address in the input/output buffer area that is not the final destination.

By combining the two examples described above with the method described below, it is possible to test whether or not each input data channel is out of order every channel data period.

FIG. 4 shows a processing flow of the method according to the present invention.

The processing flow is stored in the form of a program in the logical area 10 of FIG.

Since CPU 1 and input channel signal converters 4-7 share address buses 11, 12 and data bus 13, contention usually occurs.

To avoid losing input channel data, the CPU
One implementation method is to set the priority for the bus No. 1 to the lowest and give priority to the processing of the input channel signal converters 4 to 7.

Such priority determination including the CPU 1 is performed by a bus arbeater within the system controller 2.

The processing flow shown in FIG. 4 will be explained in detail below.

In this embodiment, the purpose is to detect failures for all input channels, and in processing block 24, pointers indicating each input channel are initialized.

In processing blocks 25, 26, and 27, the contents of the test buffer area corresponding to each input channel to be detected are sequentially checked.

In the test buffer area, an input channel data portion is stored by the address converter 3 for a predetermined input channel address information pattern.

The contents of the test buffer area are updated at regular intervals as long as there is no failure in the input channel.

In this method, a 1,0 pattern that cannot occur during normal input reception is intentionally set in the test buffer area, and after a period of one or more cycles of input channel data has elapsed, the
Read the contents of the test buffer area.

If the content remains unchanged, it indicates that the input channel has been out of order for one cycle or more, and a failure flag is set for the input channel to indicate that it is out of order.

If the content has changed, it can be determined that the content has been updated due to data being input via the input channel.

Therefore, the fault flag is reset for the input channel.

The above operations are indicated by processing blocks 25, 26, 27, 28 and 31.

After completing the verification of the test buffer areas of all input channels, if normal input data is stored in the test buffer area, the input data is stored in the input/output channel buffer area in processing block 29. The data is transferred to the final destination address of the CPU 1 so as not to cause any inconvenience to the subsequent logical processing by the CPU 1.

If normal input data is not stored in the test buffer area, the contents of the test buffer area are not transferred to the final destination address in the input/output channel buffer area, and the previous value in the human output buffer channel is stored. hold.

In processing block 31, the contents of the test buffer area are set for all input channels to values that cannot occur in actual input data, in preparation for input channel failure detection for the next cycle.

The fourth process needs to be started at regular intervals, and for the purpose of strictly testing the human channel, it is preferable to start it at a cycle slightly longer than l cycles of the input channel data.

In the processing block 25, it is determined that there is an input channel failure, but temporary data interruption of the input channel is not determined as a failure, and input is performed only when setting data A is continuously detected a certain number of times or more. If the input channel is unstable, it may be more practical to determine that there is a channel failure, and in that case, the processing block 25 may be changed to the processing described above.

Further, as an embodiment of the present invention, the address converter 3 simultaneously generates a test buffer area address and a final destination address in the input/output channel buffer area, and transfers the data portion of the input channel signal to the two addresses. It is also possible to adopt a method in which the data is stored in the buffer area for testing and the transfer by the CPU 1 from the test buffer area to the final destination address in the input/output channel buffer area is omitted.

However, in this method, the address converter 3 does not have one output per person, but has two outputs per person, which increases the complexity of the device. However, the fault detection of the input channel is the same as in the previous embodiment. Effects can be obtained.

An advantage of the present invention is that it provides a method for detecting a failure in an input signal channel in a serial transmission signal system without providing a complicated detection circuit, so that functional improvements can be realized without sacrificing economic efficiency.

Furthermore, although this method is designed with the use of electronic computers in mind, the load that must be borne by the central processing unit in order to realize this method is only the processing shown in Figure 4. 100μs per channel
This can be achieved as follows.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an example of the configuration of a device that implements the method of the present invention. FIG. 2 shows an example of the structure of the input channel signal in FIG. 1 on the time axis. FIG. 3 shows an example of a circuit configuration in which the input channel signal converter shown in FIG. 1 performs serial-to-parallel conversion of signals and separates an address section and a data section. FIG. 4 shows a processing flow of the input channel failure detection method according to the present invention. 1...CPU, 2...System controller, 3...Address converter, 4...
・Input channel 1 signal converter, 5... Input channel 2 signal converter, 6... Input channel N-1
Signal converter, 7... Input channel N signal converter, 8... Input/output channel buffer area, 9.
...Work area, 10...Logic area,
11...Address bus 1, 12...Address bus 2, 13...Data bus, 14...
...Request signal line, 15...Input channel 1 signal, 16...Input channel 2 signal, 1
7... Input channel N-1 signal, 18...
...Input channel N signal.

Claims (1)

[Claims] 1. A signal channel of a data receiving device that receives a serial signal in which an address signal and a data signal are transmitted in series for each channel, temporarily stores the received data in an auxiliary buffer area, and then stores it in a receiving buffer area. In the failure detection method, a specific signal pattern is set at a specific address of the auxiliary buffer for each of the plurality of channels, and the signal at the specific address is sequentially updated each time it is received using the address signal of the received serial signal. A method for detecting a fault in a signal channel channel, characterized in that the channel is determined to be faulty when the signal at the specific address at the time of reception and the time of current reception are the same.