JPH0155502B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to automatic data processing systems. Problems with the Prior Art 1 A long-standing problem in data processing technology has been that of developing data processing architectures that coordinate the transfer of information between two or more independent data processing systems. In the past, information exchange between data processing systems was accomplished by recording information from one system on a medium that could be accessed by a second data processing system. In commercial applications where high flow rates of information are required, the delays caused by such recording methods are undesirable. What is needed is a logical system architecture that provides dynamic exchange of information between independent data processing systems. Previous attempts to achieve the dynamic exchange of information between independent data processing systems have focused on the problems that can occur when data processing devices on different communication signal buses attempt to communicate with a telecommunications bus at nearly the same time via the same information path. It was not possible to counter the deadlock conditions. A further problem arises because interlinking logic control systems substantially affect the bus speed on these communication buses requiring the exchange of information. Additional problems arise in that special software configurations are required to coordinate logical operations between systems. Solution to Problem 1 by the Present Invention In the present invention, a link logic system between systems is provided, in which deadlock conditions include provision of parallel reversible transfer paths, dynamic assignment of priorities, and information exchange. This is overcome by providing bus cycle handling capabilities that continue the flow of information on the communication bus. Furthermore, no special software is required to enable any data processing device on one communication bus to communicate with the remote communication bus by means of an ISL device. In this way, the ISL device has software transparency so that the interlinked buses appear as one bus to any data processing device that communicates with the telecommunications bus through the ISL device. Each ISL device in the system communicates with a data processing device on one local communication bus and with any data processing device on the remaining communication buses for which the ISL device is configured to act as an information transfer intermediary. data word means stored in memory cell storage locations for regulating the transfer of information between. If the ISL device is to act as an intermediary for an unconfigured data processing device, the configuration data in the ISL device must be changed. Since bus cycle requests may continue at any time during operation of an ISL device, this ongoing request must be satisfied to avoid a break in the flow of communication bus information. Additionally, commercial applications require ISL devices to return to an on-line logic state within the shortest possible time. The present invention relates to a logic control system in which an ISL device can be converted from an on-line logic state to a halt state in which ongoing bus cycle requests are met but other bus cycle requests are ignored.
The ISL device can then selectively reallocate communication bus resources as needed to be reconfigured.
This ISL equipment can then be brought back online within a time frame compatible with commercial application requirements. Problems with Prior Art 2 Another long-standing problem in data processing technology is
The problem is the avoidance of deadlock in data processing systems consisting of multiple communication buses, each of which is electrically interfaced with an ISL pair device that interfaces with the CPU, peripheral controllers, and storage devices. In environments where there are many CPUs on a local communication bus attempting to communicate with resources on one remote communication bus, lower priority CPU bus cycle requirements may be given higher priority before a response from a remote bus is received. Interrupts by the CPU in the ranking are possible. Solution to No. 2 According to the Present Invention The present invention provides a logical system for rescheduling higher priority CPU requests until a lower priority CPU receives a response from a remote bus. Otherwise, lower ranking CPUs may be denied access to the remote bus for an indeterminate period of time. Problems with the Prior Art 3 In the past, information exchange between data processing systems was accomplished by interlink logic that was limited to serial bit transfers and multiplexed bidirectional transfers. Additionally, the intersystem logic that coordinates exchanges between communication buses is synchronized to bus activity, thereby substantially influencing bus cycle speed. Solution to Problem 3 by the Present Invention The present invention provides a method for communicating with local and remote ISL devices in each of the local and remote ISL devices, in which the communication between the ISL devices is not synchronized and the information transfer through the ISL devices is bidirectional and simultaneous. The present invention relates to a communication control system between systems. Problem with the Prior Art 4 In prior art systems, a data processing device on the local communications bus that issues a request to the telecommunications bus would halt the flow of information on the local bus until a response is received. Ta. One proposed solution involved a software control system in which the data processing device was given a response that caused it to release the local bus. Upon detection of the occurrence of a response from the remote bus, the software signals the data processing device to update its request to receive the remote bus response. Software intervention substantially affects communication bus speeds and eliminates the transparency that intersystem link (ISL) equipment would otherwise have. The ISL device therefore appears as a control device on this local bus. Solution 4 according to the present invention In the present invention, a data processing device on a local bus that issues a request to a remote bus is placed on standby (WAIT). That is, given an undefined answer, the data processing device
When the cycle is obtained, issue the request again.
Meanwhile, other information flows may occur on this local bus. Furthermore, the original request from the data processing device is serviced by the logic control system embodying the invention during the period when the device is waiting without affecting the flow of information on the local bus. Problems with the Prior Art 5 Prior systems have attempted to coordinate the exchange of information between communication buses by satisfying requests sequentially in the order in which they occur. This undesirable storage transfer delay occurs when a storage request must wait for a non-storage response. Solution to No. 5 According to the Invention The present invention is directed to a logic system in which bus requests are received in any sequence and identified by bus speed. Transactions can then be prioritized to provide optimal performance for regulating the transfer of information between communication buses without substantially affecting bus speed. Specifically, ISL transactions are identified and information from one bus is loaded into dedicated register locations at bus speed. ISL transactions can then be satisfied in parallel. Store transfers are separated from non-store transfers to avoid unnecessary delays that occur when store transfers wait for a response from a relatively slow non-store data processing device. Problems with the Prior Art 6 In the design of information processing systems, the central processing unit and the storage device are given separate logical addresses. Prior art systems were limited to transferring information only between two communication buses. Furthermore, address displacement was limited to a range of contiguous addresses provided to storage and non-storage partners. Such prior art devices further add displacement to one local address for communication with a remote data processing device. The process of adding displacements to local addresses is time consuming and thus substantially affects bus speed. Yet another limitation of prior art systems arises from the fact that one constant displacement value is attached to a variable range of addresses. If an address outside the current remote address range is accessed, the current address range cannot be shifted because of the constant displacement. Therefore, this range must be expanded and
As a result, more addresses than necessary are presented to the data processing device on the requesting side. Solution to Problem 6 According to the Invention In the present invention, multiple address translation ranges can be provided to enable communication between two or more communication buses, and data processing devices on one bus can be connected to an interconnected bus. Translation logic is provided that allows access to a clearly contiguous address range that encompasses all data processing devices in all of the data processing devices. Furthermore, in providing storage translation, local addresses are replaced instead of modified to overcome the speed limitations of prior art systems. The environment in which the present invention operates can thus be described as a data processing system having multiple communication buses, where each bus connects storage devices, peripheral controllers, intersystem links (ISLs), and so on. Interfacing central processing unit (CPU)
provides a common communication path for multiple data processing devices, including Each bus is in electrical communication with an ISL device, and the ISL devices are in further electrical communication in pairs to provide intersystem communication between data processing devices on different communication buses without interfering with bus transfer rates. Problems with the Prior Art 7 Problems arise when using prior art solutions for validation testing of stored and non-stored data and control paths in ISL devices. If one local and one remote ISL device of a pair of ISL devices that electrically communicates one local bus and one remote bus of multiple communication buses is to be tested offline, the local and remote communication buses Information can no longer be exchanged. If ISL equipment is tested on-line and information is exchanged between these buses, a similar problem exists where the local and remote bus partners are used only for test operations. At the same time, other information flows on each bus stop. Additionally, this test mode operation may be affected by requests received by the remote ISL device from other data processing devices on the remote bus. SUMMARY OF THE INVENTION The present invention provides that the effects of stored and non-stored data and control logic of local and remote ISL devices do not affect the remote bus cycle rate, i.e., on-line testing can be performed using remote bus resources. Provide a logical control system. Additionally, the remote ISL device will ignore communications received from any other data processing device on the remote bus. Problems with the Prior Art 8 Yet another long-standing problem in data processing technology has been the problem of detecting errors in the transfer of information regarding undelivered or nonresponsive destination devices. In the past, communication buses in systems having two communication buses, each providing a common information path to multiple data processing devices, would stall if a deadlock condition occurred as a result of an unresponsive destination device. We were able to. Manual restart is required to overcome transfer errors. Software systems have also been used to indicate the occurrence of such transfer errors. One more
Even if a CPU on one bus executes software and flags an error condition, the assistance of this software is lost when the bus becomes deadlocked. After that, no indication of the source of the error is obtained. Another idea was to put a CPU in the interlink logic that contained error detection software. This alternative would not only destroy the transparency of the interlink logic, but would also unduly complicate the interlink logic. In this loss of transparency, the interlink logic becomes visible as separate controllers on one bus. This resulted in a substantial compromise in transfer speed. Another problem has arisen in systems that interlink multiple communication buses in that special software is required for each communication bus to enable the transfer of information through the interlink logic. A common drawback of most error detection systems in data processing environments is that errors are only displayed and not removed. SUMMARY OF THE INVENTION The present invention relates to an error detection and removal logic system that is incorporated into each ISL device without the need for any special communication bus software or firmware. An error detection logic system in a local ISL device communicating with one local bus and with a remote bus by a remote ISL device detects and indicates the presence of an error when an error occurs at the source of the local bus. Because the combination of possible hardware and software errors is anticipated, these errors are detected before they cause a destructive deadlock on a bus. Upon detection of the error, the detection system issues a response to the local bus to complete one local bus cycle;
This frees the bus for further information transfer. SUMMARY OF THE INVENTION In a preferred embodiment, a plurality of communication buses coordinate the transfer of information between one or more communication buses, each bus providing a common information path for a plurality of data processing devices including a plurality of electrically interfacing CPUs. An intersystem link (ISL) logic device is provided for use in a data processing system having an intersystem communication link. In particular, the asynchronous information acquisition logic system occurs on a continuous local bus at bus speeds and is stored in a separate one of multiple dedicated file locations to coordinate the transfer of multiple parallel bus communications of different types. 2
Capture the progress information. An information decoding logic system in electrical communication with the information acquisition logic system identifies the binary information to be further processed by the ISL device at substantially bus speed. Information conversion logic in electrical communication with the information acquisition logic system selectively converts local address information to remote address information and remote address information to local address information at substantially the bus speed. A logic control system, in electrical communication with the decoding and translation logic system and responsive to the information acquisition logic system, selectively reconfigures the ISL devices to handle informational and non-informational read and write requests, CPU-to-CPU interrupts, and control multi-directional transfer of information, including interrupts, from peripheral control devices to the CPU via ISL devices. An intersystem link (ISL) device architecture is a link between a local communication bus and data processing equipment, including peripheral controllers, a central processing unit, and an ISL device that electrically communicates with multiple communication buses in a data processing system. To enable the transfer of information
The ISL devices are selectively reconfigurable, and the data processing device is such that each of the plurality of communication buses is in electrical communication with an ISL device, and the ISL devices are in electrical communication in pairs. In particular, a cycle control logic system that is responsive to a communication bus and responsive to one output control command from a CPU in electrical communication with one local communication bus is configured to have a cycle control logic system that is responsive to a single output control command from a CPU that is responsive to a communication bus and that is in electrical communication with a local communication bus. Convert the addressed ISL device. In the stop logic state, the ISL device responds to ongoing communications bus requests but prohibits other communications bus responses. A programmable storage logic system in electrical communication with a local communication bus has storage cell locations for storing binary encoded information received from any of the plurality of communication buses, thereby providing information between the plurality of communication buses. information transfer. A configuration control logic system responsive to the cycle control logic system modifies binary encoded information stored in selected ones of the storage cell locations of the programmable storage logic system. Such modification operations occur in accordance with configuration data received from the CPU, thereby effecting dynamic reallocation of data processing system resources among the plurality of communication buses. A logic system in an Intersystem Link (ISL) device controls the access of multiple central processing units (CPUs) on a local communication bus to a remote communication bus to avoid deadlocking the CPUs. In particular, a logical storage system of a local ISL device in electrical communication with a local bus stores binary encoded information received from said local bus at bus speed. Local ISL
A bus cycle comparison logic system in electrical communication with the logic storage system on the device is connected to a remote ISL
Responds to ACK, NAK, and WAIT signals received by the device from the remote bus. The bus cycle comparison logic system indicates occurrences of equivalence and non-equivalence between binary encoded information stored in the logical storage system and binary encoded information on the local bus. For a local ISL device, a mode control logic system in electrical communication with both the logical storage system and the remote ISL device is provided by the local bus and the remote bus in one ISL configuration mode.
Remember the NAK retry bit signal. This will indicate the presence of multiple CPUs on the local bus.
The NAK logic control system responds to the non-equivalence indicated by the bus cycle comparison logic system and issues a NAK signal to multiple CPUs on the local bus that have a higher accelerator priority than the lowest priority CPU priority. in response to the NAK retry bit signal. This results in the lowest ranking
The CPU is given access to the remote bus.
A logical communication system in an Intersystem Link (ISL) device coordinates the exchange of information between communication buses, but on each communication bus the flow of information continues at bus speed and no further information transfer between communication buses is possible. Handling continues via ISL equipment that electrically interfaces with the bus. In particular, a logical storage system in electrical communication with a local communication bus stores binary encoded information received from the local bus at bus speed, thereby completing information transfers over the local bus within one bus cycle period. do. The write selection logic control system in the local ISL device is responsive to the BSDCNN signal from the local bus and controls the logical storage system with two full active bit signals indicating the busy and active states of the storage system, respectively. Load with hex encoded information. The logic control system also issues a WAIT signal to the local bus to allow further flow of local bus information. A cycle-aware logic system in the local ISL device is responsive to binary encoded information received from the local bus and is responsive to binary encoded information received from the local bus to communicate with the remote ISL device to a non-storage data processing device on the telecommunications bus to which the binary encoded information is to be transferred.
Provides channel hit bit and memory hit bit signals that respectively identify the device. Additionally, the type of ISL activity required is identified.
The local cycle generation logic system in the local ISL device generates the local ISL in response to the activity bit, channel hit bit, and memory hit bit signals.
Initiate local RRQ cycles and local transfer cycles at the device. This transfers binary encoded information from the logical storage system to the remote ISL device. The remote cycle generation logic system at the remote ISL device is responsive to the binary encoded control signal from the local cycle generation logic system to initiate a remote RRQ cycle at the remote ISL device to receive binary encoded information from the local ISL device. The remote cycle generation logic system also signals the completion of the local transfer cycle to the local ISL device, thereby arranging further local cycles at the local ISL device. A bus cycle generation logic system at the remote ISL device issues a BSDCNN signal to the remote bus and responds to the remote RRQ cycle to provide binary encoded information to the remote bus. The remote response logic control system in the remote ISL device transmits ACK, NAK, and WAIT signals received from the remote bus to the local ISL.
Transfer to device. The logic comparison system in the local ISL device compares the ACK, NAK, and WAIT signals with the
Respond to the occurrence of an idle condition on a local ISL device. The local comparison system detects an ACK, upon the occurrence of equality between the binary encoded information stored in the logical storage and the binary encoded information on the local bus.
Give NAK and WAIT signals to the local bus.
This identifies previously issued commands from data processing devices on the local bus. A logical system is provided for identifying dedicated locations in a file register of a local intersystem link (ISL) device, where each dedicated location is responsive to requests made by a data processing device on a local communications bus. to view ISL transactions. This allows prioritization of ISL transactions in response to requests received by the remote ISL device from either the local communications bus or the remote communications bus at bus speed. Furthermore,
Information may be transferred between multiple communication buses in a data processing system, where each bus connects multiple data processing devices including a central processing unit electrically interfaced with storage devices, peripheral controllers, and ISL devices. each bus is in electrical communication with one ISL device;
The devices are further in electrical communication in pairs. In particular, a logic control system responsive to binary encoded information received from a local bus and remote ISL devices
The operation of local ISL devices is controlled by local identification of multiple ISL transactions during one bus cycle. A first programmable storage logic system responsive to the logic control system has a local
The ISL device stores a first binary bit signal indicating those storage devices on the remote bus to indicate the occurrence of either a store request or a retry request. A second programmable storage logic system responsive to the logic control system indicates, in its one cell location, those non-storage data processing devices on the remote bus to which the local ISL device should indicate the occurrence of a retry request. A second binary bit signal is stored. A logical storage system in electrical communication with the local bus and responsive to the logical control system has a plurality of locations each dedicated to one of the local ones of a plurality of ISL transactions. The binary encoded information received from the local bus may be stored in a dedicated retry location selected by the logic control system responsive to the first binary bit signal. This information is further requested by the logic controller in response to the second binary bit signal, the store reference signal and the bus lock signal to request storage of the dedicated location and to request a retry. Can be memorized in any of the things. Additionally, this information is stored in the dedicated location retry responsive and storage responsive, which location is connected to the local second half bus cycle (BSSHBC);
selected by the logic control system in response to both a storage response code generated at the remote ISL device during one remote storage request cycle and sensed by the logic control system in response to the BSSHBC signal. The usage conditions at the filled locations of the dedicated locations are thereby signaled to the logic control system. The conversion control logic system, which is responsive to binary encoded information received by the remote ISL device from the local bus and the remote bus, is sensitive to memory hit bit signals and channel hit bit signals. This logical system includes a storage address translation logic system, a logical storage system, a destination address translation logic system,
Controls the operation of the source address translation logic system and channel hit bit storage. In particular, the storage address translation logic system is responsive to a binary address code received by the local ISL device from the local communication bus and provides a storage valid bit signal identifying the type of ISL activity requested. The logic system further provides translated storage address codes to address storage devices on the remote bus or provides translated storage address codes to non-storage data processing devices on the remote bus. A logical storage system in electrical communication with the local bus stores binary encoded information received from the local bus at bus speed, thereby completing information transfers over the local bus within a bus cycle period. The CPU destination address translation logic system is responsive to the logical storage system and provides a translated CPU address code to address or provide an address code to a remote CPU on a remote bus. A CPU source address translation logic system electrically communicates with the remote ISL device on the remote bus and translates the CPU address code to identify the remote CPU on the remote bus to the data processing device on the local bus. Channel hit bit storage logic in electrical communication with the logical bus provides channel hit bit signals to non-storage data processing on the remote bus to which the local ISL device is to forward binary encoded information received from the local bus. Identify these addresses of devices. A local logic system in the local ISL device is responsive to the second locally encoded information received from the local bus and responsive to a local hit bit signal generated by a local hit bit generation logic system in the local ISL device. . Local control logic system is local
Initiates a local request cycle and a transfer cycle at the ISL device and transmits the first locally encoded information to the remote
Transfer to ISL device. A remote cycle select logic cycle at the remote ISL device ignores requests by the remote data processing device in response to the test mode bit of the output control command received from the local bus.
The remote cycle selection logic system enables detection of remote ISL address signals and remote middle bit signals generated by the remote ISL address generation logic and remote middle bit generation logic, respectively, at the remote ISL device. The remote control logic system at the remote ISL device is responsive to the local request cycle of the local ISL device and the remote cycle selection logic system to initiate a remote request cycle at the remote ISL device and transfer a remote ISL address signal to the remote bus. do. The remote control logic system further initiates a local request cycle of the remote ISL device upon detection of the remote medium bit signal, stores the remote ISL address information received from the remote bus in the remote logic storage system, and stores the remote ISL address information received from the remote bus. locally encoded remote binary encoded information
Transfer to ISL device. For these non-memory request cycles, the local
The storage reference signal generation logic in the ISL device is
A storage reference signal is issued to the local bus during a remote RRQ cycle initiated at the local ISL device by the local control logic system in response to a remote RRQ cycle at the remote ISL device. This transfers the remote binary encoded information to a local storage device in electrical communication with the local bus. The channel address translation logic system in the local ISL device, responsive to the test mode bit and the remote RRQ cycle of the local ISL device, translates the address bits of the remote binary encoded information into storage address commands provided on the local bus. Convert. Reading of the second locally encoded information from the local storage is thereby possible. The storage control word inhibit logic system at the remote ISL device converts the storage response (MRS) control bit of the storage control word generated by the local ISL device to a logic one in response to a remote RRQ cycle at the local ISL device. The remote write selection logic system is located in the local ISL device and is in electrical communication with the local bus. Upon sensing the MRS control bit, the remote write selection logic system signals the local control logic system to initiate a local RRS cycle at the local ISL device. The second of the buses received from the local bus
half bus cycle (BSSHBC) and the second locally encoded information received from the local storage device is thereby routed to a retry response (RRS) logic path in the local ISL device. The remote address selection logic system at the remote ISL device receives the second local binary encoded information and the remote address selection logic system at the remote ISL device generated by the remote control logic system in response to the local RRS cycle at the local ISL device.
Respond to RRS cycles. For storage request cycles, the local ISL device generates a remote MRQ cycle and, in response to the BSSHBC from the local storage device, generates a local MRS cycle to transfer data to the remote ISL device as in non-test mode. do. The remote address selection logic system selects remote ISL address information stored in the remote logical storage system for identification by the remote control logic system upon application to and receipt from the remote bus. This allows remote control logic systems to
Initiating a local cycle at the ISL device, the local control logic system initiates a remote response cycle at the local ISL device to transfer the second binary encoded information to the local bus. In Intersystem Link (ISL) devices, a timer control device is provided to detect and isolate information transfer deadlocks between communication buses. In particular, a local communication bus that is in electrical communication with a local communication bus.
The local logic control system in ISL equipment is
Control the flow of information through ISL equipment. A bus timer logic system responsive to the first BSDCNN signal from the local bus generates a NAK response if a response to the first BSDCNN is not received from the local bus within a first predetermined period of time. A response in lieu of the expected response from the local CPU in electrical communication with the local bus is provided to free the local bus for further transfer of information. ISL
The MYDCNN timer logic system is generated by a local ISL device in response to a bus cycle request received from a telecommunications bus by a remote ISL device in electrical communication with the local bus. Responding to requests made to a data processing device. The MYDCNN timer logic system provides NAK responses to the local bus and remote
generating a timer control signal for the ISL device;
The expected response from the local data processor is the second
signals the expiration of a second predetermined period to the remote bus if not received within a period of time. This completes one local bus cycle and any CPU on the local bus is prohibited from detecting the expiration of the second period. A store cycle timer logic system is configured to time a store read request operation during a store read request operation initiated by the local logic control system in response to a bus cycle request from a requesting data processing device in electrical communication with the local bus. Responds to local MRQ cycles. This storage cycle timer logic system is
MRS cycle locally within a third predetermined period
Generates one status bit for the local logic control system if not started in the ISL device. This allows the local logic control system to
Initiating a remote MRS cycle at the device to complete the bus cycle at the local ISL device and indicating an invalid store response to the requesting data processing device. A local system in electrical communication with a local bus and initiated by a local logic control system in response to a bus cycle request from a requesting data processing device.
A retry timer logic system responsive to local RRQ cycles at the ISL device sends a retry status bit to the local logic control system if an ACK or NAK is not received from the remote ISL device within a fourth predetermined period. and generate it. ACK by the local logic controller to the requesting data processing device;
Generation of NAK or WAIT responses is inhibited and the local bus is freed for further information transfer. An I/O timer logic system in electrical communication with the local bus causes the local
Respond to RRQ cycles. Local RRQ cycles are generated by a local logic control system in response to a bus cycle request from a requesting data processing device. The I/O timer logic system generates an I/O status signal to the local logic control system to notify the local ISL if the expected response is not received from the remote bus within a fifth predetermined time period.
Initiate a remote RRS cycle at the device. This causes the local logic control system to initiate a remote RRS cycle at the local ISL device, complete one bus cycle at the local ISL device, and indicate an invalid response to the requesting data processing device. The local bus control logic in local ISL equipment that is in electrical communication with the local bus is
In response to the BSDCNN signal, the local ISL device identifies those bus cycle requests received from the local bus to which it should respond. The local cycle control logic system is responsive to activity bit control signals from the local ISL device and the remote ISL device, controls the transfer of locally encoded information received from the local bus and the remote bus to the remote ISL device, and controls the transfer of locally encoded information received from the local bus and the remote bus to the remote ISL device. ISL
Controls the transfer of remote binary encoded information received from the device to the local bus. Local in response to local cycle control logic system
ISL interface storage logic system
Stores local binary encoding information for transfer to the ISL device. This frees up the local cycle control logic system to receive remote binary encoded information from the remote ISL device, providing simultaneous bidirectional information transfer. Remote ISL that communicates electrically with remote buses
A remote bus control logic system at the device responds to the BSDCNN signal on the remote bus. Upon detection of this signal, the remote bus control logic system identifies those bus cycle requests received from the remote bus to which the remote ISL device should respond. A remote cycle control logic system responsive to activity bit control signals from the local ISL device and the remote ISL device controls the transfer of remote binary encoded information received from the remote bus to the local ISL device. The remote cycle control logic system further routes locally encoded information received from the local ISL device to the remote bus via the remote ISL device. A remote ISL interface logic storage system is responsive to the remote cycle control logic system and stores remote binary encoded information transfers to the local ISL device. This frees up the remote cycle control logic cycle to receive local binary encoded information from the local ISL device, providing simultaneous bidirectional information transfer. DESCRIPTION OF EMBODIMENTS Arrangements according to the invention will be explained in the following description of embodiments with reference to the accompanying drawings. FIGS. 1-3 are functional block diagrams illustrating the architecture of four systems embodying the present invention. FIGS. In FIG. 1, two intersystem link (ISL) devices 10 and 11 are shown, each providing an interface between two data processing systems having a communication bus. Each communication bus interfaces storage devices, peripheral control units (PCUs), and central processing units (CPUs) in priority order. In particular, the ISL device 10 is in electrical communication with a storage device 13, PCUs 14 and 15, and a CPU 16 via a communication bus 12. The ISL device 11 has a storage device 17,
It is electrically connected to the PCUs 18 and 19 and to the CPU 20 via a communication bus 21. A detailed disclosure of this communications bus system is provided in U.S. Pat.
Found in the issue. The system architecture shown in FIG. 1 allows devices on each communication bus to communicate with any communication bus. For example, CPU 16 may communicate with devices 10 on communication bus 12, or ISL devices 10, 11 may communicate with devices on communication bus 21. A unique feature of this system is the ISL's translatable storage feature, described below.
As a result, storage devices 13 and 17, and CPU 1
6 and 20 can have the same address. Peripheral controllers may also have the same address unless they are shared. FIG. 2 shows a slightly different system architecture in which multiple ISL devices interface with the same communication bus. This provides multiple communication paths from one communication bus to another. Furthermore, all PCUs may be connected to one communication bus, and access to these PCUs is obtained by ISL devices that interface with said communication bus. Each of ISL devices 30 and 31 is electrically connected to a communication bus 32. The ISL device 30 further includes an ISL
Device 34 allows communication with one communication bus 33 . Additionally, ISL device 31 can communicate with communication bus 35 via ISL device 36. The ISL device 36 further includes:
Can communicate with communication bus 35 and ISL device 30, 3
Communication buses 32, 33 can be communicated via interfaces with 1, 34. Similarly, ISL device 3
4 is a communication bus 33 and ISL devices 30, 31, 3
communication bus 32 via an interface with 6
You can contact 35. Therefore, any device on any of the three communication buses can communicate with any other device in the system of FIG. The CPU and memory have the same addresses as above and are time-sharing possible. However, PCUs have the same address even if they cannot be time-divided. In FIG. 3, the architecture of the system with redundant communication paths is shown. For example, communications bus 40 may communicate with communications bus 41 by communications link 42 having a pair of ISL devices 42a, 42b, and communications links 43 and 44 for each pair of ISL devices 42a, 42b.
Can communicate with each of the ISL devices. If link 42 becomes inoperable, communication can still be carried out only by links 43 and 44. This multipath capability is made possible by the timeout logic system described below that resides on each ISL device.
In this case, another communication path is sought when the current communication path is blocked. FIG. 4 is a simplified functional block diagram illustrating a pair of ISL devices that provide a communication path between a pair of communication buses. In FIG. 4, ISL devices 50 and 51 each provide a path for data and control information between system components attached to communication buses 52 and 53. The ISL devices are identical and each has a register file of sufficient width to store all communications bus transfers, including security and control information. In particular, channel number and address information from local communication bus 52 is sensed by logic recognition device 54 of local ISL device 50. If this information includes a certain channel number or address recognized by the recognition device, the address and data bus information is stored in a register file 55 having four locations. If communication between local bus 52 and remote bus 53 is required, local ISL device 5
The channel number and address information received by 0 is sent to remote bus 5 via remote ISL device 51.
It undergoes conversion by conversion logic 56 before being transferred to 3. If the communication request is initiated by the remote bus 53, the channel number and address information is transmitted to the remote bus 53.
It is recognized by the logic recognition device 57 of the ISL device 51. If this information is recognized, data and address information from the remote bus is stored in a remote register file 58, which has four locations. If contact with local bus 52 is required, channel and address information is provided via translation logic 59 before being transferred to local bus 52 via local ISL device 50. For convenience, we will refer to the two buses as either local or remote buses. This local/remote relationship usually depends on which bus initiated a given cycle. Therefore, an ISL device that receives bus information from a neighboring bus is designated as a logical ISL device. The logical names of the four file locations in register files 55 and 58 were run up to the control ISL traffic.
Display ISL logical operations. This register file is used for temporary storage of bus information.
Thus, one ISL does not tie up one local bus if there is a delay while gaining access to one remote bus. Using register files, all local bus traffic operates at normal bus speeds, and each register file location dedicates functionality for a particular type of bus transfer. The table shows the types of bus cycles that can occur while bus information is stored in the file registers. The memory write bus cycle is
Requires that the particular register they are allocated to be empty. This condition is tested through a file full of flip-flops located on each ISL device. A read cycle requires a specific response to be reserved at the remote ISL device.
This requirement is related to the general purpose bus characteristics which require that the second half (response) cycle be always accepted and is accomplished by resetting the flip-flop to a full file. Once a write request has progressed from the local ISL device to the remote ISL device, the full file of flip-flops is reset to complete the operation. Conversely, a full flip-flop will not be reset during a read request until a response is received from the addressed device on the remote bus. Therefore, the previous response is remote ISL
All requests are localized until completed by the device.
Not accepted by ISL equipment.

Table: There are two distinctly different transfer paths through which ISL devices respond to bus requests. register file
In response to a storage request (MRQ) passing through an MRQ location, the ISL device issues a response on the local bus without first asking the remote bus. It is important that ISL devices respond to such requests and release the local bus as quickly as traditional storage devices. For these requests through a retry request (RRQ) location, the ISL device solicits a response from the destination device on the remote bus. Because the destination device receives a response to either an acknowledge (ACK), negative acknowledge (NAK), or wait (WAIT) signal, the ISL device does not provide any meaningful response to the requesting device until the actual response is received. I can't give it. When a local ISL device receives an RRQ request, it responds with a WAIT response. The requesting device on the local bus then proceeds to restart the request cycle until it receives a non-WAIT response. While the requesting device is occupied, the remote ISL pair addresses the destination device and sends one response (ACK, NAK or
WAIT). Each time the requesting device issues a request cycle, the local ISL device responds with a WAIT response until an ACK or NAK is received from the destination device.
The local ISL device then compares the information received during the request bus cycle with the contents of the RRQ register location. If the requesting device is the same device that made the original request, the local ISL device
Sends the response received from the device to the local bus. If the remote ISL device receives an ACK, NAK, or
Upon receiving the WAIT signal, the local ISL device issues a similar response to the local communication bus. Each ISL device gains bus visibility of its memory, I/O controller, or processor each time it interrupts a bus transfer on one bus and reinitiates it on a different bus. Each ISL device responds to a configured memory address, CPU address, and channel number through the storage of data in a mask and translation RAM. During system operation, each ISL device monitors all bus traffic and responds to individual bus request cycles within a range of identified numbers on behalf of the destination device on the remote bus to which the cycles are directed. When a local ISL device responds to a bus request cycle (BSDCNN),
At the same time, the remote ISL device resumes bus request cycles on the remote bus. The response cycle from the destination device follows a similar path in the opposite direction and is finally sent to the originating device. Except for the ISL configuration mode described below,
ISL devices have minimal software visibility. The objective is to provide an ISL device with transparency, thereby allowing the same functionality to occur between two devices on different buses to occur between two devices on the same bus. Since one ISL device connects two communication buses, this device can be used as a component in a multiple bus configuration. ISL devices can support any system configuration ranging from a single bus extension to configurations requiring shared storage capacity and dual access to central processor-to-central processor interrupts and I/O controllers. can. Furthermore,
A linked system may include certain multiple buses linked by multiple ISL devices. FIGS. 5 and 6 FIG. 5 is a simplified functional block diagram illustrating the sequence of operations performed during the transfer of information between communication buses. FIG. 6 shows the same sequence of operations by means of a timing diagram. In FIG. 5, a request cycle (BSDCNN) is generated by a device that interfaces with communication bus 60. In FIG. During a request cycle, the location of file register 61a corresponding to the type of cycle requested is scanned to determine if another request is present in the register file at this time. If the file register location is blank, data associated with the BSDCNN signal is stored in local file register 61a. Additionally, it is determined whether the associated ISL interface device 62a can act as a vehicle for communication bus 60 requests. If not,
BSDCNN signals are ignored. If the ISL interface device is able to accept the signal, an ACK or WAIT response is sent to communication bus 60. especially,
If the device to which the communication is transmitted is connected to one communication bus 63
If it is a storage device that interfaces with
ACK is normally sent as one response. If this device is a PCU, the peripheral device is ACK,
A WAIT is generated until it is determined whether to generate a NAK or a WAIT. At this time communication bus 60
is released to continue processing another cycle request. If the ISL interface device 62a becomes temporarily busy after it has been determined to act as a means for a local bus request, the device responds with a WAIT response. After verifying that the device to which the information is to be transferred is available, the local ISL cycle is transferred to the ISL device 61.
Plan within. This planning is required to avoid conflicts with responses or requests initiated by communication bus 63. Upon completion of the first local cycle in the ISL device 62a, the ISL device 62a
Loaded with address, control and data signals from 0. A second local cycle is not initiated until the remote cycle at ISL device 64 has completed and emptied the ISL interface device. In connection with the above scheme, ISL devices are also subject to a priority convention in which storage requests displace them to other devices and local cycles displace remote cycles. When ISL device 64 enters a remote cycle, ISL interface device 62a
The information stored in is transferred to file register 64b. At this time, the ISL device 64 uses MYDCNN.
An attempt is made to issue a signal to the communication bus 63. When a bus cycle is provided to ISL device 64, the information stored in file register 64b is sent to the addressed device that interfaces with communications bus 63. The information provided by communication bus 60 is thereby transferred to communication bus 63 substantially in its original form. When a device interfacing with communications bus 63 initiates a cycle request to communicate with a device interfacing with communications bus 60, the above operations are repeated to cause local cycling to ISL device 64 and remote cycling to ISL device 64. Occurs at 61.
In particular, communication bus 63 is connected to file register 64a.
Emit the BSDCNN signal stored in the . At this time, a local ISL cycle is started and the communication bus 63
address to ISL interface device 62b,
Stores control and data signals. ISL device 61
Simultaneously with the occurrence of a remote ISL cycle in
Information stored in interface device 62b is passed to communication bus 60 by file register 61b. In FIG. 6, waveform 65 shows the BSDCNN issued by the communication bus in response to a cycle request, and waveform 66 shows the occurrence of a local ISL cycle.
Waveform 67 shows that the information is from the local file register.
Indicates the duration of transfer to a remote register file via an ISL interface device. waveform 68
indicates the occurrence of a remote ISL cycle, and waveform 69 indicates the period during which communication is ensured between the remote register file and the device interfacing with the remote communications bus. It should be understood that the waveforms in FIG. 6 are approximations and do not represent exact periods. This necessarily indicates the order in which the waveforms occur, but does not indicate their duration. A first local communications bus generates a BSDCNN signal represented by pulse 65a received by a local ISL device interfacing with the communications bus. If the interface device is available, the information provided by the local communication bus is stored in the interface device. At the same time, the local ISL device generates a response to the signal BSDCNN indicating the availability of the local ISL interface device represented by pulse 66a.
enter the cycle. Simultaneously with the occurrence of the transfer cycle pulse shown at 67a, a remote ISL cycle request is scheduled. During a remote cycle, as indicated by pulse 68a, information stored in the ISL interface device is sent to a remote file register that interfaces with the telecommunications bus. At the same time, a bus cycle request is made by the remote ISL device, and the bus cycle is prioritized.
Can be used for ISL devices. pulse 69a
During this period, a BSDCNN cycle is generated on the telecommunications bus in response to pulse 69a to secure a communications channel between the remote file register and the device interfacing with the communications bus. At the same time, information provided by the local communications bus is placed on the remote communications bus. At this time,
The device addressed by the channel number that has the information receives the information and issues an ACK signal, or
Alternatively, a NAK or WAIT signal is issued as described above. FIG. 7 shows, in a functional block diagram, the architecture of another system embodying the invention, in which the multiple communication buses are integrated into one communication bus with which all PCUs of the data processing system can be interfaced. You can interface with Furthermore, if a virtual storage concept is used, the storage devices of remote systems are interfaced with one communication bus,
Local system storage can be interfaced with these communication buses that communicate directly with the CPU. In FIG. 7, remote storage devices 70-72 and ISL devices 73 and 74 are electrically connected to a communication bus 75. In FIG. ISL device 73 is further electrically connected to ISL device 76 which is connected to communication bus 77 . Furthermore, the ISL device 74 is connected to a communication bus 79.
In electrical communication with ISL device 78. Also, CPU80
, the ISL device 81 and the local storage device 82 are also connected to the communication bus 7.
9 is connected. Further, the CPU 83, ISL device 84, and local storage device 85 are connected to a communication bus 77. Thus, although the system architecture described thus far allows for the use of virtual memory concepts, CPU 83 can access not only local storage 85 but also remote storage 70-72. Similarly, CPU 80 can access local storage 82 and remote storage 70-72. ISL device 81 is in electrical communication with ISL device 86 which is further connected to communication bus 87 . ISL device 8
4 is in electrical communication with an ISL device 88 connected to a communication bus 87. A plurality of PCUs 89 are also connected to communication bus 87 to provide access to a common information source for CPUs 80 and 83. FIG. 8 is a more detailed functional block diagram illustrating the flow of data in one ISL device. The control logic for this ISL device is described below with respect to the description of FIG. Data transceiver 90 receives data from the local communications bus and stores such data in a 4 x 16 bit data file register 92.
16-bit data bus 9 connected to the input side of
Give to 1. This bus 91 is also connected to one input of a bus converter 93 for comparison with data stored in a data file register 92. The data bit zero line of bus 91 is connected to the input of master clear generator 94. The master clear generator also receives a 6-bit initialization command on bit lines 8 through 16 of the 24-bit local address bus 96. In response to the input signal, the generator issues a master clear signal on conductor 97, as further described in connection with the description of FIG.
Reset the ISL device. Bus 96 is connected to the output of address transceiver 98, which receives address information from the local communications bus. Lines 8-16 of bus 96 are applied to the inputs of an ISL address converter 99 for address detection, and bit lines 0-9 are applied to the I2 inputs of a 10-bit storage address multiplexer 100. Data bit lines 0-1 are connected to multiplexer 1 during response to an I/O output load command.
00 I1 input side. Bit lines 8-17 of bus 96 are 10-bit channel addresses.
It is applied to the I2 input side of register 101, and bit lines 18-23 are applied to the input side of function decoder PROM 102. Bus 96 also includes a 4 x 24 bit address file register 1 for storage.
03 and data file register 9
Bus comparator 93 for comparison with the contents of 2.
is applied to the second input side of. Address receiver 104 receives address information from the telecommunications bus and converts this information into a 24-bit tri-state address signal connected to the input of function code decoder 106 by a 4-bit bus 107 consisting of bit lines 20-23. bus 105. Bit lines 20-23 of address bus 105 are connected to the 4-bit output side of PROM 102. Bit lines 5 to 17 of bus 105 are 13
Bits 0-23 are connected by bus 110 to the 23-bit output of the address file register. Furthermore, bus 105 is connected to the 24-bit input side of bus comparator 93, and bit lines 8-23 of the bus are connected to address multiplexer 1.
Connected to the I2 input side of 11. Bit lines 14-17 of this bus are connected to address multiplexer 11.
Connected to the I1 input side of 2. Bit lines 14 to 17 of the bus 105 are connected to a 4-bit input I1 of a 16×4-bit CPU source conversion RAM 113.
Bit lines 14-17 are connected to 4-bit input I2 of CPU address register 114, and bit lines 0-2
3 is the ISL interface output driver 115.
For 24-bit inputs, bit lines 8-17 are connected to the 10-bit input I2 of register 101. Data from the telecommunications bus is transferred to a 16-bit tri-state data bus 11 via a data receiver 116.
7, and its bit lines 2-15 are applied to the input side of a 10-bit RAM progressive counter 118. This counter 118 provides a 3-bit write enable control signal on lead 119 and also sends a 10-bit count to RAM control register 1 via bus 120.
08 input side. Furthermore, the data bus 11
7 is connected to the output of a 16-bit data file transmitter register 121 which provides information from data file register 92 to the tri-state bus. The input of register 121 is connected to the 16-bit input of bus comparator 93, the output of data file register 92, and the 16-bit input I1 of multiplexer 111. The third input I3 to multiplexer 111 is connected to the output of address multiplexer 112, whose second input I2 is connected to 4-bit bus 122. The 16-bit output of multiplexer 111 is applied to the input side of address transceiver 123. The output of address transceiver 123 is provided to the local communications bus. Data file register 92 provides data to bus comparator 93 during local communication bus cycles, to address multiplexer 111 during response cycles, and to data file registers during internal ISL cycles.
Provides data to file transmitter register 121. Bit lines 6-15 of data bus 117 are
Its write enable input I2 is provided to the 1.0K I1 input by an 11-bit storage address translation RAM 125 connected to the bit 5 data input of data bus 117. A third input to RAM 125 is connected to the 10-bit output of multiplexer 100. Input side of 10-bit memory verification register 126 or 10-bit IOLD (input/output load)
For any of the registers 127, the RAM
gives 10 bits of converted storage address data. The RAM 125 also provides a hit bit control signal via lead 128 to the input of an internal data multiplexer 129. register 126
The output of is provided by a 10-bit three-state bus 130 to the second input of multiplexer 129 and via driver 115 to the telecommunications bus. The output of register 127 is provided by bus 130 to driver 115 and to the third input of multiplexer 129. Bit lines 6-9 of data bus 117 are applied to the I1 input side of register 114, and the output of this register is applied to I1 of 16 x 4 bit CPU defined RAM 131.
given to the input side. The I2 input to RAM 131 is connected to bit lines 0-3 of data bus 117, and the I3 input to RAM 117 is connected to bit lines 0-3 of data bus 117.
connected to the data bit 3 line. The output of RAM is the 4-bit input I5 of multiplexer 129.
is applied to the 4-bit input of driver 115. Bit lines 6-9 of data bus 117 are connected to a 4-bit interrupt channel register 132, bit lines 0-15 are connected to the inputs of timer and status logic 133, and bit lines 10-15 are connected to
On the input side of bit interrupt level register 134, bit lines 0-15 are connected to the 16-bit input I1 of data multiplexer 129. Bit lines 0-4 of data bus 117 are 5-bit lines.
connected to the input side of the mode control register 135;
Bits 0-3 are connected to the I1 input of the 4-bit CPU source address register 136 and the I1 input of register 136, and bit lines 6-9 are connected to the I2 input of register 136.
Connected to the input side. Bit line 3 of data bus 117 is provided to the write enable input of CPU destination RAM 131. The 4-bit output of register 132 is provided by bus 122 to the I2 input of address multiplexer 112 and to the 4-bit input I4 of data multiplexer 129, as previously described. Logic unit 133 provides the ISL status bit to the I3 input of multiplexer 129, and the output of register 134 is provided to the I2 input of the data multiplexer. The output of the mode control register 135 is
Control logic is provided which will be further described in connection with the figure description. The 4-bit output of register 136 is
This RAM is given to the I2 input side of RAM113.
The output of is applied to the I1 input side of data multiplexer 137. The I2 input to data multiplexer 137 is connected to the output of data multiplexer 129;
It is connected to the I3 input of data multiplexer register 138 and to the telecommunications bus via ISL output driver 139. Data multiplexer 1
The output of 38 is I2 of data multiplexer 138.
given to the input side. Data multiplexer 1
I1 input to 38 is hex rotary switch 1
40, the output of the multiplexer is provided to the local communication bus via a data transceiver 141. Multiplexer 138 provides a 16 bit output to transceiver 141. 6-9 of this output
The bits are provided by multiplexer 137;
Bits 0-5 and 10-15 are multiplexer 12
9. Bits 0-15 of the output of multiplexer 129 are provided to driver 139. One input of the 1024×1 bit RAM 142 is connected to the output side of the register 101. RAM142
The writeable input I2 to data bus 117
The output of the RAM is applied to the I8 input side of the data multiplexer 129. The control logic further described in conjunction with the description of FIG. 14 provides control signals on leads 143-145 to the input of cycle generator 146. In response, generator 146 issues a timing signal as further described. A brief explanation of how communication buses work can be found in
For understanding the type and format of commands and other information received by ISL equipment. next,
ISL/Bus Interface Description followed by ISL
A description of the interface and the operation of the ISL device of FIG. 8 in response to specific bus cycle requests follows. A communication bus provides a common communication path for all devices that interface with it. This bus is an asynchronous structure that allows devices of various speeds to operate effectively within the same system. 2 due to the bidirectional nature of the bus.
Two devices can communicate at once. The transfer of information between the two devices forms a master/slave relationship, where the device requesting and being granted access to the bus becomes the master and the device addressed by the master becomes the slave. All information transfers are from master to slave, and each transfer is called a bus cycle.
This bus cycle is the period during which the requestor (master) requests use of the bus. If no other device of higher priority makes a bus request, use of the bus is granted to the requestor (master). The master then sends the information to the slave,
The slave confirms this communication. If the master's request requires a response, then
The responding slave device takes the role of master,
The requesting device (former master) becomes the slave. Communication between a master and a slave requires a response from the slave while the slave is transferring data. In this case, a request for information requires one cycle and returning the information to the requester requires another bus cycle to complete this task. A master device can address any other device on the bus as a slave by placing the slave device's address on the address line of the bus. There are 24 address lines, which can take one of two interpretations depending on the state of the storage reference (BSMREF) signal. If the BSMREF signal is at a logic one level, the following format is applied to the address lines.

[Table] If the BSMREF signal is erroneous, the following format is applied to the address line.

[Table] Three types of communication are allowed on one bus. namely, memory transfers, I/O transfers, and interrupts. When devices on a bus are transferring control information, data, or interrupts, they address each other by channel numbers. According to the channel number, a 6-bit function code is transferred specifying the function to be performed. When the master device requests a response from the slave device, the master device sends a bus write (BSWRIT).
-) Convert the signal to a logical zero level. Furthermore,
The master device provides its identification attribute to the slave device by channel number. this is,
It is encoded on the data line of the bus as shown below.

TABLE A channel number exists for each device in the system except for storage, which is identified only by storage address. The slave device's channel number appears on the address bus for all non-store transfers. Each device compares this channel number with its own internally stored channel number. A device that detects that these are equal is a slave device,
must respond to said cycle. This response cycle is directed to the master device via a non-memory reference transfer. A second half bus cycle (BSSHBC-) signal accompanies the transfer identifying this bus cycle as a bus cycle awaited by the master device. CPU channel numbers are limited to the range 000 ₁₆ to 00F ₁₆ . The six most significant bits of the channel number are
Fixed to zero by CPU logic, the lowest 4
Only bits can be used. The CPU channel number is not used by any other device. Tables 2A and 2B list common types of bus operations that each require one or two bus cycles. Information transfers that are considered write operations require one bus cycle, while transfers that are considered read operations require another bus cycle for a response.

【table】

TABLE Table 3 provides a complete list of signals used to interface ISL logic with the bus. Further these signals are shown in FIG. The interface signals described below provide the initial connection functions required by a device on the communication bus to either initiate, accept, or reject a request for a bus cycle from another device. It should be understood that in the description of signals, the terms "true" and "false" are to be construed with respect to the plus and minus associated with the signal mnemonic. For example, BSREQT- is at a logic zero level when true and a logic one level when false. However, when the signal BSAUOK+ is true, it is at a logic one level, but when it is false, it is at a logic zero level. The bus request (BSREQT-) signal, when true, indicates that one or more of each device connected to the bus has requested one bus cycle. When this signal is false, no requests are alive. The Data Cycle Now (BSDCNN-) signal, when true, indicates that a particular master device (i.e., CPU, memory, or controller) has given the required bus cycles to transfer information to the bus for use by a particular slave device. Indicates that it is placed above. When this signal is false, the bus is not in use and is between bus cycles. The acknowledge (BSACKR-) signal, when true, indicates to the master device that the slave device has received and accepted a particular transfer from the master device.
A negative acknowledgment signal (BSNAKR-) indicates to the master device that the slave device is rejecting a particular transfer. For example, a slave device may refuse to accept a transfer when a busy control device is addressed for a data transfer. The wait signal (BSWAIT-), when true, indicates to the master device that the slave device is unable to accept a particular transfer at this time.
The slave device is temporarily busy and the master device must initiate continuous retries until the transfer is acknowledged. The following signals transfer information during one bus cycle. This bus data bit line (BSDT00- to BSDT15) consists of one data bit line (BSDT00- to BSDT15).
word, channel number encoding, lower address
It can be formatted according to the operations to be performed on the decoding of bits or priority levels. Thus, data, address, control, record, or status information can be reflected by the 16 data lines of the communication bus. 24 address lines on one bus (BSAD00
- through BSAD23-) can be formatted to one 23-bit main memory address to select one of 8 million words. This address line is also the channel number code, lines 18 to 23.
I/O function code above or further explained below
It can be formatted for all three combinations for IOLD operations.

【table】

TABLE The signals below act as data, address, and information control signals to transfer and control information during one bus cycle. The storage verify signal (BSMREF-), when true, indicates that bus address lines 0-23 contain the complete main memory address from the master device. If false, the BSMREF- signal indicates that this bus address contains a channel number on lines 8-17 with or without feature codes on lines 18-23, or that this bus address line contains a channel number on lines 0-17 with or without feature codes on lines 18-23. 7 contains the main memory module address code. The write signal (BSWRIT-), when true, indicates that the master device is transferring data to the slave device. When this signal is false, the start bus cycle signals a read request;
The data line of the bus contains the channel number of the requesting device; if the slave device accepts this request, the second half bus cycle (BSSHBC)
It is expected to respond with a read response within
The BSWRIT- signal is true for all operations except controller or CPU memory read requests and CPUI/O read commands. These operations require a response request to provide information to the master device via another bus transfer. The second bus half cycle (BSSHBC-) signal is true when the current information produced by the slave device to the master device is the information previously requested during the first bus cycle. Show that. The byte (BSSYTE-) signal, when true, indicates that the current transfer is a byte transfer rather than a word transfer. This signal is used only during memory write operations. BSLOCK
-) signal, when true, indicates that the master device requests a change in the storage lock flip-flop status. This BSLOCK- signal also allows three-cycle read/modify/write operations that allow three cycles to be performed to the requesting device without interruption. The first cycle is a read cycle in which the address line of the bus cycle contains the storage address and the data line of the bus contains the channel number of the requesting device. Second
The cycle is a response cycle in which the address line of the bus contains the channel number of the requesting device and the data line of the bus contains the data read from main memory. The third cycle is a write cycle, where the address lines of the bus contain the storage address and the data lines of the bus contain the data to be written to memory. In this way, one device can read and modify a particular memory location while preventing read/modify/write interruptions by other devices on one bus. However, memory can be accessed by other storage requests following the second of the three cycles described above. When the double pull (BSDBPL−) signal is true,
Indicates that the master device is requesting one doubleword operand from the slave device.
During the first second half-bus cycle, the signal
BSDBPL- is returned to the requesting device to indicate that another word will follow. The next signal line provides a two-way bus parity line for main memory error notification signals for available devices and odd parity signals used with address and/or information bits placed on one communication bus. do. The two lines perform bus continuity checks and test the integrity of resident logic tests on each device. The bus red error signal (BSREDD-) is generated only by main memory, including the EDAC logic. This signal, when true, indicates that the memory has detected an error during the second half bus cycle of a read operation. Bus yellow error signal (BSYELO−)
is generated only by main memory containing EDAC logic. When true, this signal indicates that the memory has performed error detection and correction during the second half bus cycle of a read operation. The logic level of the bus address parity signal (PSAP00-) provides odd parity for address bits 0 through 7 (ie, module address bits). The logic level of the Bus Data Parity Left Byte signal (BSDP00-) provides odd parity for bits 0 through 7 of a 16-bit data word. The logic level of the bus parity right byte signal (BSDP08-) provides odd parity for bits 8 through 15 of the 16-bit data word. The bus characteristic logic test out/in signals (BSQLTO- and BSQLTI-) are static integrity signals that, if continuously true, indicate successful completion of each test. Signals are relayed from device to device from one end of the bus to the other or vice versa. This effect efficiently performs continuity checks on all available devices. Tie breaking signal (BSAUOK+ to
There are nine signals called BSIUOK+), all of which must be true to provide availability to a device requesting a bus cycle. If more than one device requests a bus cycle at the same time, this cycle is given to only one device based on positional priority as described above. Memory has the highest positional priority and the CPU has the lowest priority. Therefore,
Under simultaneous request conditions, the highest priority requesting device receives a true enable signal from all nine tie-breaking signals. The remaining requesting devices receive 8 or less according to their relative positions down the hierarchy. The signal (BSMYOK+) indicates to the next lower priority device that the generating device and some other higher positional priority device have not requested one bus cycle within a predetermined period of time. Therefore, one bus cycle is given to lower priority devices as needed. The following control signals are asynchronous to the functions they perform in the normal initiation and control of bus cycles. The interrupt resume signal (BSRINT-), when true, allows all controllers to resume a previously denied interrupt to the CPU with a negative acknowledge signal. The master clear signal (BSMCLR-) indicates that the master clear button located on the CPU control board has been pressed or that a power-on sequence is in progress. If any of these conditions exist, the initialization operation is effectively performed on all available devices. If the bus power on (BSPWON+) signal is true, it indicates that all power supplies are functioning correctly. When the power supply is stable, this signal converts to the true state,
Convert to false state a few milliseconds before power failure. The communication bus interfaces with ISL equipment by a group of transceivers that provides the required equal electrical characteristics of all bus connections, thereby providing ISL data addresses and most control signals.
Allow access to and from equipment. The interface between ISL devices is shown in the overall functional block diagram in FIG. The interface signals exchanged between ISL devices are shown in FIGS. 11 and 4.

【table】

[Table] The asynchronous inter-ISL interface consists of two identical bidirectional buses, as shown in FIG. 10, which provide parallel bidirectional processing between ISL devices. FIG. 11 shows information transfer on one of the two buses. The following section describes the ISL that appears on such a bus.
Briefly explain the signal. When the local ISL device has information to transfer to the remote ISL device, the local ISL device issues a remote strobe (RMTSTB+) signal to the remote ISL device. The remote ISL device can identify the type of bus cycle by the state of four control signals, including the RMTSTR+ signal. Each type of bus cycle (i.e., store request, store response, retry request,
and retry response). The remote ISL device uses the RSTSTR+ signal to
Receipt of the information is acknowledged by strobing the control logic's priority circuitry with one control signal and sending a transfer complete bus signal (XFRDUN+) to the local ISL device. Local ISL device
The transfer cycle is complete when the XFRDUN+ signal is received. When true, the Generate Memory Request (GENMRQ-) signal indicates that the local ISL device completes the local storage request cycle and initiates the remote storage request cycle to perform the remote storage request cycle.
Indicates that an ISL device is being requested. The Generate Memory Response (GENMRS−) signal, when true,
Indicates that the ISL device has completed a local store response cycle and is requesting a remote ISL device to perform a remote store response cycle. The generate retry request (GENRRQ-) signal, when true, indicates that the local ISL device has completed a local retry request cycle and is requesting a remote ISL device to perform a remote retry request cycle. . The generate retry response (GENRRS-) signal, when true, indicates that the local ISL device has completed a local retry response cycle and is requesting a remote ISL device to perform a remote retry response cycle. Retry Response (RMRESP
-) signal, when true, indicates that a response was received by the remote ISL device during the remote retry request cycle. The RMRESP− signal is used by local ISL equipment to connect two telecommunications bus response lines, ACK and
Strobes to NAK and starts a bus compare cycle. The remote bus acknowledge (RMACKR+) signal, when true, indicates that the remote pair has received an acknowledgment (ACK) from the telecommunications bus. This signal is used during the retry request cycle, in which the slave device's response must be obtained before issuing a response to the master device. The Remote Bus Negative Acknowledge (RMNNAKR+) signal, when true, indicates that the remote ISL device receives a negative acknowledge (NAK) from the remote communications bus.
Displays that it has been received. The RMNAKR+ signal is used during the retry request cycle in which the slave device's response must be obtained before issuing a response to the master device. The answer acknowledge (ANSWAK+) signal, when true, indicates that the local ISL device has transmitted an acknowledgment (ACK) while completing a local retry request cycle. this
The ANSWAK+ signal is used by remote ISL devices as a timing signal in handling associated retry response cycles. The Translate Channel Number (XLATOR+) signal, when true, indicates that the local ISL device has detected a CPU channel number on the local communication bus. signal
Upon receipt of the XLATOR+, the remote ISL device performs a CPU channel number translation on bits 6-9 of the communication bus. This signal XLATOR+ is
Used when the device is transferring interrupts between CPUs or processing either output interrupt control commands or input interrupt control commands. When the remote function (RMTFUN+) signal is true,
Indicates that the local ISL device has received an ISL command addressed to a remote ISL device. When the ISL clear (MYMCLR−) signal is true,
Indicates that the local ISL device is performing a clear sequence. The paired connection (TWINCN-) signal, when true, indicates that the remote ISL device is properly connected. The Address Parity Error (LCAPER+) signal, when true, indicates that the local ISL device has detected a communications bus address parity error. Upon receiving this signal,
Remote ISL devices generate incorrect address parity during telecommunications bus transfers. In this way, errors can be sent to a practical destination before notification. The data parity error (LCDPER+) signal, when true, indicates that the local ISL device has detected a communications bus data parity error or bus redundancy. Upon receipt of signal LDCPER+, the remote ISL device generates incorrect data parity and bus read errors during telecommunications bus transfers. In this way, errors are forwarded to the actual destination before they are notified. When the illegal memory (NOXMEM−) signal is true,
Indicates that the remote ISL device has received a negative acknowledgment (NAK) response on one of the unlocked storage write requests. Upon receipt of the signal NOXMEM-, the local ISL device attempts to generate an illegal resource interrupt. The remote monitoring time out (WTIMOT+) signal, when true, indicates that the remote monitoring timer has expired. signal
Upon receipt of the WTIMOT+ signal, the local ISL device will attempt to generate a supervisory timeout interrupt. The Remote Dead Man Time Out (RMTOUT-) signal, when true, indicates that the remote ISL device has not received a response, i.e., ACK, NAK,
Indicates that no WAIT response was received. The transfer of information between ISL devices forms a local/remote relationship. The ISL device that is transmitting information is displayed as a local ISL device, and the ISL device that is receiving information is displayed as a remote ISL device. All information transfers between ISL devices are in the local-to-remote direction, and each transfer is called a transfer cycle. This local/remote relationship is the master/remote relationship on the communication bus.
Similar to slave relationship. When a master device requests a bus cycle on the bus, the ISL device that interrupts the cycle becomes a local ISL device. For other types of bus cycle requests,
The slave device must respond with either an ACK, NAK or WAIT response, and it is likely that any of the three responses will occur. In such a case, the ISL device cannot provide a meaningful response to the master device until the destination slave device responds. There are the following types of bus cycle responses: That is, I/O output requests, I/O input requests,
A memory read request test and set lock signal, and an interrupt. If one of these types of bus cycle requests is received by the local ISL device, the ISL device
Reply with WAIT. Therefore, the master device on the local bus will remain on the bus until a non-WAIT response is received.
Proceed to start the cycle request again. While the master device is occupied in this way, the remote ISL device can address the slave device and send an ACK or
Get a NAK response. Upon the next bus cycle request from the master device, the local ISL provides the slave device's response. An ISL device that addresses a slave device on a remote bus becomes a remote ISL device. However, if the communication requires a certain response, the previous slave device becomes the master device. Furthermore, the previous remote ISL device becomes the local ISL device. The basic cycles generated for one ISL device are 3
There is one. There are three cycles: local, remote, and transfer. Local cycles generally enter to operate on information in address file register 103 and data file register 92. A local cycle is also entered if no remote cycle or file information cycle is ongoing and an ISL interrupt, storage timeout, or I/O timeout is ongoing. The local cycle also causes the RAM counter 118 to count from zero to 1024.
It also occurs during the master clear sequence that initializes all RAM locations in the ISL device. When an ISL device enters a local cycle to process information in the address and data files, no transfer cycles are in progress. A remote cycle is entered by a remote ISL device that receives information from a local ISL device. If local and remote cycle requests are received simultaneously,
Local cycle requests are satisfied first. The remote cycle consists of four remote ISL commands: store request generation command, store response generation command, retry request generation command,
or in response to either a retry response generation command. To enter a remote cycle, an ISL device must be in either a local cycle or a bus compare cycle. A transfer cycle is entered to transfer information from a local ISL device to a remote ISL device. A local ISL device that transfers data to a remote ISL device generates a transfer cycle and causes a corresponding remote cycle to occur. The transfer cycle is terminated by the local ISL device upon detection of the remote cycle at the remote ISL device. During the generation of each cycle described above, the ISL device is in one of three main states. In particular, CPU commands can load mode control register 135 with a bit pattern that places the ISL device in one of three logic states: clear, stop, and on-line. Conversions between states occur in response to I/O output control commands or power-on sequences. This I/O command can be initiated from either the local or remote communications bus. The clear state is transient. In this state,
Entered when an I/O output control command requests initialization of the ISL device or when a power-on sequence is initiated. In the clear state, local
The CPU can reset the local ISL device by setting each translation storage cell of RAM 125 to a logic one level. As a result, the ISL configuration information
It is removed from RAM113,125,131,142. Therefore, the ISL device will not respond to any bus cycles except those given to the ISL channel number. The ISL device automatically enters the Clear state or an ISL device that requests the ISL device to enter the Stop state.
It enters the stop state in response to the O output control command. When entering the stopped state from the online state, the ISL device:
RAM113, 125, which existed before the stopped state
All configuration information in 131 and 142 is retained. While in the stopped state, the ISL device does not respond to any bus cycles except those directed to the ISL device's channel number. It is only in the stopped state that the ISL device accepts I/O commands and changes configuration information. Specifically, the on-line state is entered in response to an I/O output control command that requests the ISL device to enter a data transfer mode. In the on-line state, for bus cycles directed to an ISL channel number that are not configuration control commands, and have a logic value of 1, called the channel hit bit.
The ISL device responds to a bus cycle directed to a location in RAM 142 and to a location in RAM 143 with a logic one bit called the storage middle bit. However, ISL devices can be configured to operate in special test modes. This test mode is associated with the bus response that occurs during testing and verification as further described below. The ISL device is further placed into one of five logical control modes indicated by the I/O output command word. The control modes include clear mode, stop mode, restart mode, and circulation mode.
Includes NAK retry mode. Clear mode, as indicated by control mode register 135, occurs when any of the following conditions exist: That is, (1) the master clear function is activated while power is being applied to the ISL device; (2)
If a power failure occurs, (3) the initialization bit (data bit line zero on bus 90 or 116) is enabled in the output control command. or (4) the master clear function is activated when the master clear button is pressed on the operator control panel;
These are the four conditions. The occurrence of any of the first three conditions causes the initialization of all configuration data in the ISL device. When the master clear function is activated, the ISL device maintains its current logical state and the ISL
The composition remains unchanged. master clear
The sequence is initiated simultaneously on the local and remote ISL device partners. This sequence includes an interrupt channel register 132, an interrupt level register 134, and a mode control register 135.
Continues until the ISL register is cleared. The interrupt level of the ISL device is thereby set to zero. A local retry cycle is generated during the master clear sequence and the RAM counter 118 is
Increased to a count of 1024 (CNTR1K). Signal CNR1K is the master clear signal when valid.
Terminate the sequence. At the same time, all RAM locations on the ISL device are initialized and then
An ISL device responds only to bus traffic directed to its own ISL channel number. In stop mode, all ISL devices respond only to bus cycles directed to their own channel number. Commands attempting to communicate through the ISL device will be ignored and time out as described below. Store or I/O read cycles that are accepted before entering stop mode are completed before entering stop mode. In resume mode, the ISL device returns to the online state. This ISL device assumes that the bus cycle is not a configuration control command.
Responds to bus cycles directed to an ISL channel number. Additionally, the ISL device is responsive to the occurrence of hit bits on the outputs of RAMs 125 and 142. The relationship between logic states and possible logic control modes of an ISL device is shown in FIG. The three logical states that an ISL device can be in are an online state 150, a stopped state 151, and a cleared state 15.
It is 2. If the ISL device is on-line and receives an I/O output control word command and enters the resume logic control mode, the on-line state is re-entered as indicated by logic control loop 153. If logical decision flow or online state 1
If you convert from 50 to stopped state 151, ISL
The device must enter a stop logic control mode to perform such conversions. Upon receiving an I/O output control word commanding the ISL device to enter the stop logic control mode while in the stop state, the logic control loop 1
Re-enter as illustrated by 54. If the ISL device converts from the stopped state 151 to the clear state 152, the ISL device must enter the clear logic control mode to perform said conversion. Clear state 152 is temporary, as shown by the dotted line in FIG. At the same time as entering the clear state, the ISL
The device automatically converts to the stopped state 151 as indicated by the dashed logical path 155. In addition, the clear state can be turned on or off depending on the clear logic control mode.
Power on or power off from line state 150
It can also be entered in response to an off action. If a power-off condition occurs while the ISL device is in the online logic state, the ISL device is allowed to remain online for approximately 1.50 milliseconds to allow notification of status between the communication buses. When an I/O output control word command is stored in mode control register 135 of FIG. 8, the output of the register signals the type of ISL response desired to the control logic. When bit zero is at a logic one level, the master clear control mode is entered. However, when bit 1 is a logic 1, logic control resume mode is entered. When bit 1 is at a logic zero level, logic control stop mode is entered. register 13
Bits 2 and 3 of 5 control the circular logic control mode and bit 4 controls the NAK retry logic control mode. Specifically, when bit 4 is at a logic one level, the ISL device issues a NAK response, and when bit 4 is at a logic zero level, it issues a WAIT response. Circular logic control mode and NAK logic control mode have no effect on the ISL logic state, so
It should be understood that said modes are not shown in the state diagram. Circular logic control mode is a test condition under which local and remote ISL devices and internal ISL interface logic are tested. The NAK retry logical control mode is used to
Causes a NAK response to be sent. This control mode is
Used to temporarily remove higher order devices from the communication bus while the ISL responds to the CPU. The operation of the ISL device shown in FIG. 8 will now be described. In operation, information is received from the local communication bus by transceivers 90 and 98 and stored in registers 92 and 103. register 92
and 103 together provide four 40-bit locations (0-3) to identify the type of information transfer that is occurring. Memory responses (MRS) are assigned the highest ranking location (location 3). The next highest priority is given to location 2 where memory requests (MRQs) are stored. Retry response (RRS) is in location 1
and the retry request (RRQ) is stored in location zero. There are two distinctly different logical decision paths taken by ISL devices in handling bus cycle requests. In one, the ISL device responds to bus cycle requests without first interrogating the remote bus. In the second path, the actual response of the destination device must be obtained by the ISL device before a response to the bus cycle request is made. There are three possible responses to each bus cycle request: ACK, NAK, WAIT. ACK response if the file location is not full, and WAIT if the file location is full.
ISL devices respond to the following types of bus cycle requests in response: An ISL device will never respond with a NAK response to a bus cycle request such as: These are memory read requests, memory write requests, memory read responses, memory read requests, and reset locks, memory write requests and reset locks, and I/O input responses. It is important that ISL devices respond to bus cycle requests and release the bus to avoid undue slowdowns in bus cycle speed. Therefore, if an ISL device accepts a storage request cycle and receives a NAK response on the remote bus, the ISL device may initiate an illegal resource interrupt on the local bus for the write cycle, or use a storage halt timer as further described. must generate a second half bus cycle with incorrect parity for the read request. Local MRQ cycles occur in response to activity bits being set in file registers 92 and 103 when local bus information is stored. A storage request is generated to enable reading or writing in remote memory. In the case of a read, location 2 of registers 92 and 103 remains filled and is not reset until a response is received from the remote memory. The response in the form of MRS data is loaded into remote ISL register location 3, which corresponds to registers 92 and 103 in FIG. The remote ISL then counters an ISL cycle that transfers MRS data to receivers 104 and 116. This allows MRS data to be transferred to buses 105 and 11.
7 to the local communication bus.
and 141. During a remote MRS cycle at the local ISL device, MRS address information is obtained from data file register 92. Upon completion of the transfer of data from the remote communications bus through the ISL device of FIG. 8, a new request is received from the local communications bus. It is understood that there are four communication bus cycles involved in a read operation between communication buses linked by a pair of ISL devices. In contrast, a read operation on one communications bus will involve only two bus cycles. Each local bus cycle given to one ISL device must be duplicated on the remote bus. Thus, the number of cycles required to transfer information between communication buses is twice the number of cycles required for one bus information flow. Two further information transfers will be discussed: RRQ and RRS. RRQs (Retry Requests) are never acknowledged first with an ACK signal. until a response is received from some device on the remote bus.
The WAIT signal must be issued first. For example, when a certain storage location has to be sensed to determine whether this location is used or not.
An RRQ transaction occurs. If not, the data in this memory location may be modified or replaced. Once an RRQ request is made,
All bits are set at location zero in registers 93 and 103 to indicate the usage conditions. At the same time, local
An ISL cycle is generated, followed by a remote ISL cycle and a remote communications bus cycle as described above. When such a response, such as an ACK, NAK, or WAIT, is received from the remote bus, the response and remote response control signal (RMRESP) are sent to the local ISL device. It will be appreciated that a WAIT response is indicated by the absence of an ACK or NAK response. As mentioned above, when an ISL device receives a single bus cycle request, it uses a selective bus cycle to determine which of the four locations in file registers 92 and 103 will be used in capturing the binary information on the bus. Control signals are questioned. Each of the four locations has associated with it a location busy bit called the total bit. All bits are set true when the associated location is loaded and directed to be operated on by the ISL device. Such instructions occur in conjunction with the generation of hit bits by RAMs 125 and 142 of FIG. This entire bit prohibits further information from being loaded only in relevant locations. The other three locations in registers 92 and 103 are loaded unless all associated bits are set. The contents of the relevant location are no longer internal
It is reset whenever it is not needed for the ISL application. For example, all bits of the storage request location are output devices 115 and 1 of the ISL interface.
39 is reset when loaded during the local MRQ storage request cycle of a storage write operation.
However, in the case of a memory read operation, it is not reset until a remote memory response cycle (MRSCYR) occurs. Associated with each location of registers 92 and 103 drive a cycle generator 146.
Local activity called “2D0” bit
It's bit. Sometimes the cycle generator
Activity of local ISL device (FIL2D0−)
and the remote activity bit (RMT2D0-). When a local cycle is generated, the associated activity bit is reset. Coinciding with the idle state at the local ISL device and the occurrence of a bus cycle request on the local bus, a bus compare cycle is initiated at the local ISL device. Bus comparator 93 is connected to file register 9
All 40 bits at locations 2 and 103 are compared with the information received from local bus transceivers 90 and 98. If an equal condition occurs, the ACK, NAK, or WAIT response received from the remote bus is sent to the requesting device on the local communication bus. It is thus clear that whenever a device on the local bus requests one bus cycle on the remote bus, said device will be issued a WAIT response by the local ISL device until a response is received from the remote bus. be. If this response is ACK or NAK,
The local device does not continue to retry. But the response
As long as it is WAIT, this local device continues to generate the RRQ signal. When an I/O command or memory test and set command is issued, the CPU sends the RRQ signal.
Generate it in the ISL device. When an interrupt command is issued to a CPU on a remote bus, the PCU
A signal can be generated. If a WRITE operation is requested, register 9
All bits in 2 and 103 indicate that the information stored in file registers 92 and 103 is
15 and 139. Further communication requests are then made from the local bus. However, if a read operation is requested, the CPU waits until the data is received from the remote bus.
Enters WAIT state. Therefore, all bits in registers 92 and 103 remain set until data is received from the remote bus. Low priority in a multiple CPU environment
If a higher priority CPU on the local bus attempts to access a local ISL device that previously stored information from the CPU to file registers 92 and 103, bus comparator 93 will indicate an inequality condition. To avoid CPU deadlock, NAK retry logic, described further below, is activated by lower priority CPUs to issue NAK signals to higher priority CPUs. It will be appreciated that the ISL device configuration shown in FIG. 8 provides multiple communication paths between local and remote communication buses. In particular, the local ISL device registers four information transfer transactions in registers 92 and 103: RRQ, RRS, MRQ, and
MRS can be placed on standby. One of the transactions can be active during one local ISL cycle while the other three cycles are ongoing. During this period, only selected control signals from remote ISL devices are received. Other information provided by remote ISL devices to receivers 104 and 116 is prohibited. Upon completion of the local cycle and other ongoing cycles, the local ISL device transfers receiver 1 along tri-state buses 105 and 117 to transceivers 123 and 141, respectively.
It enters a remote period where information on 04 and 116 can be sent. Thus, a typical leaf crop for a local ISL device may proceed in the following manner. The local communication bus generates BSDCNN and loads file registers 92 and 103 to the local ISL device. The remote ISL device can then provide information to receivers 104 and 116. Because local cycles have higher priority than remote cycle operations, the information in registers 92 and 103 is initially transferred to three-state bus 10, respectively.
5 and 117 to remote ISL devices by interface output drivers 115 and 139. The logic levels of the three-state buses 105 and 117 are then changed to provide the outputs of receivers 104 and 116 to transceivers 123 and 141, respectively, leading to the local communication bus. What are the four types of transactions, the priority levels assigned to them and ISL cycles, and the ISL architecture?
Together they act to transfer ISL information without substantially affecting communication bus speed. In the preferred embodiment described herein, the duration of one bus cycle is 175-300 nanoseconds. Within this approximation range, no influence on the information flow on the communication bus was detected. A more detailed description of the flow of data between the local and remote communication buses will now be provided in light of the foregoing. ISL devices operate in two modes: information transfer mode and ISL configuration mode. In the information transfer mode, the initial signal BSDCNN from the local communication bus is transmitted to transceiver 9 in FIG.
0 and 98, and if the register is still found to be empty, registers 92 and 1 are received, respectively.
03. If a memory request (MRQ) becomes active during a local ISL cycle,
Local bus information is written to location 2 of registers 92 and 103. If all bits in these registers are not logic 1, they are unconditionally loaded with information as to whether the local ISL device is available as a resource for this cycle. Transceivers 90 and 98 address storage address translation RAM 125 by multiplexer 100 while data information is written to registers 92 and 103. If a hit bit, described below, is present at the addressed location, an MRQ is initiated. Additionally, the storage address data at the addressed RAM 125 location is loaded into storage verification register 126. Therefore, when a local ISL device enters a local cycle, certain storage addresses become available. Memory conversion is performed from bit 0 on the output side of RAM125.
Occurs on 9th. Bits 0-9 represent up to 1024 8.0K modules of memory, while bits 10-23 represent one 8.0K module. Therefore, there is a total of 8.0 megabytes of memory addressable by the communication bus. RAM 125 has 1024 8.0K blocks that are addressed during storage request cycles.
Provides equipment for converting any of the modules. This translation operation enables communication between devices on separate communication buses, where similar storage devices have the same address assignments. Each ISL device includes a 1024-bit channel number RAM, such as channel mask RAM 142.
Each bit in RAM is called a hit bit and represents one channel number. Specifically, this channel number hit bit represents a channel that does not actually exist on the local bus, but requires an ISL device to respond. The ISL device accepts a non-memory match whose channel number corresponds to a channel number hit bit at a logic one level. Data file register 92 and address
Upon completion of loading location 2 of file register 103, if three events each occupy
If the store check signal issued by 25 and received from the local bus is true and the bus lock signal from the local bus is false, all bits of the store request are set. All of these bits also cause the activity ``2D0'' bit to be set, which drives one cycle generator 146 and causes the local
Start an MRQ cycle. During the period when driver 115 is loaded from registers 103 and 126, the 16-bit data word in data file register 92 is loaded into data file transmitter register 12.
1 along bus 117 to the I1 input of data multiplexer 129. The output of multiplexer 129 is selected as input I1 and provided to ISL output driver 139. Driver 115 and 1
19 comprises the local ISL half of the ISL interface device 62a of FIG. 5, as shown by the dotted line. The remaining half of interface device 62a resides at remote ISL device 64. Upon completion of the local cycle, the logic control system strobes to enable drivers 115 and 139, thereby beginning a transfer cycle to send information from the local communications bus to the remote ISL device. When a remote ISL device initiates a memory request (MRQ), the local ISL device of FIG. and 117. When the local ISL device enters the remote cycle, the local
The ISL logic control system signals the completion of the transfer cycle to the remote ISL device. Thereafter, the interface between ISL devices is free to allow further information transfer. Bits 0-23 of bus 105 are multiplexer
It is applied to the I2 input of transceiver 123 via register 111. The 16-bit data word on bus 117 is connected to I1 of data multiplexer 129.
The output of this multiplexer is applied to the transceiver 141 via a data multiplexer register 138. When the logic control system strobes to enable transceivers 123 and 141, information from the remote communications bus is applied to the local communications bus to complete the remote cycle. The previous discussion described the operation of an ISL device under both local and remote cycles in response to storage requests. If an RRQ (retry request) is
Once received by the ISL device, information from the local communication bus is provided to buses 91 and 96 via transceivers 90 and 98, respectively. This information is loaded into registers 92 and 103 as described above. Master device (device that issues commands) on the local communication bus
Bits 8 to 17 of the address information that identify
6 to I1 of channel address register 101
given to the input. In response, register 1
01 addresses channel mask RAM 142. If a logic one bit is present at the addressed location, the output of the RAM converts to a logic one level, thereby identifying the local ISL device as the agent for the request issued by the master device. Control logic is RAM1
42 is sensed, and in response register 9 is sensed.
Set all RRQ bits to 2 and 103. Thereafter, no more information can be loaded into the registers until a response is received from the telecommunications bus. The control logic further issues command strobes as described above to control buses 105 and 1 in response to the I2 input of driver 115.
47 along address file register 10
Send the address information stored in 3. The 16 data bits from data file register 92 are sent via transmitter register 121 along bus 117 to the I1 input of multiplexer 129. However, register 92 may or may not contain valid data. If the master device issues an output or write command, data will be transferred to the addressed device on the telecommunications bus. However, once a read command is issued, the only information that needs to be sent to the remote ISL device is the address of the master device. No data needs to be transferred. If a read command is received from the local command bus, the address of the master device on the remote bus is stored in data file register 92. Additionally, the read command is forwarded to the control logic of the remote ISL device, as further described below with respect to the description of FIG. The control logic of the remote ISL device senses the read command and in response issues the address of the remote ISL device by actuating a six-way rotary switch corresponding to switch 140. At the same time, the ISL address will be presented to the telecommunications bus during a remote retry request cycle via a data multiplexer similar to multiplexer 138 and via a remote transceiver similar to transceiver 141. Upon receipt of a response from the telecommunications bus at a remote transceiver, similar to transceivers 90, 98, during the second half bus cycle, the address information received by the remote transceiver is transferred to the remote ISL address by an ISL address comparator, such as comparator 99. It will be compared against the code.
If the same result is obtained, the comparator will signal the remote control logic. At the same time, the activity 2D0 bit in location 1 of the remote address and data file register will be set by the remote control logic to initiate a retry response (RRS) cycle at the remote ISL device. At the same time, data from the remote file register will be transferred to the remote ISL interface output driver. Upon initiation of a transfer cycle at the remote ISL device, this data is transferred from the driver to the receiver 10 of the local ISL device.
4 and 116. In response to the transfer cycle, the local ISL device enters an RRS retry response cycle and transfers the data from receiver 116 to transceiver 141, which extends to the local bus. In particular, data received from a remote ISL device by receiver 116 is transmitted to multiplexer 1 by bus 117.
It is applied to the input I3 side of multiplexer 138 via the I1 input side of 29. Furthermore, multiplexer 13
The output of 8 is provided to the local communication bus via transceiver 141. To complete the read operation, the master device address stored in data file register 92 is provided to transceiver 123 via multiplexer 111 to the local bus. The transfer of information through an ISL device is discussed next in connection with specific I/O commands passed through an ISL device. The format of such commands is not important for ISL devices since the commands are specific to the devices on the telecommunications bus. These directives are simply ISL
It appears as data to the device and is sent to the communication bus via the ISL device. If an output I/O command is forwarded by a local ISL device to a remote ISL device, the ACK received from the remote ISL device in response to the I/O command will set all bits in registers 92 and 103 to Convert it to a value of zero. This allows additional information transfer from the local communication bus. However, in the case of a read command from the local ISL device, all of the bits will remain at a logic one level until data is received from the remote ISL device. Additionally, data from the remote bus is not allowed to flow back to the local ISL device until an ACK response from the addressed device on the remote bus is forwarded to the master device on the local bus. It is noted that the local ISL device must enter the idle state before the bus compare cycle is performed so that it can receive the requested data from the remote bus. Until the ACK response to the request occurs,
The remote control logic ensures that data is not transferred from the remote ISL device to the local ISL device so that data from the remote bus is stored in the remote data file and address file registers until after appropriate acknowledgments are received. Ru. Data requested from remote ISL device is sent to local ISL
When sent to the device, all bits in registers 92 and 103 are converted to logical zeros, freeing the RRQ path for further information traffic. When an input I/O command is sent to the local communication bus through the remote and local ISL devices, the local ISL device
ISL set on rotary switch 140
The channel address is provided to the local communication bus via multiplexer 138 and transceiver 141. The corresponding local bus generates a bus second half bus cycle (BSSHBC) signal and device address. Signal BSSHBC is received by transceiver 90 and the device address is received by transceiver 98. This device address is compared by comparator 99 with the local ISL device identification code. If the results are equal,
Comparator 99 signals the local control logic. At the same time, the control logic generates an ACK response to the local communication bus. It will be appreciated that all second half bus cycles are ACKed and WAITs are not NAKed. Data from the local bus is then transferred to the immediate data file and address
Stored in file registers 92 and 103.
The local RRS cycle is then queued by the local control logic, and as soon as the cycle begins,
Information stored in data file register 92 is passed through data file transmitter register 121 along tristate bus 117 to the I1 input of internal data multiplexer 129. The output of the multiplexer is provided to an ISL output transceiver 139. During the transfer cycle, information at transceivers 115 and 139 is transmitted remotely.
Given to the receiver of the ISL device. When information is received by receiver 116 from a remote ISL device in response to a request from a device on the local communication bus, the data file. The address of the local bus device stored in register 92 is
11 and the I2 input of transceiver 123 to the local bus. Data from remote ISL devices is routed along tri-state bus 117 to multiplexer 1.
29 and input I3 of multiplexer 138 to transceiver 141. Information transfer mode storage test and set commands are storage requests that use the internal ISL retry path to test remote memory before responding to the local master. The associated data path is the same as that of the local MRQ cycle except that the address information is retrieved from the storage match register 126. The remaining bits 0-23 are transceiver 1
15 from address file register 103 by bus 105 on the I2 input side. Bit 23 is a storage address translation bit for test and set instructions. It should be understood that the I2 and I3 inputs to transceiver 115 are multiplexed. Thus, in the local ISL cycle, the address information is stored in the memory verification register 1.
26 and file register 103 to transceiver 115. Data from file register 92 is provided to data multiplexer 129 via data file transmitter 121 to transceiver 139. The conversion occurs at the remote ISL device. The remaining ISL operations in test and set instructions are standard I/O
Same as for cycles. Before discussing the sending of communication bus interrupts through ISL devices, a more detailed discussion of CPU channel number translation is required. In addition to channel number identification, the ISL device can be used in the range 000 ₁₆ to 00F ₁₆
Performs channel number conversion for any CPU channel number within. In the CPU architecture, the CPU channel number determines the location of dedicated memory on one bus. Channel 0 uses locations 0 to 255, channel 1 uses locations 256 to
511, etc. Typically, the lowest priority CPU on a bus is assigned channel 0, and the next highest priority CPU on the bus is assigned channel 1. If the same channel number assignment occurs on more than one bus, this CPU's channel number must change to avoid conflicts. In FIG. 13, the flow of information for channel number recognition and modification is shown for two cases. That is, when a bus cycle request is initiated by a local communication bus, and when a local response to a remote bus cycle request occurs. In the first case, a single destination channel number is provided by address bus 96 to channel number mask RAM 142 and CPU destination RAM 131 according to the format shown at 156. Channel mask RAM 131 has hit bits to indicate whether the local ISL device accepts a particular channel number. A channel number change table is stored in two 16x4 bit RAMs, one on the local ISL device and one on the remote ISL device. RAM located on local ISL device
is the CPU destination channel number change RAM, that is, R1
It is called 31. Placed on remote ISL equipment
RAM is CPU source channel number change RAM i.e.
It is called RAM113. In the second case, where a local response to a remote bus cycle request is made, the source channel number is provided by data bus 91 to the CPU source channel change RAM 113 of the remote ISL device. Each ISL device also includes one channel number selector. In FIG. 13, the local ISL device includes one channel selector 157 and the remote ISL device includes one channel selector 158. Either an unchanged channel number for a non-CPU channel number or a modified channel number for a CPU channel number is selected. A modified channel number is selected whenever one of the following three conditions occurs: That is, (1) the CPU channel number on the address bus is changed by the destination change table. (2) While a CPU interrupts another CPU, the CPU channel number on the data bus is converted by the source change table. (3) “Output interrupt control command”
CPU channel numbers that are on the data bus as part of the data bus are translated by the origin change table except when directed to the ISL. The format of the destination and source channel number information provided by the remote ISL device to the telecommunications bus is shown at 159 and 160, respectively. There are four conditions under which CPU conversion occurs. In that first condition, the local communications bus device may attempt to interrupt the CPU on the remote communications bus. At the same time, the local ISL device initiates a local RRQ retry request cycle upon detection of a hit bit in the addressed cell of channel mask RAM 142, if location zero in file registers 92 and 103 is blank. Start. ISL interface output driver 139 is loaded from internal data multiplexer 129 whose I1 input receives data from data file transmitter register 121. Bits 0-13 and 18-23 of ISL interface output driver 115 are loaded from address file register 103, bits 14-
17 is loaded from the CPU destination RAM 131.
The RAM 131 further includes a file register 103.
CPU address that receives the output of bits 14 to 17 of
Addressed by register 114. The second condition occurs when the I/O command to the telecommunications bus device consists of function code 03. Such function codes identify output interrupt control instructions. During a remote RRQ cycle, bits 6-9 of bus 117 are provided via register 136.
Address RAM113. The output of this RAM is sent to data multiplexer 137, multiplexer register 138, and transceiver 1.
41 to the local bus. Thus, RAM 113 replaces data bits representing CPU channel addresses in interrupt control information provided to devices on the telecommunications bus. In the third condition, CPU source conversion RAM1
The information flow is identical to that of condition 2, except that 13 indicates the source CPU channel address in the local CPU's data field for the remote CPU interrupt. That is, the data field in the interrupt command contains the address of the source of the interrupt and interrupt level information. The fourth condition is that the I/O for the telecommunications bus device is
This occurs when the O command is found to have function code 02, which identifies an input interrupt control command. remote ISL generated in response to a second half-bus cycle from an addressed device on the telecommunications bus
During a local RRS retry response cycle at the device,
Data File Transmitter Register 1
Data bits 6-9 from 21 are routed to CPU destination RAM 13 via CPU address register 114.
given to 1. The output of RAM 131 is loaded into bits 6-9 of ISL interface driver 139. Bits 6-9 are remote interrupts.
Represents the CPU address. Again for sending I/O commands through the ISL device, an interrupt is generated by the CPU or
It should be understood that this is a cycle issued for In particular, during a BSDCNN cycle, address information received from the local communication bus by transceiver 98 is stored in channel address register 1.
Channel mask RAM 142 given to 01
Address one of 1024 locations in .
If the output of RAM 142 converts to a logic one level, the local ISL device of FIG. 8 becomes an agent for the BSDCNN cycle. especially,
CPU addresses occur between hexadecimal numbers 00 and 0F.
When the output of the RAM 142 changes to a logical 1 level and the upper six bits 0 to 5 of the address information on the bus 96 are zero, the slave becomes the CPU.
Since such an occurrence occurs in a bus cycle other than the second half bus cycle, this cycle becomes an interrupt cycle. Thus, if the local ISL device receives the address of the CPU of which it is an agent, this bus cycle must be an interrupt cycle. During a given interrupt cycle, the CPU address can be changed. When a local ISL device becomes the agent for an interrupt cycle, the local ISL device's control logic waits for the next RRQ cycle. Local ISL device
Upon entering the RRQ cycle, the remote ISL device receives changed addresses and data from the local ISL device. This modified address is applied to the telecommunications bus to interrupt the addressed CPU. At the same time, the CPU ACKs or NAKs this interrupt. This ACK or NAK is returned directly to the local ISL device by bus comparator 93 as described above. If the local ISL device's retry path is in use servicing a previous command, the interrupt cannot be processed. Therefore, the ISL device NAKs the interrupt request and then generates a resume interrupt command to the local bus when the previous command is completely serviced. At the same time, the local bus again issues an interrupt request to the adjacent ISL device. If the interrupt is not NAKed, the interrupt action prevents the CPU from taking any more communication bus cycles. In the case of multiple CPUs, an ISL control command called NAK RETRY is given to allow for a condition where the higher priority CPU issues a request after the lower priority CPU has had one bus cycle to wait for a response. given for. This NAK
The RETRY response satisfies the higher ranking CPU and temporarily allows the lower ranking CPU to complete its task. This allows for
A deadlock that freezes the ISL communication path is prevented. A certain CPU where the command CPU interrupts the PCU
There are two CPUI/O instructions that identify the address of the interrupt and the priority level of this interrupt. These two instructions are an output interrupt control instruction and an input interrupt control instruction. If the command CPU is on one communication bus and the PCU is on another communication bus, such interrupt control information must be changed.
CPU source change RAM 113 and CPU destination RAM 13
1 allows changing of interrupt control information. As mentioned earlier, the flow path of this changed data is based on condition 2.
This is related to condition 4, the CPU change. To complete the description of the information transfer mode of the ISL device of FIG. Let's understand and explain. Function decoder PROM10
2 is bits 18 to 23 of address information on bus 96.
decodes local communication bus commands for ISL devices that appear in Such directives may
Can be received during ISL configuration mode. However, in the information transfer mode, bus commands may include input status, input ID code, reset timer/interrupt mask, and output control word commands. All bus commands are responded to in ISL configuration mode, as described below. Table 5 is a decoding table for the functional decoder PROM 142.

【table】

【table】

【table】

【table】

【table】

【table】

【table】

【table】

Mode control register 135 is loaded during execution of control word commands, which are further described for either the information transfer mode or the ISL configuration mode of operation. Timer and status logic 133 includes:
Internal supervisory timers for ISL devices, I/O time-out devices, ISL bus cycle time-out devices, and communication bus cycles encountered only when the ISL device is attached to a communication bus that does not have a CPU. - Contains a time-out device. The timer device generally makes the ISL device transparent to the actions of the communication bus. Logic state 133 further comprises a status bit generator that indicates the mode of operation of the ISL, the clocks that are enabled, the presence of interrupts, the interrupt type, etc. Interrupt channel register 132 and interrupt level register 134 are loaded during output interrupt control instructions to the ISL device. The interrupt channel and level registers 132 and 134 are used by the ISL device during interrupt generation. Interrupt channel register 132 is a 4-bit register that indicates the address of the CPU being interrupted. Interrupt level register 134 is 6
It is bit wide and indicates the priority level assigned for the interrupt. The CPU on the communication bus can detect the interrupt level and control internal software operations for the CPU. When the CPU is interrupted, the output of interrupt channel register 132 is provided to the I2 input of address multiplexer 112. The output of multiplexer 112 provides the address of the CPU to be interrupted via multiplexer 111 and transceiver 123. Therefore, bits 6 through 9 of the address bus are surplanted with 4 bits from the interrupt channel register 134. register 134
The output of is the input I2 of data multiplexer 129
via data multiplexer/register 138
given to bits 10 to 15. Multiplexer/
Bits 0-9 of the register are provided by hex rotary switch 140 and signal to the interrupted CPU that the ISL device is the interrupting device. In response to the mask address instructions further described, RAM counter 118 and RAM control register 108 are loaded with addressing and writable information for each of the hit bits and modified RAM. The output mask data instruction loads modified data into the modified RAM location addressed by the output mask address instruction. Cycle generator 146 comprises decision control logic for selecting operating cycles and generating timing signals to control operation of the ISL device during the selected cycles. The cycle generator receives two inputs. The first is remote
It is a remote cycle signal on line 143 extending from the ISL device. The second input is the file register activity 2D0 bit carried by line 144 which indicates the local ISL device cycle request. In response to these two inputs, cycle generator 146 provides timing signals to control the operation of the ISL device. The I/O load (IOLD) register 127 is
When an I/O load command is issued to the controller, it is loaded with the address of the translated storage module. The I/O load command consists of two subcommands: a storage address and a storage range command. The storage address portion of the I/O command requires a storage conversion. Thus, conversion bits from RAM 125 are loaded into the IOLD register in response to an I/O command. In the further discussion of the operation of an ISL device in response to an IOLD command, storage locations will be described in terms of storage module addresses. A module address is a translation bit of a storage address. For example, one local storage device has 32.0K bits of memory, consisting of four modules of 0.8K storage locations each. Thus, one local storage device has module addresses 0, 1, 2,
3 will be responded to. In the presently preferred embodiment, both the local and remote communication buses have storage devices each including four storage modules. Furthermore, local and remote ISL devices are configured to provide visibility to each communication bus. Thus, each bus provides access to eight storage modules of memory. When a CPU on a local communications bus commands a peripheral control unit (PCU) on a remote communications bus to communicate with a storage module on a remote bus, the local CPU
Issue an IOLD command to the PCU. The IOLD instruction specifies a storage module address above any storage module available on the local bus. In this manner, the local ISL device responds to the channel hit bit in RAM 142 corresponding to the remote PCU by registering the address bits on bit lines 0-7 of address bus 96 and bit lines 0 and 1 of data bus 91. is used to address the storage conversion RAM 125. At address locations in RAM 125, converted storage modules of remote PCUs are stored. This translated address is
Transferred to the IOLD register 127 for transfer to the remote ISL device during the RRQ cycle. remote PCU
receives this translated address and at the same time,
Directly access remote storage modules. When the local CPU commands the remote PCU to communicate with the local storage module, the local CPU issues an IOLD command to the local ISL device. The local ISL device accepts commands and sends 24 signals on buses 91 and 96.
The bit address is used to address RAM 125. RAM output is IOLD register 12
7 and later sent to the remote PCU as described above. The remote PCU also addresses a storage module that has a higher address than any storage module on the remote bus. The remote ISL device is configured to translate a storage module address provided by the remote PCU to a storage module address on the local bus with which the remote PCU is commanded to communicate. The only difference between the IOLD command and the standard I/O command is the input path to transceiver 115.
In the IOLD instruction, bits 0-9 are provided by register 127 rather than register 126. An IOLD command is accepted by an ISL device whenever it addresses a channel number recognized by channel mask RAM 142. ISL devices perform translations on the address portion of the IOLD instruction. The format of the IOLD instruction is shown in Table 6.
This conversion is performed on the most significant 10 bits of the address contained in bits 0-7 of address bus 91 and bits 0 and 1 of data bus 96. The most significant ten bits of the address portion of the IOLD instruction are replaced by the contents of the addressed location in storage address translation RAM 125. During the initial setup operation of the ISL device, storage address conversion
RAM 125 is loaded with all logical ones. The CPU software on the communication bus only needs to load those specific RAM locations where IOLD instructions are expected to be addressed. If the IOLD address falls outside the specified location, this address is translated to an address between 8.0 million and 8.0 million minus 8.0K words. Unless the addressed memory is used on a system containing ISL devices, programming errors
Leading to the illegal resource situation from the O controller. Two cases can be considered when configuring an ISL device to handle IOLD instructions. In the first case, the controller is issued on the local bus which checks the storage module of the local bus.
Accessing storage modules on a remote bus in response to an IOLD command. The address translation location in RAM 125 that corresponds to the local storage module must be loaded with the most significant bits of the remote bus storage module. The controller then probes the IOLD storage address on the remote bus.

It will be appreciated that the hit bit for the remote storage module in RAM 125 has no effect on IOLD address translation. If there is a logical zero hit bit at the addressed location, storage is physically present on the local bus. If there is a logical 1 hit bit, the storage module is visible to the CPU on the local bus, but is not physically located on the remote bus. In the second case considered here, the remote controller accesses a storage module on the local bus in response to an IOLD command on the local bus. Since there is actually a storage module on the local bus,
RAM 125 issues a logic zero hit bit.
It can be seen that in this case two address translations are required. IOLD once for remote controller
Once the command is transferred, it allows the remote controller to access local memory. In the ISL configuration mode, the ISL device responds to a total of nine I/O commands that transfer data to and from the ISL device. Table 7 shows this I/O command. In configuration mode, no data transfer occurs between the communication buses. Rather, ISL devices are loaded in configuration mode to enable communication between buses in ISL information transfer mode.

For ISL devices, an active/passive state switch is internal, which will be further described in connection with the description of FIG. This switch controls the visibility of the ISL device to configuration commands. The effect of the switch on the ISL device's acceptance of local and remote bus commands is shown in FIG. 8 and discussed below. In the active state, the ISL device responds to configuration commands received in the ISL configuration mode. If in the passive state, the ISL device will only respond to the selected configuration mode command. Through the use of active/passive state switches, local and remote ISL devices can be configured from one bus or separate buses. In the following discussion, a cycle is local when generated from a communication bus. However, when a cycle is generated from an internal ISL interface, this cycle becomes remote. When a bus command is issued to an ISL device, the detection of this ISL device is the address at address comparator 99, which decodes the 6-bit function code on bus 96 in PROM 102. PROM10
The two 4-bit outputs are held in output registers for internal use. The ISL address comparator 99 signal sets the RRQ activity 2D0 bit and all bits, thereby starting a local RRQ cycle that is used to control the flow of data for all ISL commands. The RRQ cycle activates function code detector 106. When an output bit of PROM 102 is provided to decoder 106 by address bus 105, one of the possible 16 output control lines is activated to initiate a particular command to be executed. The ISL Directive has one, two, or three internal
Gives rise to an ISL cycle. A local input or output command initiates one RRQ cycle in which data is loaded into a specific register and
Or read from a specific register. An input command also requests data.

【table】

[Table] One (BSSHBC) second half bus generated by the local ISL device to the master CPU.
give rise to a cycle. A remote ISL output command results in two cycles. The first cycle is the data
Data from file register 92 is standard
A local RRQ cycle that is forwarded to a remote ISL device as in an RRQ cycle. Furthermore,
Bus 10 containing function codes from PROM 102
Information regarding 5 and other function code specific information may be further transferred to the remote ISL device.
device 115. The second cycle is remote
occurs to the remote ISL device as an RRQ cycle, during which data is transferred to the local ISL device's buses 105 and 117.
is stored in the same way as information that occurs in Remote ISL input commands require three cycles. The first cycle is the same as the output command. The second cycle is such that data is read from a particular register and presented to a data bus corresponding to bus 117 at the remote ISL device, and is localized by driver 139 and the corresponding interface driver.
It is the same as for output commands, except that it is forwarded to the ISL device. At the local ISL device, data is received by data receiver 116 during remote RRS cycles. The RRS cycle transfers data to the local bus to data multiplexer 129 and data multiplexer 129.
to be transmitted to data transceiver 141 via. Retrieves address information from data file register 92 and transfers address information to transceiver 1 via address multiplexer/register.
Given to 23. As mentioned above, each ISL device has a channel number that is used when the CPU addresses the ISL device. However, when a command is to be sent to an ISL device, the CPU destination channel number is used. A CPU on a particular bus can address a local ISL device on a local bus or a remote ISL device through a local ISL device. The channel number for each ISL device is determined by a DIP switch. Therefore, in principle, Table 7
ISL commands are valid for any ISL device and can be issued from either bus. Active/passive switches in each ISL pair allow the ISL devices to be controlled from the local bus or not. The first bus command described below is an output control command having function code 01 as shown in Table 7. The command word data fields include data transfer/configuration, initialization, stop, resume, NAK/
RETRY, and test mode control including the modes shown in Table 9, where
indicates either a possible logical zero or logical one. There are two test mode bits, bits 2 and 3. One bit indicates the memory verification mode and the other controls the ISL device's response to local or remote bus cycles.

【table】

[Table] System initialization is controlled by bit 0 of the control word command. This bit is sensed by master clear generator 94.
Clear ISLRAM. Bits 0 and 1 of the control word command cause the ISL device to enter a non-data transfer state while servicing an existing request.
Thus, if an ISL device confirms that it is acting as an agent for a communication bus cycle, it continues to service this request until all communications necessary to satisfy the request are completed. Other data transfer requests that occur after the configuration mode command is initiated are ignored. This directive places the ISL device in a mode that allows it to service standard communication bus requests. In the case of a multiple CPU system, the NAK/RETRY logic is initiated by bit 4 of the control word command to NAK a higher priority CPU causing the ISL data transfer to continue for the lower priority CPU. Control word commands are assigned the highest priority in ISL systems because they control modes of operation. However, this control word command can only be issued when the ISL device is active. In the passive state, the ISL device does not accept output control commands. As previously mentioned, the output control command takes two cycles to load the mode control register 135 to the local and remote ISL device partners. The output interrupt control command with function code 03 is
Loads registers 132 and 134 with interrupt data only when active in configuration mode. if
This command is not accepted if the ISL device is in the passive state. Output interrupt control commands can be local or remote
can be issued to any of the ISL devices,
One or two cycles are required as described above. This command is a 16-bit command that interrupts the level used by the ISL device to identify the CP channel number and interrupt the CPU. This Directive has the following format:

[Table] Register 132 is set when an interrupt condition is encountered.
The ISL device is loaded with the 4-bit address of the interrupting CPU. The most significant six bits of a CPU's address are always a logical zero. register 134
is loaded with a 6-bit field indicating the interrupt level used by the interrupted CPU in defining interrupt priority. Function code 27 reset timer command is:
Controls resetting of all timer status bits. This directive further provides for enabling or disabling local or remote monitoring timers; enabling or disabling I/O or retry timers;
Controls the enabling or blocking of ISL interrupts. Memory timers are always enabled. When one of the timer errors is activated due to the occurrence of an error, the timer must be reset by a reset timer command. As previously discussed, the output timer data and status information companions are loaded into logic unit 133. This allows the logic device to display the operating status of each timer. The reset timer also turns the supervisory timer on and off while in data transfer mode or configuration mode, or in active or passive states.
It can be used to switch to . If the timer is not strobed within a predetermined period, a higher priority interrupt is handled within the CPU's interrupt architecture. If the logical decision flow cannot get out of the CPU's control loop,
A watchdog timer cannot provide a means of exit. In the preferred embodiment described herein, there is a local monitoring timer and a remote monitoring timer. Each timer and future interrupts are controlled by the CPU. Reset timer can be local or remote
assigned to any of the ISL devices and generates one or two cycles as described above. The format of the reset timer command is specified in Table 10 below.

[Table] The output mask address command with function code 0B and the output mask data command with function code 11 are stored in the storage address conversion RAM 12.
5. Channel mask RAM 142 and CPU
Begin ISL configuration by writing to translation RAMs 113 and 131. When the output mask address command is active
Can be issued to an ISL device or only to a local ISL device. Thus, only one cycle is required as described above. The output mask address command loads RAM counter 118 with the address and writable information for the particular translation RAM into which the data provided during the output mask data command is to be written. In particular, RAM counter 1
18 is storage address translation during ISL configuration period.
RAM125, channel mask RAM142,
CPU destination RAM131 and CPU source RAM1
13. The address of the RAM location to be modified is stored in RAM counter 118 and RAM control register 108
given to. Register 108 is a tristate device that interfaces with address bus 105. Memory address conversion using register contents
RAM 125, channel address register 101, CPU address register 114,
CPU address register 136 is addressed. This allows data appearing on data bus 117 to be written to the addressed location. Output or input mask data command is counter 1
Increment 18. Counter in use, ISLRAM
Consecutive locations can be addressed without having to issue the output mask address command again. The counter facilitates this operation by addressing sequentially from the starting location. When an output mask address command is issued to the local ISL device, the data received from the local communication bus and stored in data file register 92 is routed along bus 117 via register 121.
It is applied to the input side of RAM counter 118. As previously mentioned, the 10 bits of the storage address are used to address 1024 locations in memory by the storage address multiplexer 100 and channel address register 101. The 13-bit input to RAM counter 118 is input to RAM 14.
2 or 125, and the ability to write to any or all of the translation RAMs. The lower 4 bits are
Used to address RAM 131 and 113. Bits 3, 4 and 5 of bus 117
represents a write enable signal. Bits 3, 4, and 5 of bus 117 are RAM
When applied to bus 105 via counter 118 and RAM control register 108, these become address bits 5, 6, and 7, respectively. address·
Bit 5 enables writing to CPU RAM 131 and 113. Address bit 6 enables channel mask RAM 142 and addresses
Bit 7 enables storage mask RAM 125. Thus, in response to an output mask address command, the ISL device stores in counter 118 the RAM address at which data is to be written. For this purpose, bits 0 through 15 of data file register 92 are stored in counter 118. 16
Of the bits, 10 bits represent the RAM address and 3 bits are write control bits. The Output Mask Data command, which is issued in the active state only during configuration mode, provides the data to be written to the locations addressed by the Output Mask Address command. This output mask data is issued to either a local or remote ISL device and
Requires one or two internal cycles as described above. In response, the data stored in data file register 92 is provided to data bus 117 via register 121. Function code information is provided by PROM 102 and decoded by function code decoder 106, as described above. The output of decoder 106 is used by local control logic to write data on bus 117 to one of RAMs 142, 125, 113, or 131.
order it to be sent to. The starting address of the identified RAM location to which data is to be written is identified by counter 118. This address is provided along bus 105 via RAM controller 108 to address one of the identified RAM storage cells. Thus, bits 5, 6, and 7 of the register output of counter 118 are
This serves as a usable strobe for RAMs 131, 113, 125 and 142. The specific timing of write operations is handled by cycle generator 146. A write pulse is generated for each enabled RAM of the local ISL device. This allows data to be written to any or all of the RAM. Either local or remote ISL devices can be loaded with an output mask data command. However, output/address commands are provided only to local ISL devices. In this way, if the data is localized from location zero
If written to RAM, no separate output mask address command must be issued to write to remote RAM from location zero. Only output mask data commands issued to remote ISL devices are required. Thus, the output mask address and output mask data commands work in pairs to create the four configurations.
Load RAM into ISL. The format of the command to load the storage address conversion mask RAM 125 is as follows.

【table】

[Table] Output mask address command is RAM counter 1
Establish 18 starting locations. This output mask data command loads a 10-bit quantity into the previously specified location and increments the counter. To load the next consecutive location, only an output mask data command needs to be issued. The Hm (memory hit) bits are initialized to all zeros and the storage mask data are all initialized to logical ones. In loading channel mask RAM 142, the command has the following format:

【table】

[Table] Output mask/address command is RAM counter 1
Establish 18 starting locations. This output mask data command loads the Hc (channel hit) bit to make the ISL respond to this channel number. Furthermore,
This output mask data command increments counter 118. Only an output mask data command needs to be issued to load the hit bit into the next consecutive location. CPU conversion RAM, i.e. RAM131 or 113
To load the output mask address and mask data commands have the following format: That is,

【table】

[Table] The output mask address command identifies the CPU channel number. This output mask data directive is
Specifies the value to which a channel number is converted when passing through an ISL device. Additionally, the output mask data command increments counter 118 to the next consecutive value. Next, input commands will be explained. The input interrupt control command, function code 02, is similar to the output interrupt control command. This command requires one or three cycles for local or remote ISL commands, as described above, and the ISL device must be in configuration mode and active. However, instead of interrupt channel register 132 and interrupt level register 134, the command sends data to internal data multiplexer 129. The data is then transferred to multiplexer 129 and transceiver 1
38 to data transceiver 141. The contents of data file register 92, including the address of the master device, are passed to address transceiver 123 via address multiplexer/register 111. The input interrupt control command causes the ISL device to present the contents of interrupt registers 132 and 134 to data multiplexer 129. Interrupt channel register 132 provides four bits indicating the CPU channel number, and interrupt level register 134 provides six bits of interrupt level information. The format of this command is the same as for the output interrupt control command. The input mask data command for function code 10 is:
Causes the ISL device to read the contents of the storage cell previously addressed by the output mask address command. In particular, the local control logic includes counter 118.
Detects the address loaded into each RAM11.
Start reading 3,125,142. One channel mask bit is read from RAM 142, ten storage translation bits and one hit bit are read from RAM 125, and four CPU
The specified bits are read from RAM 131. Thus, a total of 16 bits are provided via the transceiver to either the local or remote communications bus. The input mux data is issued to the local and remote ISL device partners, thus resulting in one or three cycles as described above. The input mask data command also provides the ability to increment the RAM counter 118 to notify when it is loaded with the first count. RAM location zero can be read first, followed by 1024 input mask data command reads from a total of 1024 locations. Because the RAM data must initially be hex 03FF, the other data indicates that a translation or hit bit is present at the addressed memory location. The ISL must be in configuration mode and active. The format of the input mask data command compared to the output mask address command is as follows. That is,

【table】

TABLE The output mask address command sets the starting location in counter 118. The input mask data command provides the contents of the addressed location and increments this counter. To read the next location, only an input mask data command needs to be issued. The input mask data command returns the contents of all ISL configuration RAMs at the same time. For a specific address, the corresponding storage translation address,
The Hm (memory hit) bit, Hc (channel hit) bit, and CPU conversion channel number are returned.
Since the CPU channel number conversion memory only has 16 locations, an output address of 0 returns the same location as 010 ₁₆ , 020 ₁₆ , etc. The input status word command of function code 18 causes the status bits stored in logic unit 133 to be read. This determines the state of timers, the occurrence of ongoing interrupts, and the logical state of ISL devices. Status word commands are issued in either data transfer or configuration modes, and in either active or passive states. This status bit is shown in Table 11. Yet another input command is the input device identification (ID) command, which is issued in either information transfer or ISL configuration mode and in either active or passive state. The ISL ID is a fixed number that is the same for each ISL device regardless of its address. This command is unique in that only the local ID is read whether a local or remote ISL device is addressed. However, even if the remote ISL device is not electrically connected to the local ISL device, the ID number read to the local bus will be, for example, 2400 hex.
Even if each ISL device is electrically connected and powered, this ID number will be, for example, 2402 in hexadecimal.
In this way, input device ID commands can be used by diagnostic programs to identify local and/or remote ISLs.
Determine whether the device is connected. A more detailed discussion of test mode operation of ISL equipment is provided below. In the output control word instruction, there are two tests or rotation mode bits as described above. Bit 2 is called the total test mode bit and bit 3 is called the remote test mode bit.
This is called a mode bit. Total test mode
Once the bit is set, each ISL device will
Enter the mode. However, when the remote test mode bit is set, only remote ISL devices are affected. In test mode, one of two logical paths is used. When the total test mode bit is set, the memory wrap logic path is used. The I/O wrap logic path requires both the total test mode and remote test mode bits to be set. In the storage wrap logic path, local and remote ISL devices must be configured to operate on addresses issued by the local communication bus.
In particular, when the CPU issues a memory verification command to the local communication bus where an address other than a local memory address is displayed, the local ISL device forwards a translation of this information to the remote ISL device. If the displayed address is configured in the remote ISL device, the remote ISL device returns this information to the local ISL device. This initiates a loopback and changes the information in the local ISL device to provide it to the local bus again. It will be appreciated that local and remote ISL devices can be configured to recognize storage addresses and act as agents for associated storage cycles, even though the storage addresses may reside on either local or remote storage buses.
Therefore, the ISL device issues an ACK in response to the storage address as described above.

【table】

[Table] Test mode is unique in that it allows local and remote ISL devices to be dynamically tested without interrupting system operations on the telecommunications bus. No devices on the remote bus are used and no more than one bus cycle is lost. Another feature is that the task in progress cannot be interrupted before completion. When I/O wrapping tests are performed, the same logical paths are not used for data. but,
The ISL cycles generated on ISL devices are different. Additionally, instead of the storage address register 100 and storage address translation RAM 125 used in the storage wrapping test, the channel address
Register 101 and channel mask RAM1
42 is used. In operation, an I/O command is issued for the channel number. Channel numbers are not translated because they are supported by I/O requests rather than storage requests. instead of,
A channel number that does not indicate a channel number on the local or remote bus is translated into a storage address on the loop back to the telecommunications bus. When reading or writing to local memory, the storage request is forwarded through the local ISL device to the remote ISL device and back to the local ISL device. It will be appreciated that if the selected channel number occurs on either the remote bus or the local bus, the ACK will be generated outside the ISL device. Thus, the channel number recognized by either the local or remote bus must be provided to channel mask RAM 142. The RAM can be configured to recognize this channel number so that the channel is transferred from the local ISL device to the remote ISL device and then back to the local ISL device. The channel number containing the remainder of the address bus information must be translated into an actual storage address on the local bus for a successful test to be detected. A test mode bit set to initiate an I/O wrap test also converts the memory check line in the local control logic to a logic one state. Thus, when return information is received at receivers 104 and 115 from remote ISL devices and loaded into multiplexers 111 and 138, the address information, including the channel number, becomes a storage address. This causes memory locations on the local bus to be read or written to perform logic testing. The difference between the memory wrap test and the I/O wrap test is that only memory-to-memory cycles MRQ and MRS are used during the memory wrap test.
However, during I/O wrap tests, internal cycles RRQ and RRS are used. Storage cycles are always acknowledged, but I/O cycles are not initially acknowledged. Instead, local RRQ at the remote device
WAIT is issued before the cycle occurs. Remote
As a result of RRQ local in ISL equipment, local
A remote RRQ cycle is generated at the ISL device. Upon occurrence of a remote RRQ cycle at the local ISL device, the I/O command is translated into a storage address from local storage and transferred from the local ISL device to the remote ISL device. Comparator 99 and corresponding remote
The equal result on the ISL device's bus comparator causes the remote ISL device to forward the ACK from the remote bus to the local ISL device. Local ISL device bus
If the results at comparator 93 are equal, then
An ACK is sent to the local bus. At the same time, the CPU on the local bus that initiates the RRQ request is satisfied and RRQ request generation is stopped. Thus, it is clear that two foldback tests are performed to test the local and remote ISL logic. One test is performed in response to an RRQ request, and another test is performed in response to an RRQ request. Again for ISL configuration mode, if the ISL device
It will be appreciated that this is configured through the use of the O output command. In particular, the control word command loads the mode control register 135, the interrupt control word loads the interrupt channel register 132, and the reset timer command loads the timer and status logic 113. Furthermore, the output mask address command is RAM
The counter 118 and RAM control register 180 are loaded. The output mask data command is used to load data into ISL RAM. Data loaded into the ISL device during ISL configuration can be examined through the use of I/O input commands. Each ISL device includes five timers, further described in connection with the description of FIG. 14, for the purpose of detecting and clearing stop conditions. The timer is reset by the reset timer command previously described. If the second half bus cycle from memory does not occur within a predetermined period of time as indicated by the memory stop timer, the ISL completes the read request by sending an invalid data word to the requesting device. In the preferred embodiment described herein, a predetermined period of approximately 6 microseconds is used. If the second half bus cycle from the I/O controller does not occur within, say, about 200 milliseconds, then
The I/O stop timer signals the ISL device to complete the input request by sending a meaningless data word to the requestor and setting the invalid data parity and RED indicators. I/O
The stop timer is enabled by the reset timer command. If the local bus cycle is not completed within 7 microseconds, a dead man timeout signals the ISL device to NAK.
This is a service to the bus, not to the ISL device, and is intended for these configurations where the bus does not contain a CPU. A NAK produces the same effect as an illegal resource NAK, and may cause additional actions within the ISL if the ISL device is parity to the cycle. A watchdog timer is provided to facilitate the use of ISL equipment in redundant systems. When the timer is turned ON by an I/O command, the timer produces a logic 1 signal unless the timer is reset more frequently than once per second at 60 Hz. When the timer produces a logic 1 signal,
Local and remote buses are interrupted. Supervisory timer interrupts can be blocked by proper setting of the reset timer command. The retry stop timer is started when the ISL device first generates a WAIT signal as a result of a retry and is reset when an ACK or NAK occurs.
If, for example, more than 100 milliseconds elapse and the retry cycle is not completed, the ISL device will not respond to further bus cycle requests from the original master. The bus times out and the original cycle is now known to have stopped. The timer is enabled under the control of the reset timer command. Each of the timers controls the logic level of a status bit as shown in Table 11. Each ISL device has a timer and status logic unit 13
It has a status register at 3. The local status register contains information for the local ISL device along with composite status bits representing certain conditions at the remote ISL device. If the remote interrupt bit in the local status register is at a logic one level, the local
Detailed status is obtained by reading the remote status register via the ISL device. Three mask bits are provided to block certain interrupt and status conditions. These mask bits are used to reset the reset timer/interrupt remask command (F
=27). Figures 14A to 14Z, Figures 14AA to 1
4AC Diagram FIG. 14 shows one ISL device in a detailed logic diagram. It will be appreciated that logic systems with ISL devices are distributed within the device and share common logic elements. In an attempt to explain the connection of logic elements to an ISL device, it will be readily seen that the conductors for the inputs and outputs of the logic elements extend to other logic elements distributed in FIG. 29 making up FIG.
The result is not meaningful instructions on how to configure the ISL device, but rather a large number of conjunction displays that require an excessive amount of time to decode and organize. In order to provide a meaningful description by which the connections of the logic elements in any of the figures may be easily ascertained and organized, two computer lists, included herein as Appendices A and B, are particularly useful.
Intended to explain Figure 4. Additionally, the logic elements of FIG. 14 are numbered according to the numbering rules that capture the information in Appendices A and B. For example, each component is identified by three digit numbers. Each component receives one or more signals and produces one or more output signals. Each signal is identified by five digit numbers. The first three digits of each signal identify the component on which the signal is an output. The last two digits identify the pin number of this component's output. Each signal has a nine character mnemonic that functionally names the signal and two digit numbers that identify different signals having the same mnemonic. Each signal also has a (+) or (-) indicator to identify the condition that makes the mnemonic true, and two decimal digits to differentiate between each signal with the same six-character mnemonic. . For example, in Figure 14M, the inverter
74LS04 is identified by three digit numbers 641. The output signal appears on pin number 04. The output signal is identified as 64104. The input signal connected to input pin number 03 is identified by number 64013. This is generated by an integrated circuit NOR gate 640 designated 74S02. Output signal is pin number 13
occurs in The shorthand symbol for the write interrupt function is
It is WRTINT. Signal number 64013 is a simple symbol
Has WRTINT-00. The minus sign is the signal 64013 when the system implements the write interrupt function.
indicates that it has a logical value of zero. Similarly, the signal
64104 has a simplified WRTINT+10. A positive signal is the signal when the system performs a write function.
Displays that 64104 is a logical value of 1. display 00
and 10 identify different signals with the same mnemonic. Appendix A is separated by five digit signal numbers and has six columns. The first column identifies the signal. The second column identifies the mnemonic. The third column lists the three digit reference numbers and the two digit pin numbers. The fourth column is column 5

【table】

[Table] and terminal program
For example, on line 64013 in column 1, 64013 is the signal number.
This is the number. WRTINT-00 in column 2 is a mnemonic.
Ru. Signal number 64013 is repeated in column 3.
S in column 4 is the source (from gate 640, pin 13)
Display. Number 74S02 in column 5 is the component
640 manufacturer's identification number. Column 6 characters
06Z is ignored. Character 13 corresponds to the sheet shown in Table 12.
It is called the port number. In Table 12, sheet number 13 is
Corresponds to Figure 14M showing interrupt control logic
do. On the line following signal number 64013, columns 1 and 2 are
It is blank. Number 64103 in column 3 is component 6
It is called pin 03 of 41. Column 4 is the letter L and signal 64013
is connected to the 03 input pin of component 641. column
The number 74S04 in 5 is the manufacturer of component 641.
This is the side identification number. However, character 13 in column 6 is
12 to identify Figure 14M. Annex B is stored by the mnemonic in column 2 and contains 6
It consists of a column of The first column lists signal numbers.
The second column identifies the signal mnemonic. third column
lists the signal numbers. The fourth column is in column 5.
A component is given a source (S) or load (L)
or the connector provides input (I) or output (O).
Displays whether the Also, terminal (T)
and wired OR gate (W) can also be displayed.
Column 5 is the circuit component by manufacturer's catalog number.
identify. The first three characters of column 6 are not used.
stomach. The last two letters are used in conjunction with Table 12,
Figures 14A-14AC where the components are found
Identify the diagram. For example, indicated by the signal mnemonic symbol WRTINT-00.
In rows 1 and 3 of the line, signal number 64013
is given. In column 4, the letter S is
640 is the source of signal 64013.
In column 5, number 74S02 is the main gate of gate 640.
This is the identification number of the manufacturer. In column 6, the character
06Z is ignored. In Table 12, character 13 is
14 Identify the M diagram. WRTINT - on the line after 00
In this example, columns 1 and 2 are blank. Column 3 number
64103 is the signal number, which is also the reference number 641.
Identify the component with component connection pin 03
Ru. The character L in column 4 is composed of signal 64013.
Indicates that it is applied to the input pin of 74S04. Column 5
The number 74S04 is the manufacturer's identification for gate 641.
It's a different number. In column 6, character 07D is ignored and
Letter 13 identifies Figure 14M of Table 12. As yet another example, in FIG.
Signals with the abbreviation AFIL10+00 and the abbreviation
Signal 83509 with RMAD10+00 and mnemonic symbol
Signal 74105 with CNTL10+00 is wired OR
is applied to gate 142. Wired OR gate
142 output has the mnemonic symbol ADDR10+00
Signal 14201. In Figure 14-0, the abbreviated symbol AFIL10+
Signal 16306 with 00 goes to pin 06 of RAM 163
This is the output of In Figure 14Z, simplified
Signal 88309 with symbol RMAD10+00 is the driver
This is the output signal at pin 09 of the 883. 14th
In the Q diagram, it has the abbreviation CNTL10+00.
The signal 74105 is the output on pin 05 of register 741.
It's a signal. In Appendix A, columns 1 and 3 are simplified for line 16306
Identify signal 16306 with symbol AFIL10+00.
The letter W in column 4 indicates that signal 16306 is wired.
Connected to OR gate. In column 5, the signal
is generated by the 74LS670 circuit element.
ing. In column 6, character 08A is ignored and table 12 and
Associated letters 16 identify Figure 14-0. next
In the line, columns 1 and 2 are blank. Column 3 is wai
The add OR gate is identified as gate 142.
Number 02 connects the wire to the second wire rat on the pin.
identified as a group. In column 4, the letter L is
No. 16306 is input to wired OR gate 142.
Identify as power. In column 5, the character +W003 is the word
IAD OR gate wrapped around one pin
3-input wired OR gate consisting of 4 wires
. The wires are 01, 02, 03, 04.
It is identified by Column 6 shows the wired OR gate.
See sheet number 06 in 12 and the associated diagram.
Show that it can be released. This figure shows the 14th floor.
It is a diagram. Character 11A in column 6 is ignored. For line 14201 ADDR10+00, column 1 is configured
Identify the component reference number 142. Character 01 is pin
Identify the wire as the first wire wrap above.
Ru. Column 4 indicates that this signal is the source (S) signal.
and is displayed. Column 5 has the constituent elements as described above.
Identifies it as a 3-input wired OR gate. row 6
The wired OR gate is sheet number 06 in Table 12.
Indicates what may be found in the associated figures. character 11A
is ignored. Annex B indicated by the abbreviation AFIL10+00
For the line, columns 1 and 3 identify signal number 16306
It turns out that it does. In column 4, the letter W is
Identifying a signal as an input to an add OR gate
Ru. Column 5 takes the signal as the output of the 74LS670 circuit element.
and identify it. Character 08A in column 6 is ignored. Table 12
Letter 16 used in connection identifies Figure 14-0
do. In the next line, columns 1 and 2 are flanks.
Column 3 identifies wired OR gate 142. Sentence
Figure 02 connects the wire to the second wire wrapped on the pin.
and identify it. In column 4, L wipes the signal.
Identifies it as an input to an add OR gate. column
5 is a 3-input wired OR of circuit components + W003
Identify as a gate. In column 6, the character
11A is ignored. Statements used in conjunction with Table 12
The letter 06 identifies Figure 14F. For line ADDR10+00, columns 1 and 2 are signals
Identify number 14201. Column 3 connects the signal to component 1
42. Character 01 is
wire is the first wire wrap around the pin.
It shows. In column 4, S is the component
identify as the source. In column 5, the configuration
The element is a 3-input wired OR gate as described above.
It is identified by Column 6 is the wired OR gate.
Display what is shown in Figure 14F. signal 88309 with simple memory RMAD10+00;
Signal 74105 with the simple symbol CNTL10+00 is
Headings in Annex A and Annex B in accordance with the guidelines listed below.
can be done. Next, we will explain the functional explanation of the ISL device shown in Fig. 14.
do light work A logical system consisting of ISL devices is a device
Functional explanations are also distributed within the 14th
This shall be done regarding figures. The initial settings for the ISL are power up and master.
- clear phase, as shown in Figure 14L.
The logic diagram will be explained. Figure 14A shows the ISL theory
A connector that connects communication bus signals to a management system.
104 and 105 are shown. From the communication bus to the bus
A power on signal is provided to all devices.
The ISL logic includes delay circuit 250 in FIG. 14L.
Pass power on signal 10535 given to input
Detect the leading edge of. The delay circuit 250 has two outputs.
It has a delayed output of The first output signal 25003 is 30
Delay bus power-on signal 10535 by nanoseconds
do. The second output signal 25014 is buffered for 60 nanoseconds.
delay power-on signal 10535. signal
25003 and 25014 are applied to the input of OR gate 251.
available. The output of OR gate 251 is its leading edge
is 30 after the rising edge of bus power on signal 10535
Rise for nanoseconds, trailing edge bus powered on
Pulse dip for 60 nanoseconds after signal 10535 dip
Signal 25103. Output signal 25103 is positive signal 37005 and negative signal
Input side of one shot 370 that generates 37012
given to. Negative signal 37012 lasts 1.5 ms
This is the later pulse that becomes negative. Negative signal 37012 is D-flip-flop 531
is applied to the clock input side of Flop 531
is the bus power on signal 10535 in Figure 14A.
given approximately 1.5 ms after the leading edge of is detected.
Responsive to trailing edge of negative signal 37012. The output signal 53109 of flop 531 is an exclusive OR
It is applied to the input side of gate 290. Local communication bus
master clear signal 24305 is an exclusive OR gate.
is applied to another input of port 290. signal
24305 is the positive output of the D-flop 243. system
The master clear button on the control panel sends signal 10407.
Connector 104 to driver/receiver of Figure 14B.
server 242. Driver receiver 242
The output signal 24214 is output from the flop 243 in FIG.
is applied to the clock input side of Signal 93213 is far away
from the ISL to the CD input side of the flop 243.
It will be done. Signal 93212 is the master signal that occurs on the remote ISL.
- Flop 243 is set only when there is no clear.
ensure that the Bus power on signal or master clear
Either switch 24305 is an exclusive OR game.
Forces output signal 29006 of output 290 to logic 1.
Open the master clear sequence by
start Output signal 29006 is fed to inverting driver 468.
It will be done. The inverted output 46808 is the 200 ns second
is applied to delay line 467. 200 nanosecond tap
Output signal 46707 is the reset terminal of flop 243.
- given to the terminal. This allows ISL Logits
A 200 nanosecond pulse on the bus clears the bus.
No matter how long signal 10407 is on the bus.
This ensures that the reset function is performed regardless of the
The 100 ohm resistance for delay line 467 is this
Used to electrically terminate the signal. At the end of the 200 nanosecond pulse, signal 46707 flows
Clear tup 531. The negative of flop 531
The output signal 53108 is the clock of D-flop 511.
is given to the terminal to set this flop.
force to the default condition. Flop 511 setup
starts an internal clearing process. There are four master clear functions for ISL devices.
is generated by one of the signals. one signal
24306 is flop 2 caused by local control board
43 is the negated output. Second signal 93212
is the master clear signal from the remote control panel.
be. The third signal 91612 is the software on the telecommunications bus.
Software initialization command or power-up condition
caused by. The fourth signal is the local communication bus
The above software initialization command or power supply
This is a pull condition. OR game with three signals inverted
is applied to the input of port 734. Output signal 73406 is
It is given to the input of OR gate 831. The fourth belief
Master clear signal 53109 of issue is gate 831
is given to the other input side of . OR gate 831
Output signal 83111 is for flops and registers.
NAND game that gives output master clear
four inputs of port 830. signal
83006 is inverted by inverter 448 and its
Output 44806 is also a clear flop and register.
used for clearing. Some flops and
and registers require an affirmation signal, but other
Taps and registers require negation signals. Signal 83006 is the clock signal of flop 470.
Given. The output signal 47005 of this flop is
Initiate star clear sequence. first
master clear 200 nanosecond pulse 46707 is generated.
When completed, the 40 nanosecond pulse signal 46712 is a NAND
is applied to gate 512. NAND with signal 53109
is applied to the other input side of gate 512. Output path
The pulse signal 51208 is applied to an OR gate 469.
The output signal 46908 of the gate 469 is normally a logic 1.
Because output signal 46908 is a logical value, signal 51208 is
When it changes to zero, it changes to logic zero and resets the flop 470.
Set. The above sequence is
The 200 nanosecond pulse 46707 has its normal logical value 1
After returning to the initial state, the
We guarantee that. This is the output of JK flop 581 in Figure 14N.
Signal 58109 is also connected to NOR gate 469 in Figure 14L.
given to the input side. Retry request is processed
When the signal 58109 is forced to a logic zero, the flop
470. Therefore, flop 470 is the master clear
Restarts for 40 nanoseconds after signal 10407 is received on the bus.
is set. Flop 470 receives signal 83006.
It is set again by the trailing edge and master clears.
Start the sequence. MY MASTER CLEAR signal 53109 is inverted
The output signal 86804 is applied to the fourteenth
It is sent to the input side of driver 870 in Figure B. output
Signal 87014 is sent on the remote bus to the ISL logic
Indicates that the device is in master clear operation
do. Signal 91612 is connected to the remote bus by ISL logic.
and is applied to the input side of NOR gate 734.
and another device is in master clear mode.
Show that. Output signal 73406 is an OR gate
831 to the other input side of the 831 so that the previous
Generate master clear signal 83111 as described above.
Flop 47 alternately and at the same time as signal 83006 rises.
Set to 0. Therefore, the master clear sequence flow
Switch 470 provides security at both local and remote devices.
be tested. Master clear signal 47005 is the first
4V is applied to AND/OR gate 388 in the diagram.
Output signal 38808 is given to NOR gate 608
Ru. Output signal 60808 is CD input of D-flop 464
given to the side. Signal 60408 is AND gate 60
The clock input of flop 464, which is the output signal of
given to the power side. Signal 17612 is AND gate 60
4 input side. Signal 17612 is a negative OR
This is the output of gate 176. AND/OR gate 3
The signal 38808, which is the output of 88, is the negative OR gate 1
76 on the input side. Outside of the local cycle flop 464, the ISL support
cycle D-flop 441 clock signal 60408
It is set by ISL cycle flop 4
41 is set when an ISL cycle occurs and the local
Cycle flop 464 attracts ISL cycles.
When the triggering condition is due to a request from the local communication bus
Set. An ISL cycle is initiated from the telecommunications bus.
When started, remote cycle flop 572 is set.
will be played. ISL cycle flop 441 set
output signal 44109 is output from power driver 3.
22 input side. Output signal 32206 is 125
A nanosecond delay circuit 374 is provided. delay line 3
74 output signals in the ISL cycle.
Control the rope. In particular, signal 37411, a 50 nanosecond delayed signal,
Reset ISL cycle flop 441.
This synchronizes the output signal 44109 to a 50 nanosecond pulse.
let Local cycle flop 454 is set.
output signal 46405 is input to 4-bit register 4.
90 and input data to register 490
clock. The input to register 490 is
Storage request signal 48305, retry signal 58109, and retry
They are a response signal 58810 and a storage response signal 35106. The logic in Figure 14V also shows the priority
Determine whether local or remote control is required for the ISL cycle.
to decide whether to access it. Master
The clear sequence has the lowest priority.
Master Clear and Master Clear
A sequence has the highest priority. deer
However, relatively high priority functions are master cleared.
Controlled to enable operation. As an example, local retry request signal 58109 is
Generated as the output of JK flop 581 in the 14N diagram.
be done. Flop 581 is used for initialization sequence.
It is set for a while. Signal 83006 is
If the logical value is zero, set the flop D-
Provided to the S input of flop 632. this condition
The situation is that if the logic 1 bus data signal 21510 is
If not, force the output signal 63209 to a logic one.
At the same time, the output of NAND gate 559
The signal 55906 changes to logic zero. Signal 55906 is Flo
Flop 581 is applied to the S input of flop 581.
Set. Output signal 58109 is set to logic 1.
is input to the CJ input side of JK flop 584.
It will be done. Flop 584 is also connected to OR gate 605.
Set by input 53108 given. output
Signal 60506 is applied to the S input side of flop 584.
This sets the flop 584. centre
Loop 584 is set at this time and another request is
Block to prevent it from entering the screen. The signal 58109, which is the output of the flop 581, is as described above.
is applied to the input side of register 490 in FIG.
signal 46405 clocks the register.
I get pricked. The corresponding output of register 490
Signal 49010 defines the four basic ISL cycles.
AND gate, one of the four AND gates
5831. These ANDs explained below are called AND gates.
583, AND gates 590, 486 and
There are 493. In this case, the output signal 58306 is locally
Selected from retry request operations. In Figure 14Q, the master clear sea
During the period, the predetermined pattern is random.
All 1024 addresses of system access memory
be remembered. counters 744, 745 and 74
6 is the OR gate 83 in FIG. 14L, as described above.
The reset signal 83111 generated by 1
Cleared to zero for the first time. Next, the counter 744,
745 and 746 are reset to zero and then 1024
Incremented against the count. count signal
is on the input side of NOR gate 908 in Figure 14Q.
The signal of flop 470 of FIG. 14L given
Started by output of 47006. Output signal 90812
is applied to the input side of AND gate 740.
Local retry request signal 90002 is applied to AND gate 740.
given to another input side. Output count increment signal
No. 74003 is given to the input side of AND gate 747.
Ru. The output signal 74711 is the +1 counter of the counter 746.
given to Minal. AND gate in Figure 14V
The output signal 58306 of 583 is the inverter shown in Figure 14U.
signal 90002 is generated.
Ru. End pulse signal 37606 is AND gate 74
7 on the input side. Delay line in Figure 14V
The 125 ns output signal 37407 from 37415 is
is applied to the input side of the controller 377. output signal
The 37712 is an interface that generates the end pulse signal 37606.
is applied to the input side of inverter 376. This 125
The nanosecond signal controls the output of AND gate 74711.
By doing so, the counters 746 and 7 in FIG.
45,744 is operated step by step. Carry output signal
74612 is given to the +1 terminal of counter 745
The carry output signal 74512 is output from the counter 744.
+1 is given to the terminal. 1, 2, 4, 8 output signals of counter 746
74603, 74602, 74606, 74607 are register 741
applied to its respective input side. counter 745
1, 2, 4, 8 output signals 74503, 74502, 74506,
74507 is also on its respective input side of register 741.
Given. 1 and 2 output signals of counter 744
74403 and 74402 are given to the input side of register 929.
It will be done. Registers 741 and 929 are 3-state registers
It is. Registers 929 and 741 can be used as registers.
Count selection signal given to function terminal
74808 makes it available for use. signal 74808
is generated by the output of AND gate 748,
ISL system is in master clear mode
It is in operation state. for AND gate 748
Both inputs 53910 and 56108 are now at logic zero.
Ru. The output signals of registers 741 and 929 are
92915, 92912, 92916, 92909, 92905, 74105,
74106, 74119, 74102, 74109, 74115, 74112,
It is 74116. These signals are shown in Figure 14F.
Wired OR gate 13701, 13801, 13901,
14001, 14101, 14201, 14301, 14401, 14501,
14601, 14701, 14801, 14901 address bus
Given for bits 5 to 17 respectively. In Figure 14R, signals at addresses 8 to 17
14001, 14101, 14201, 14301, 14401, 14501,
14601, 14701, 14801, 14901 are multiplexer 3
Give to terminal "1" of 13,314,315
It will be done. Multiplexer 313, 314, 315
The output of channel address 0-9 signal is
given to the address terminal of RAM276
Ru. Therefore, the master clear sequence
During this time, terminal “1” is selected by signal 53910.
All 1024 addresses of RAM276 are
be accessed. Similarly, address signals 14001, 14101, 14201,
14301 is the input terminal of multiplexer 472
Given to "1". Signals for addresses 12-15
14401, 14501, 14601, 14701 are multiplexer 4
73 input terminal "1" and the address
The signals on switches 16 and 17 are sent to multiplexers 474 and 4
75 terminal "3" respectively.
Multiplexers 474 and 475 pass signal 48112 to
Selected terminal “1” from NAND gate 481
give to Signal 48112 is input signal 24414, 47006
and 53910 are all at logical zero, so at this time
It is at logical value 1. Multiplexer 472, 473, 474, 47
The signal 47212 of memory address 0 to 9 which is the output of 5,
47209, 47207, 47204, 47312, 47309, 47307,
47304, 47409, 47507 are memory conversion memory RAM7
06,708,709,710,711,71
2,714,715 address terminal,
A hit bit storage RAM 863 is provided. In Figure 14W, the signals at addresses 14 to 17 are
No. 14601, 14701, 14801, 14901 are multiplexers
749 terminal "0". CPU
Translator address 0-3 signal 74912,
74909, 74907, 74904 are RAM754 and 757
Address given to input terminal. signal
92806 selects logical zero from multiplexer 749
to the terminal and to AND gate 928
Local retry response cycle signal 59012 input is logical
Since it becomes zero, the input of multiplexer 749
"0" is selected. Master clear sequence signal 47006 is
NAND gate 750, 751, 752, 753
is given to each input. ISL system is master
signal 47006 is in clear cycle.
It is at logical zero. Output signal 75003, 75108, 75211,
75306 is at logic 1. These signals are RAM
754 data input terminal.
RAM 754 cycles through 16 address locations
At the time, the signal is inverted at the input side of RAM754, so
Therefore, a logical zero is written to each address location. The writable terminal of RAM754 is AND
Activated by signal 76003 at the output of gate 760
It is placed. AND gate 638 in FIG.
The output signal 63811 is the input of NAND gate 760.
given to the power side. for AND gate 638
One input is a 60 nanosecond delayed pulse 32502. 1st
In the 4K diagram, MYCLER signal 51105 and mass
Clear sequence signal 47005 is
is applied to the input side of port 471. NAND game
MYCLER signal 51105 input to 471 is
Power on master clear sequence
Clear operation of RAM 754 is enabled. deer
However, the clear operation of RAM754 is performed on the control panel.
is prohibited when the master clear button is pressed.
It will be done. Both of these signals have a logic value of 1 and are written to RAM.
display the embedding operations. Output signal 47113 is a NOR game.
is applied to the input side of port 639. Logical 1 output
Signal 63908 is connected to AND gate 638 in FIG.
given to the input side. Logic value 1 output signal 63811
is, if signal 13701 at address 5 is also logical 1
If so, input the NAND gate 760 in Figure 14W.
given to the power side. Output of NAND gate 760
At this time, the signal 76003 changes to a logical value of zero and is written to RAM.
Allows for embedding operations. In Figure 14R, the input channel mask
The write signal is the writable terminal of RAM276
given to Le. Signal 63811 is NAND gate 31
2 input side. Also, the signal at address 6
13801 is the other input terminal of NAND gate 312
given to Le. Signal 63811 is a logical value as described above.
It becomes 1. If address bit 6 is a logical 1
If so, RAM 276 performs the write operation. trout
The clear sequence signal 47006 is an AND game.
is applied to the input side of port 275. first master
– Signal 47006 is a logic value during the clear sequence
Since it is zero, the output signal 27505 has a logical value of zero.
Therefore, a logical zero is defined by address bit 6.
is written to the specified RAM 276 address. In Figure 14S, signal 68311 and address
7 signal 13901 is given to NAND gate 859.
Ru. The output of the enable signal 85906 is the RAM 706,
707, 708, 709, 710, 711, 71
2,713, 714, 715, and 863 books
given to embeddable input. Master clear sequence that is a logical zero
The signal is provided to AND gate 862. logical value
Output signal 86208, which is zero, is written to RAM 863.
given to the input terminal. Therefore, logical value zero
is written to all address locations. Data 6-15 signals 33901, 34001, 34101,
34201, 34301, 34401, 34501, 34601, 34701,
34801 is data input for RAM706 to 715
given to the terminal. The signal of data 6 to 15 is
Normally the logic value is 1, so the logic value 1 is RAM70
Written to all 1024 addresses from 6 to 715
Ru. In Figure 14M, the master clear service
During cycles, resistor networks 648, 649, 650
is data 01~15 signal 33401, 33501, 33601,
33701 and 33801 are held at logical value 1, and the 14th
Through receiver drivers 232 to 238 in Figure B.
No data is received on the communication bus. In Figure 14Q, signal 86108 is an OR gate.
759, 737, 730. Output signal
No. 75906, 73706, 73003 are inputs of register 929
given to the terminal. Output signal 92912,
92915 and 92916 are wired OR terminus in Figure 14F
Nulls 137, 138, and 139 are given. Output signal
Nos. 13701, 13801, 13901 have logical value 1 and write
Allows you to perform operations using RAM is mass as mentioned above.
initialized during a clear operation. In Figure 14V, the 100 nanosecond delay signal
37406 is applied to the input side of the inverter 327.
The inverter output signal 32712 is the inverter 326
is given to the input side of Output of inverter 326
The signal 32610 which is also on the input side of the inverter 762
given to. Signal 32712 is NAND gate 323
given to. Other inputs are end pulse signals
It is 37712. As mentioned above, various RAM addresses 1024 are cleared.
Master/Clear/List of Figure 14L until cleared.
Sequence flop 470 is set
maintain. In FIG. 14Q, counters 746, 74
When the count in 5,744 reaches 1024,
The output of the signal 74406 of the counter 744 has a logic value of 1.
Become. This signal is transmitted to inverter 316 in FIG. 14L.
is given to the input side of Output signal 31608 is Flotz
This is applied to the reset terminal of step 511.
Reset it. Signal 31608 is also shown in Figure 14N.
Provided to the input side of NAND gate 540. theory
The output signal 54008 of logical value 1 is the output signal of NAND gate 582.
given to the output side. End pulse signal 37712
and the local retry request signal 58306 becomes logical 1.
In the 1024th cycle, the two signals are
It is applied to the input side of NAND gate 582. child
The output signal of the gate of
changes to a logical zero value given to the target terminal. No.
To the input terminal of OR gate 469 in Figure 14L
The applied signal 58109 has a logical value of zero. signal
46908 is the reset terminal for flop 470
This flop is reset because
Ru. This will cause the master clear sequence to
be completed. Once the master clear sequence is complete,
Flop 584 in FIG. 14N is reset and
Remote requests entering the ISL system on the communication bus
is allowed. Signals 74406, 47005, 76208 are AND/
It is applied to the input side of OR gate 286. Output signal
No. 28608 is on one input side to OR gate 293
Given. Output signal 29308 is output from flop 584.
Given to reset terminal. signal 76208
is the output of inverter 762 in Figure 14V.
The signal applied to the input side of the inverter 762
It is the inversion of 32610. Description of the action of an ISL device in response to output control commands
Please refer to FIG. 14A. order
is the bus address signal 10503 to 10510, 10512
to 10519, 10521, 10523 to 10525, 10530 and
and 10532 from communication bus connector 105.
It will be done. The signals at addresses 0 to 23 are shown in Figure 14C.
provided to the driver/receivers 181 to 205.
Ru. In Figure 14J, addresses 8 to 16 are
Signal 18900, 19010, 19103, 19214, 19306,
19410, 19603, 19703, 19810 are compared respectively.
302 to 310. Compare
Data 302 to 310 are address comparators shown in FIG.
Consists of data. Also, comparators 302 to 31
0 is given to switches 101, 102,
Signals 10307, 10306, 10314, which are the outputs of 103,
10315, 10207, 10206, 10214, 10215, 10107,
It is 10114. This switch can be manually preset.
The address will be set to the specified address. Comparator 30
2 to 310 output signals 30208, 30303,
30411, 30506, 30611, 30703, 30806, 30911,
31008 is given to the input side of NAND gate 439
Ru. Output signal 43909 is the CD input terminal of flop 440.
- given to the terminal. Signal 24512 indicates that the transfer of information is
Indicates that the information is not forwarded. This signal AND gate
439 input side. Signal 10444 is the first
4A and received on connector 104 of FIG. 14B.
The driver/receiver 244 shown in FIG. Out
The force signal 24414 is applied to the input side of the inverter 245.
The output signal 24512 is the input of the AND gate 439.
given to the side. Bus data signal 21404 is
Picked up at Kuta 105, Wired OR Gate 21
given to 4. Signal 21815 is driver receive
output signal 21814 is applied to the 14th I
It is applied to the input side of inverter 215 in the figure. Out
Force signal 21510 is provided to driver 216. de
The output signal 21606 of the driver 216 is sent to the delay line 358.
is given to the input side of 60ns output on delay line
Signal 35811 is given by AND gate buffer 360
Then, the clock input of flop 440 in FIG.
Resulting in signal 36008 being applied to the power terminal.
This means that the bus signal has reached steady state and strobes.
guarantee that it can be done. ISL address signal
44006 changes to logical value 1 and signal 44005 changes to logical value zero
Change. Bus address 18-23 signal 20006,
20103, 20206, 20314, 20410, 20510 are the 14th K
In the address selection terminal of PROM399 shown in the figure
Given. Also, activity signal 10115 and operation signal
53910 is also PROM399 address selection terminal
given to Le. Activity signal 10115 is shown in Figure 14J.
This is the output of switch 101. in the system
Each ISL can be set to active or passive state.
Wear. Active state is where the ISL performs some other function
allow it. If true, data transfer mode
, and if false, specify as ISL configuration mode
The operation signal 53910 to be input is the data bit in FIG.
Controlled by the 1 signal 33310. About this
The details are explained below. In Figure 14L, bus addresses 18-
20 signals 20006, 20103, 20206, 20314, 20410
is applied to the input side of the NAND gate 131.
If addresses 18 to 22 are all logical zero
In this case, the output signal 13106 has a logical value of 1, and the AND game
is applied to the input side of port 405. address 23
Signal 20510 is applied to another input of AND gate 405.
available. Activity signal 10105 and ISL address signal
44006 is given to the other input side of AND gate 405.
It will be done. The output control signal is 40508. Function code 01 signal 40508 is the function initial setting signal
On the input side of the NAND gate 394 that generates 39408
Given. Data bit 0 signal 22203 is
applied to the other input side of NAND gate 394,
The output control is executing the sub-command initial setting command.
and is displayed. Function cutoff setting signal 39408 is
This input signal is applied to the S input terminal of
Set the lop and master clear as described above.
Start the sequence. The only difference is mass
The clear function is used in the power-on sequence.
Instead, it is initiated from the local communication bus. In Figure 14H, MYCLER
Clear) signal 53109 is the output of OR gate 438.
given to the input side. Output signal with logic value 1
43808 is given to the input side of register 631.
The 135 nanosecond delay signal 35809 is clocked into register 631.
Given to Tsuku Terminal. Therefore, the output signal
Force No. 63116 to logical 1. Signal 63116 is OR
It is applied to the input side of gate 130. Its output signal
The signal is applied to the S input side of the flop 433, and this
According to the driver/receiver 178 of FIG. 14C,
179 to generate a confirmation signal 43305.
This signal is sent to the communication bus to receive information from the source.
Confirm receipt of. Output control initial setting command is always
accepted and constantly verified. Stopping the subcommand puts the ISL in ISL configuration mode,
Subcommand restart places the ISL in information transfer mode. No.
In the 14L diagram, if data signal 22203 is
If the logical value is 1, the output signal 39404 becomes the logical value zero.
Therefore, the above sequence is never constructed.
Instead, the output of PROM399 in Figure 14K is
used. The output signals 39909 to 39912 of PROM399 are
is applied to the input terminal of register 400. vinegar
The probe signal 36204 is the cross of register 400.
given to the terminal. PROM399 is
This is the PROM 102 in FIG. The 90 nanosecond signal 35805 in Figure 14I is a NAND gate signal.
is applied to the input side of port 361. ISL ready signal
No. 44512 and write bus enable signal 64405
It is applied to the other input side of NAND gate 361. In Figure 14K, the ISL address signal
44006 is given to the input side of AND gate 445
Ru. Also given to the input side of AND gate 445
Displays data in response to read request
BSSHBC (Second Bus Half Cycle) signal 26012
be. The second half bus cycle signal 10412 is
Connector 104 in Figure 4A to dryer in Figure 14B
to the receiver/receiver 259. The output signal is
It is 25914. This command is a test mode command.
test mode signal 53914 is a logic value.
It is 1. In Figure 14N, the 60 nanosecond delay signal
36008 is on the clock input side of D-flop 644.
Given. File write enable signal 39607
644 to the CD input terminal.
Multiplexer 396 is configured such that the information in FIG.
Register to be written, address file 1
03 or data file 92 is not full
Select the display. In this case, multiplexer 3
The signal 58406, which is the input to the flop
584 is not set, the retry request is full.
Show that the register is empty. file
Selection signals 40903 and 41106 are sent to multiplexer 396.
Given to the selection terminal. At this time, both selections
The selection signal is at logic zero and is output to multiplexer 396.
The zero input terminal of is selected. In Figure 14-0, the second half bus cycle
Signal 25914 is connected to the input side of NAND gate 565,
AND gate 409 and NAND gate 478
available. Bus reset lock signal 24102 is
Inputs of AND gate 409 and NAND gate 476
given to the side. Bus memory verification signal 24414 is
applied to the input sides of NAND gates 476 and 565.
It will be done. Signal 20006 at bus address 18 is NAND
Provided to the input side of gate 478. Signal 47808,
56506 and 47603 are applied to the input side of NOR gate 411.
and generates a file write signal 41106.
File write 1 signal 40903 is AND gate 409
This is the output of This is the second half bus cycle or
Signal 25914 is moot since it is not a bus store cycle.
The logical value is zero. Both file write selection signals
40903 and 41106 are also logical zeros. In FIG. 14B, signal 10410 is
Connector 104 to driver/receiver 24 as shown
given to 0. The output signal 24006 in FIG. 14B is
The input of the inverter 241 that generates the output signal 24102
given to the power side. Memory verification signal 10444 is the 14th
Connector 104 to driver/receiver in Figure A
244 to produce output signal 24414. However, if the retry request in Figure 14N is full
When lock 584 is set, the ISL device is not in use.
It's inside. Therefore, the ISL device must not accept the command.
stomach. Thus, the write bus enable signal 64405 is
14H diagram D-flop 404 clock
given to Minal. given to CD terminal
Local retry request full signal 58406 has a logical value of zero.
Ru. Flop 404 remains reset.
Function confirmation signal 40409 has a logical value of zero and is an AND game.
Input terminal of gate 401 and NAND gate 421
given to Le. Prohibition standby signal 42103 is an AND game.
is applied to the input side of port 447. Comparison signal 31808
is applied to another input of AND gate 447.
Since this is not a compare cycle, signal 31808 is moot.
The logical value becomes 1. Local retry request set signal 58506
is applied to the input side of AND gate 447. Faith
No. 58506 is the output of AND gate 585 in Figure 14N
It's a signal. Input signals 40802 and 41008 are logical 1
be. Signal 40903 is inverter 4 in Figure 14-0.
10 inputs. Signal 41108 is inverter
is applied to the input side of the controller 410. The output signal is
It is 41008. The retry signal 56608 is the AND gate 5 in Figure 14N.
85 input terminals. Figure 14K
In this case, signals 40712, 33006 and 44512 are AND gates.
is applied to the input side of port 442. ISL available
Signal 44512 is a logic one. data parity
error signal 33006 is the data parity error signal 33006.
Since there is no error, the logical value is 1. retry signal
56608 is the output of NOR gate 566 in Figure 14N.
be. Signal 31704 is on the input side of NOR gate 566
ISL function OK signal to NOR gate 317
No. 44208 Since the input is a logical value of 1, it is a logical value of zero.
Become. The function OK signal 40712 in Figure 14K is PROM39
This is the decoded signal of No. 9. Four output signals 39909~
39912 is provided to NOR gate 406. The signal is
As long as one is a logical 1, the output signal 40606 is logical.
The logical value is zero. Signal 40606 is of inverter 407
given to the input side. The output of the inverter is a logical value
This is a signal 40712 at a level of 1. In Figure 14H, ISL standby signal 44706 is
It is applied to the input side of OR gate 629. Output signal
No. 62906 is applied to the input side of register 631.
Output signal 63102 is provided to inverter 630.
The output signal 63006 is the S terminal of the D-flop 453.
Given to Naru. Output signal 45309 has a logic value of 1.
level and the driver/receiver of Figure 14B.
is given to the driver side of H.263. output signal
26302 is given to wired OR gate 262,
This is applied to connector 104 and the signal
Sent on the bus as BSWAIT-00. In Figure 14H, signal 58406 is at flop 4.
Given to CD terminal and R terminal of 04
Ru. Write bus enable signal 84405 is clocked
signal 84405 is applied to the flop terminal 404.
Set at the leading edge of the Flop Flop 404 is
This means that the bus is in the set state as described above.
A confirmation signal is sent to the user. In Figure 14-0, the address in Figure 8 is
RAM consisting of file register 103
161 to 166 are bus address 0 to 23 signals
remember. Figure 8 Data File Registry
RAM 364, 177, 647, consisting of data 92,
365, 366, 389 record data 0 to 15 signals.
memory and control bus signals. Write selection signals 40903 and 41106 are used in each RAM.
Select one of the four locations and move to the selected location.
In this case, the input terminal of the RAM is
The number will be memorized. Write bus enable signal 64406 is
Given to the clock terminal of the RAM, the input
Clock data into each RAM. When information is being written to RAM, the 14th N
Flops 644 and 584 in the figure are set. child
state is signaled during the 60 nanosecond delay signal 36008.
Flop set at the rise of No. 64405
581 results. At the same time, the signal
Since 58109 is at logic 1, flop 584 is
Set by nanosecond delay signal 35602 of DCN135.
will be played. In Figure 14V, the cycle ze of Figure 8 is
Nerator 146 signal 92306, 27108, 83006,
58109 is applied to the input side of AND/OR gate 388.
It will be done. ISL devices provide transfers for remote bus operations.
Since this is not done, the signal 92306 has a logic value of 1.
Since no master clear sequence occurs,
Signal 63006 is a logic one. In addition, the bus/register
No star operation occurs and signal 58109 is at logic 1 level.
Therefore, the signal 27108 has a logic value of 1. Output signal 38808 is given to OR gate 608
Ru. Output signal 60808 is the CD input side of flop 464
given to. Output signal 60408 is output from flop 464
is applied to the clock input side of As mentioned above, believe
No. 37606, 17612, 57206, 46406 is AND gate 6
04 input side. If the ISL device is idle
state, signals 37606, 46406, 57206 are logic
It is at level 1. Input to OR gate 176
Since the force signal 38808 is a logical zero, the AND gate
The output signal 17612 given to 604 has a logic value of 1.
It's on the level. This causes flops 464 and 4
41 is set to open the ISL cycle as described above.
start In Figure 14-0, the master clear
Sequence signal 47005 and local cycle signal 46406
is applied to the input side of AND gate 369, and both
It is at the level of logical value zero. Signal 46406 becomes logic 1
When the data file transmission shown in Figure 8 changes,
The output signal 36903 in the ivy register 121 is
Changes to the level of logical value 1. Signal 36903 is the
Figure 8 Data File Transmitter Register
Registers 367 and 368 consisting of registers 121
Noh terminal. As a result, the register
are signals 36702, 36705, 36706, 36709, 36712,
36715, 36716, 36719, 36802, 36805, 36806,
Outputs 36809, 36812, 36815, 36816, 36819.
Furthermore, the registers receive signals 39102, 39105, 39106,
Outputs 39109. These signals are shown in Figure 14F.
Wired OR gates 332, 334 to 348
given to. In Figure 14-0, file read selection
Signals 40211 and 40312 appear on the output side of the RAM.
Select the location in RAM that contains the information to be stored.
Signals 49014 and 90704 are the outputs of NOR gate 402.
The logic of the local retry request cycle given to the power side.
The logical value becomes 1. Signals 49404, 49014, 48502 are NOR
It is applied to the input side of gate 403. ISL equipment
Specified by the signal given to NOR gate 403
Since the input is not in one of the cycles
Becomes a logical level of 1. Output signal 40312 is a logical value
It's at zero level. Two read selection signals at logic zero level
40211 and 40312 select RAM location zero. place
Zero is defined as the retry request (RRQ) register.
File write selection signal 40903 during communication bus transfer
When 41106 is at logic zero level, information is stored in RAM
was written at location zero. In Figure 14I, data signal 33401 is
is applied to converter 333. Output signal 33310 is
It is applied to the input side of register 539. Taimin
The input signals 32610 and 39702 are input to NAND gate 547.
given to the power side. In Figure 14K, the signal
41810 and 58306 are at the logical 1 level,
It is applied to the input side of AND/OR gate 363.
Output signal 36308 is the function code decoder in Figure 8.
Usable deco of decoder 397 with decoder 106
is given to the reader 106. Signal 36308 is a logical zero
Therefore, decoder 397 is enabled.
Ru. Signals 15301, 15401 for addresses 20 to 23,
15501 and 15601 are given to the input side of the decoder 397.
It will be done. In this case, signal 15401 at address 21 is
Addresses 20, 22, 23 are at the level of logical value 1.
Since the signal is at the level of logic value 1, the output control
Signal 39702 is selected. In Figure 14I,
When timing signal 32610 changes to logic zero, register
is given to the clock terminal of star 539.
Output signal 54713 is output if data signal 33401 is a logical value.
If the level is 1, the operation signal 53910 is set to a logical value of zero.
Convert it to Therefore, the ISL device is in the stop logic state.
It will be in . If the operation signal 53910 is a logical value
If the level is 1, the ISL device will go online.
is in a logical state. In Fig. 14F, signals 40006, 40003,
40004 and 40005 are wired OR function devices 153 to
156. Signals 40003 to 40006 are the first
This is the output of register 400 in the 4K diagram. register
400 is the usable terminal of register 400
Can be used with signals 41811 and 60306 given to
I am forced to play Noh. Signal 41811 is in register 418.
generated as output. Signal 44208 is as described above.
is applied to the input side of register 418. Signals 64508 and 57205 are inputs of AND gate 603
given to the side. Both input signals are at logic zero level.
It is located in the file and is explained below. Output signal 60305 is
to the second available terminal of the register 400.
This allows the output of PROM399 to be stored.
Ru. PROM399 logic value 1 level signal 40003
is encoded for the selected operation using
Signal 40003 is wired OR junction 1 in Figure 14F.
54, and the output signal 15401 is supplied to the decoder as described above.
coder 397. If signal 19914 is at logic 1 level, then
Signal 19914 at bus address 17 is in register 41
8 input side. At the same time, remote access
The address signal 41807 is the output of the register 418.
is selected and the remote ISL device is addressed.
Show that. If signal 19914 is a logical zero
If the local address signal 41806 is at
Display that the ISL device is addressed
selected as such. Bus address 17 signal
Regardless of the state of 19914, the output control command is
Processed by local and remote ISL device partners
It will be done. The control signal 41815 output of register 418 is the function controller.
is at a logic 1 level for code 01. signal
41814 is applied to AND gate 387. The signal is
When at the logic zero level, the NAND gate 54
The output signal 38706 given to the input side of 5 is a logical value.
Change to zero level. Signal 41802 is also a NAND gate
545 on the input side. further explained below
The signal is also at a logic zero level. output signal
54513 is the input of NAND gate 906 in Figure 14U
given to the side. Local retry request cycle signal
58306 is given to another input side of NAND gate 906.
It will be done. Both input signals 54513 and 58306 are logical 1 levels.
It's in Bell. Output signal 90611 is OR gate 763
is given to the input side of The output signal of the gate is
Logic given to CJ input side of JK flop 923
Changes to level 1. The CK input or signal 86011 is
Star clear cycle not completed
It is at logical zero. Cycle 100 signal 76208 is inverter 76
given to 1. Output signal 76108 is from flop 92
3 is applied to the clock input side. clock signal
is given 100 nanoseconds for the ISL cycle.
The set state of flop 923 is
Indicates that a transfer operation is about to occur to the ISL. transfer
The flop remains set until the
Ru. All transfer signals 92305 are the clock of D-flop 919.
The flop is set by being applied to the flop input side.
to tsut. Output signal 91909 is NAND driver 92
0 input side. Output signal 92008 is 125 na
is applied to the input side of the second delay line 917. 37.5 nanosecond signal 91703 is input to OR gate 918
given to the side. Output signal 91808 is flop 91
9 is applied to the reset input side of
After being set to 37.5 nanoseconds, the flop 919 is reset.
Set. Transfer cycle signal 91908 is NAND gate 897
is given to the input side of master clear sea
signal 86106 is the other input of NAND gate 897.
is given to the force side and has a logical value of zero for this operation.
Ru. Remote strobe signal 89701 is sent to the remote ISL.
data sent from the local ISL.
save. ISL interface driver 11 in Figure 8
5 and 14 indicating remote address receiver 104.
In the Z diagram, all transfer signals 92306 are multiplayer
Kusa 832, 835, 836, 838, 840,
842,846 clock terminal
It will be done. Signals 82610, 86404, 87311 are OR gate 9
11 input terminal and is at logical value 1.
Ru. Output signal 91108 is a multiplexer register
832 and 835 selection terminals, and the discussion
The logical value becomes 1. Therefore, given to input terminal 1
The input signal that is applied is selected. Signals 86404 and 87311 are the inputs of OR gate 912.
given to the power side. Output signal 91203 is multiplayer
is applied to the selection input of the processor register 836.
In this case, signals 86404 and 87311 are logical 1, so
input terminal of multiplexer register 836.
terminal 1 is selected. Signals 43009 and 58306 are the inputs of NAND gate 910.
given to the power side. Output signal 91003 is multiplayer
applied to the select terminal of the register 840.
It will be done. In this case both signals 43009 and 58306 are logic
Since the value is zero, multiplexer register 84
0 input terminal 1 is selected. Multiplexer registers 838, 840, 8
42 selects input terminal 1 under all conditions
It is wired to do so. Address 0-2
3 signals 13201, 13301, 13401, 13501, 13601,
13701, 13801, 13901, 14001, 14101, 14201,
14301, 14401, 14501, 14601, 14701, 14801,
14901, 15001, 15101, 15301, 15401, 15501 and
and 15601 are multiplexer registers 832, 8
35,836,838,840,842,846
is memorized. ISL interface driver 13 in Figure 8
No. 9 and No. 14 showing remote data receiver 116.
In the AA diagram, signal 92306 is multiplexed.
registers 849, 851, 853, 855
Applied to clock input. Signal 92806 is multi
Selection input side of plexer registers 851 and 853
given to. Multiplexer register 849
and 855 selection inputs are wired to selection input terminal 1.
I am being iaded. The selection signal 92806 is shown in Fig. 14W.
This is the output of AND gate 928. Signal 59102
92505 is given to the input side of AND gate 928.
Ru. Both input signals are logical zero for this operation.
The multiplexer/register shown in Figure 14AA
Input terminal 1 of terminals 851 and 853 is selected.
Ru. Data multiplexer 0-15 signal 78307,
78409, 78507, 78609, 78707, 78809, 79009,
79107, 72209, 79307, 79409, 79509, 79607,
79709 and 79807 are multiplexer registers
849, 851, 853 and 855 input terminals
given to Minal. In Figure 14T, signals 78111 and 78208 are
From internal data multiplexer 129 in FIG.
Selection 1 of multiplexers 783 to 798
and selection 2 is given to the terminal. signal 42410
and 80108 are OR gates that generate output selection signal 78111.
is given to port 781. Signals 82010 and 80108 are
OR gate 782 generating output selection signal 78208
given to the input side of. OR gates 781 and 782
Since the input to is a logical zero, the multiplex
The 0 inputs of the sensors 783 to 798 are selected. day
Data 2 to 15 signals 33501, 33601, 33701, 33801,
33901, 34001, 34101, 34201, 34301, 34401,
34501, 34601, 34701, 34801 are multiple
Provided to input terminal 0 of lexers 785 to 798.
available. Signals 93102 and 93009 are multi
applied to input terminal 0 of plexers 783 and 784.
available. Signals 93012 and 93009 are multiplexer 9
30 outputs. Data 0 and 1 signals
33201 and 33401 are the input terminals of multiplexer 930.
Given to minal 0. Signal 82706 is multiplayer
This operation is given to the selection terminal of Kusa 930.
The logical value is zero because of the operation. Usable signal 80108
Usable targets for multiplexers 783 to 788
is given to the terminal and is at logical zero, which causes
Enable multiplexers 783 to 788
Ru. Multiplexers 789 to 798 are always used
be placed in a state of possibility. At this point, address and data information
is received by the local ISL on the communication bus and registered
stored in the data. This address and data signal
is the ISL interface driver 1 in Figure 8.
15 and 139 remotely on the internal communication bus.
Sent to ISL. As an example, in Figure 14AA, the multiple
Signals 84912 to 84915, which are the outputs of lexer 849, are
Provided to the input side of driver 848. output signal
84803, 84805, 84807, 84809 are the end of Figure 14AC.
It is applied to the bank of terminal resistors 651. resistance bank
Signals 65111 to 65114, which are the outputs of 651, are ISL
Terminal of connector 660, which is the internal communication bus
given to. In Figure 14AA, multi
The outputs of plexers 851, 853, and 855 are dry.
ISL internal communication
connected to the resistor bank of Figure 14AC.
Connected to connector 660. Signal lines at connectors 660 and 663 carry information away.
Send to ISL every other day. Signal circuit of connectors 661 and 662
The line receives information from a remote ISL. In Figure 14U, signal 92305 is a register
813 clock terminal. Enter
The force signals 86404, 90002, 86712, 90910 are as described above.
four ISL cycles: storage request, retry request.
Represents request, memory response, and retry response. Here
The mentioned ISL cycle is a local retry request RRQCYL
It's a cycle. In this case, signal 90002 is a logical value
It is zero. Output signal 81307 is a logical zero and is far
Driver 814 in Figure 14AB to send to the ISL
is given to the input side of In Figure 14AB, AC ground signal 67708 is
given to the F terminal of the receiver/driver 733.
It will be done. If the ISL cable between local and remote ISL
is plugged into its respective ISL, this
The receiver/driver is always enabled.
Signal 67708 is the output of inverter 677 in Figure 14AC.
It is power. Capacitor 667 and resistor 668 are in
Connected to the input of converter 677. resistance 668
The other terminal is given +5 volts.
Connected to the other terminal of capacitor 667
It will be done. In remote ISLs, the AC ground signal 66201 is
local connected to pin 1 of the connector 662 and grounded.
Connect the cable to pin 1 of ISL connector 663.
It is connected through the wire. Once the cable is connected,
The ground at pin 1 of cable 663 is
appears on the input side of the controller 677, and the output AC ground signal
67708 to logic value 1, and therefore in Figure 14AB.
Enable receiver number 733 (for remote ISL)
), if the cable (of the two ISLs) is
When disconnected, the AC connection on pin 1 of connector 662
The ground signal, ie, the signal 66201, is set high by the resistor 668.
AC ground signal 67708 to logic zero.
let This signal, which has a logic value of zero, is connected to the remote terminal in FIG.
The output of the receiver 733 is prohibited. Therefore, if
When the cable is connected, the remote strobe signal number
No. 73307 is set at the trailing edge of the strobe signal.
Clock input of JK flop 874 in Figure 14V
given to the power side. In a remote ISL, the output signal 87409 is an AND gate.
is applied to the input side of port 799. signal 62088
It is applied to the other input side of AND gate 799.
Since the signal 62008 has a logical value of 1, the output signal 79911
becomes logical value 1. Signal 79911 is shown in Figure 14AB.
It is applied to the input side of AND gate 812. K
signal is connected and therefore available for generation 81208
is a logical value of 1, so the signal 67708 has a logical value of 1.
Become. Signal 81208 is the receiver/driver 815
Given to available terminals. Signal 66222 included
Force is generated at the local ISL. output signal
81509 is applied to the input side of inverter 816.
The output signal 81606 is the AND/NOR game shown in Figure 14V.
is applied to the input side of port 578. Signals 93214 and 92306 are AND/NOR gate 5
78 and is at logic 1. Remote ongoing output signal 57808 is AND gate 5
58 input side. Signal 87407 is an AND game.
is applied to the other input of the gate 558 and has a logic zero
becomes. Output signal 58803 at logic zero is AND
It is applied to the input side of gate 571. comparison signal
27909 is given to the other input side of AND gate 571.
This is not a comparison cycle, so it is a logical zero.
Become. Signal 57106 is on the input side of NOR gate 176
Given. The output signal 17612 with logic value 1 is an AND gate.
is applied to the input side of port 604. This results in the above
This results in an ISL cycle as follows. However, in this case the remote cycle flop 57
2 is set in place of local cycle flop 464.
to Also, since the flop 464 is not set,
Therefore, register 490 remains blank and the cycle
The signal signals 58306, 59012, 48603, 49303 have a logical value of zero.
maintain the condition. Instead, in Figure 14U
The remote cycle signal 90201 is generated. Signals 81509 and 57206 are NAND gates 902
is given to the input side of Output signal 90201 is remote
Specifies remote retry request cycle in ISL
The signal is RRQCYR. If you are not in information transfer mode, the
AND gate 573 logical 1 output signal
57304 is the input of AND gate 880 in Figure 14AB
given to the side. AC ground signal 67708 is on the other input side
given to. The output signal 88006 is the level shown in Figure 14V.
Given to the available terminal of Seaver 803
Ru. Signal 56108 is applied to the input side of inverter 876.
available. Output signal 87602 is the AND of Figure 14AB
Provided to the input side of gate 878. ground signal
66201 is given to the other input side. Output signal 87803
is the use of drivers 882 and 884 in Figure 14Z.
available on the input side. Figure 14AA Dora
Iba/Receiver 889, 890, 891, 89
2,818,817 and the Dry of Figure 14AB
driver/receiver 809 is driver/receiver 803
It is also made available for use. Also, the 14th Z
In the figure, drivers/receivers 881-88
6 receives ISL internal communication bus information
The REMOTE signal makes it ready for use.
Ru. address and data lines and some control lines
is transferred from the local ISL to the remote ISL and the ISL cycle
The file is initiated at the remote ISL. In Figure 14K, remote signal 56108 is
given to the input side of AND/NOR gate 363
Ru. Signal 93214 is other than AND/NOR gate 363
is given to the input side of As mentioned above, decoder 3
97, that is, the function code decoder 106 in FIG.
be placed in a usable condition. Address signals 15301, 15401, 15501, 15601 are other
Because it is received from the ISL on the internal communication bus,
Output control signal 39702 is selected as before. In Figure 14V, delay line 374 is
End cycle signal provided to inverter 377
Generate 37407. Output signal 37712 is a NAND game
323. Signal 32712 is also NAND game
is given to port 323. Output signal 32306 is OR
It is applied to the input side of gate 463. output signal
46306 is given to OR gate 291 and this game
By resetting flop 572,
A clip that completes the remote cycle operation of the output control configuration.
A. Generate remote signal 29111. the final end of the command
The edge occurs in the local ISL. CYC100 signal 76208
Remote cycle signal at AND gate 922
When generated in a remote ISL by 57205, the transfer
The transmission completion signal 92206 is sent to the local area via the above-mentioned receiver.
Received at ISL. In Figure 14U, at the local ISL, the
No. 73303 is given to the input side of NOR gate 739.
Ru. Output signal 73913 is a reset of flop 923.
is given to the terminal, which causes the flop
Reset. When information transfer between local and remote ISL is started,
Loop 923 is set for the first time. In Figure 14V, signal 92306 is again
given to AND/NOR gates 388 and 578
Cause another ISL cycle to occur to the local ISL and this
This allows the local ISL to accept different commands from the bus.
and make it possible. The output interrupt control instruction loads interrupt information into the ISL.
and the resulting interrupt is initiated, the central
Sesa is interrupted at the indicated level. In FIG. 14N, the flop 58 is
1 is set. Set flop 581
Signal 64405 also indicates address data received on the bus.
data and control information as described above.
clock to the address and data register files.
Tsuku. Signal 58109 is shown in Figure 14V as before.
Applied to the input side of register 490. In Figure 14K, AND/NOR gate 3
Signals 41810 and 58306 given to 63 are output signals.
No. 36308 is enabled, which enables decoder 3.
97 is enabled. As before, PROM39
9 is addressed and addressed location
The information in is stored in register 400. Re
The output of register 400 is the wired OR of Figure 14F.
the input terminal of the decoder 397.
Given to Naru. In this case, the output interrupt control signal
No. 39710 is selected, signal 39710 is AND gate 5
51 on the input side. Signal 57508 is an AND game.
is applied to the other input side of the gate 551 and has a logical value of zero.
be. The output signal 55106 is shown in Fig. 14M.
It is applied to the input side of NAND gate 825. Ta
The timing signal 32610 is other than the NAND gate 825.
given to the input side. The output signal 82504 is shown in Fig. 8.
Registers 819 and 857 clock terminals
interrupt channel register 132, and interrupt channel register 132.
level register 134. Signals 33901, 34001, 34101 of data 6 to 8 are
Provided to the input side of register 819, data 10 to 15
Signals 34301, 34401, 34501, 34601, 34701,
34801 is given to the input side of register 857, and this
This completes the cycle portion of this instruction. No.
The local flop 464 in Figure 14V is reset as described above.
be tested. If this command is applied to the local ISL in Figure 14N,
, the total RRQ flop 584 is
Reset as described above. If the remote ISL then shares the power with the local ISL
If you are processing an embedded control command, the level in Figure 14K is
BSAD1 of logic value 1 of input to register 418
7 signal 19914 sets remote address signal 41807 to logical value 1
local address signal 41806 is set to logic zero.
Become. The signal 38706 at the output of AND gate 367 is
The signal at the output of the NAND gate 545 has a logical value of zero.
Force 54513 to logical 1. This is an AND gate
Forcing the signal 57508, which is the output of 575, to logic value 1
do. This is the output of AND gate 551
Force signal 55106 to logic 1. In FIG. 14M, the signal 55106 with logic value 1
is the output of the NAND gate 825, the signal 82504.
Forced to a logical zero, the information is stored in register 819 and
857. In this case, the local ISL forwards the information to the remote ISL.
Ru. In FIG. 14U, a signal with a logic value of 1
54513 is the signal that is the output of NAND gate 906
Forces 90611 to logic zero, which forces signal 76308 to logic zero.
force to logical value 1. As a result, as mentioned above,
Remote ISL information can be accessed by setting
generate a local ISL for the transfer cycle. The reset timer instruction is
Enable several timers. output tie
Mar signal 39717 is sent to decoder 397 in Figure 14K.
is generated as a logical zero, and the AND gate 55
3 is given to the input side. This is a local operation
Therefore, the input to the other input side of AND gate 535 is
The remote function signal 57508 that is sent has a logical value of zero. logic
Output signal 55311 with value zero is input to inverter 554
given to the side. The output signal 55404 with logic value 1 is
Apply to the input side of NAND gate 280 in the 14X diagram.
It will be done. 50 nanosecond delay timing signal 32502
It is applied to the other input side of NAND gate 280.
Output signal 28008 is the mode control register in Figure 8.
The clock signal in register 914, which is part of
given to the terminal. Output of register 914
The signal is ready for use with a number of timer conditions.
do. One of these timer conditions is timeout.
, the output timer instruction resets the timer.
to prevent further timeout errors.
used for Output signal 91407 is a monitoring timer available gate
It's a signal. The supervisory timer indicates that the device is
Software that determines whether or not to respond to communications
A second timer used in conjunction with
Ru. Output signal 91402 resets the watchdog timer.
Ru. Output signal 91410 is a timer enable signal.
The time-out enable signal is
Test if there is a fault. output signal
91415 is an interruptible reset signal. interrupt
Possible signals test against illegal resources. This percentage
The write is performed during a memory write operation or at a memory time
It is sensed after the output. The above tie along with the master clear sequence
For one of the mar operations, the NOR gate 552
Either the signal 28008 or 47006 given to the input side
When the logic value is zero, the output clear signal 55208 is
The logical value is 1. This signal is used for all
Enable timer clear operation. In Figure 14Y, the timer and
and status device 133 data 3 signal 33601 and
Output clear signal 55203 is input to NAND gate 600
given to the power side. All data 9-15 signals are
Stays at logic 1 during star clear sequence.
Ru. The output clear signal 60006 is immediately output from the D-flop 599.
Retry timeout flop reset input
given to the force side, which resets this flop.
to tsut. The operation of flop 599 is as follows.
Explain. Similarly, output clear signal 55203 and data 0
Signal 33201 is applied to the input side of NAND gate 506.
It will be done. The output signal 50608 is from the D-flop 505.
is applied to the reset terminal, which causes the
Reset the lop. Setting the flop 505
indicates that no response was received from memory.
Show. This operation will be explained below. Output clear signal 55203 and data 1 signal are
It is applied to the input side of NAND gate 460. Out
The power signal 46011 resets the D-flop 459.
given to the terminal, which causes the flop to be reset.
Set. Showing the set of flop 459,
I/O device times out. In Figure 14X, the output clear signal 55203
And data 2 signal 33501 is AND gate 635
is given to the input side of Output signal 63503 is a counter
636 and 637 reset terminals.
given, which resets the counter.
These counters 636 and 637 are monitor timers.
It is part of the market control. Monitoring timer control operation
I mentioned this before. The output address instruction, which is different from the previously mentioned instructions, is
It has no effect on remote ISLs. all addresses
Will it now be controlled by the associated local ISL?
If the output address command is sent only to the local ISL,
It will be done. The output instruction sends one address to the local ISL.
Load. This address information is the channel address
address and/or storage address. Out
A power address instruction selects one of the address locations.
Ru. In Figure 14K, the output address command is
Output of signal 39706 of function code decoder 397
Select. RAM counter 118 and
FIG. 14Q shows the RAM control register 108.
For example, signal 39706 and 50 ns delay timer
The timing signal 32404 is the input side of the NAND gate 743
given to. Output signal 74310 is output from register 75
8 clock terminal and inverter 742
is given to the input side of Output signal 74212 is
G1 data of RAM counters 744, 745, 746
is given to the terminal, which causes the data in the counter to
data input. Register 758 has three RAM (CP transformer)
translator, memory translator, channel bits
Data 3 to 5 which is writable control for
Loaded with signals 33601, 33701, and 33801. The counter 744 receives the data 6 and 7 signals 22901 and
and 34001. counter 745
are data 8 to 11 signals 34101, 34201, 34301,
34401, counter 746
By signals 34501, 34601, 34701, 34801 of data 12 to 15.
is loaded. Where the output address command is read or modified
RAM counter 74 loaded at the address of
Completed at 4,745,746, register 258
stores writable bits for RAM selection.
Ru. The quality of output data is related to the output address command.
used. Use address location and output address
This uses the RAM specified in the
The data received from the communication bus during the
The data is stored in RAM at the specified address. In FIG. 14K, the output of decoder 397
Signal 39715 is forced to a logic zero. As mentioned above,
Signal 39715 and remote function signal, both of which are logic zero.
No. 57508 is given to the input side of AND gate 643.
Ru. The logic zero write RAM signal 64303 is a NOR gate.
is applied to the input side of port 639. Write enable signal 63908 is a logical zero. 1st
In the 4V diagram, signal 63908 and a 50 nanosecond delay timer are shown.
The timing signal is applied to the input side of AND gate 638.
available. This condition causes the write storage signal 63811 to
Force to logical zero. In Figure 14Q, signals 53910 and 56108
is applied to the input side of AND gate 748. Out
Force signal 74808 can use registers 741 and 929
function terminal, which causes the register
RAM counter 744, 745, 7 for output
46 to store the address. Figure 8 RAM system
The output signal from the control register 108 and the signal 74102,
74105, 74106, 74109, 74112, 74115, 74116,
74119, 92905, 92906, 92909, 92912, 92915,
92916 is the wired OR tar in Figure 14F.
terminals 137-149. In Figure 14Q, the output of register 758
is given to OR gates 730, 737, 759
Ru. Outputs 73003, 73706, 75906 are from register 74
1 and 929 are written.
Determine the RAM to use. Signal 73003 is memory conversion write
The output is viewable. Signal 73706 is channel write
Possible output, signal 75906 is CP conversion write signal
It is. Therefore, writing to any combination of RAM
It is possible to do this. Signals 73003, 73706, 75906 are also in register 929
is memorized. Signals 75906, 73706, and 73703 are each address
as signal 13701, 13801, 13901 in ISL.
Appears on the address bus. Signal 13701 is the first
Applied to the input side of the NAND gate 760 in the 4W diagram
It will be done. Signal 63811 is for NAND gate 760
The output signal 76003 is shown in Fig. 8.
RAM757 and 754 writable terminal,
CP source and destination RAMs 131 and 113
available. In Figure 14R, signals 13801 and 63811
is applied to the input side of NAND gate 312.
Output signal 31206 is the writable data of RAM 276.
terminal, that is, the channel hit bit in Figure 8.
It is given to RAM142. In Figure 14S, signals 13901 and 63811
is applied to the input side of NAND gate 859.
The output signal 85906 is the RAM 706 to 7 in FIG.
15 and 833 writable terminal memory changes
given to the conversion and hit bit RAM 125.
It will be done. In Figure 14Q, at the end of the instruction,
RAM counters 744, 745, 746 are
applied to the +1 clock terminal of the printer 746.
signal 74711. NOR gate 9
The signal 39715 input to 08 is a logic zero, therefore
Output signal 90812 is a logical zero. Signal 90002 also
Since the logical value becomes zero, the output signal 74003 has a logical value of zero.
become. The end pulse signal 37606 is a logical zero.
Therefore, when the signal 97606 becomes a logic value 1, the logic
Output signal 74711 at value zero indicates the end of the ISL cycle.
The counter 746 is incremented by the counter 746 as described above.
The printers 745 and 746 each send ripple digits.
Promoted by Nos. 74612 and 74512. In Figure 14N, input signals 76208,
RRQ complete flop 5 due to 56803, 47006, 57611
AND/NOR gate 286 where 84 is logic 1
will be reset to For remote control of output mask data commands, output
Only the power mask address is sent over the local bus.
As a result, if the output mask data command
If sent to a remote bus, the address is
to the remote bus in the same manner as described above via the remote bus.
data and other functions as described above.
Coming from Ta Huair. Address and data in remote ISL RAM
In order to write, the information from the local ISL is
is sent to the remote ISL, and the counter at the remote ISL is
It is not used to control RAM addresses;
Information for location specification always comes from the local ISL. Input interrupt control is disabled once an output command is received.
Similarly, it is searched from internal communication, but in Figure 14K.
According to the PROM399 output signal 39909 has a logic value of 1
become. Signal 39910 is on the input side of register 400
Given. The output signal 40005 is the wire in Figure 14F.
ad OR terminal 156. logical value
1 signal 15601 is sent to the decoder 397 in Fig. 14K.
given to the input side. Output signal 39709 is logical zero
It is. Also, signals 19914, 44028, 44508 are in register 41
8 input side. Output signal 41806,
41810 and 41814 have a logical value of 1. These signals are
It is applied to the input side of AND gate 387. logic
The output signal 38706 with value 1 is the input of NAND gate 545.
given to the power side. The output signal 54513 with logical value is
It is applied to the input side of NOR gate 613. output
Signal 61306 is forced to a logic one. In Figure 14N, flops 581 and 58
4 is set again and the local ISL cycle is as described above.
It starts like this. Address and data on the communication bus
Data information is stored in local ISL register file
be done. The intent of this instruction is to use the two registers in Figure 14M.
819 and 857. Regis
The register 819 contains the CP channel address and
Star 857 contains the level at which interrupts are controlled.
There is. Register 819, interrupt channel in FIG.
register 132, register 857, and
Information from interrupt level register 134 in Figure 8
is placed on the communication bus. Signal 81902, 81907, 81910, 81915, 85715,
85702, 85710, 85707, 85705, 85712 is the 14th
Internal data multiplexers 789 to 7 of T diagram
98 terminal 3 inputs, respectively.
The ground signal is connected to internal data multiplexer 783.
to 788 terminal 3 inputs. Faith
Nos. 39709 and 42708 are on the input side of NOR gate 801.
Given. Signal 89709 is a logical zero. logic
The output signal 80108 with value 1 is connected to OR gate 781 and
782 input side. Logic value 1 output signal
No. 78111 and 78208 are multiplexer 783 respectively.
to 798 1 and 2 selection terminals.
This allows three terminals to the multiplexer.
Select null input. Signals 78907, 79009, 79107, 79209 are the 14th W
The multiplexer 780 shown in FIG.
given to input terminal 0 of the multiplexer
Ru. Output signals 78004, 78007, 78009, 78012 are the first
Input terminal of multiplexer 526 in 4G diagram
1 and selected for this instruction. Out
Force signal 78609, 78307, 78507, 78409, 78809,
78707, 79307, 79509, 79609, 79807 are shown in Figure 8.
configuring the data multiplexer register 138.
The multiplexer register 5 of FIG.
25,527,528 to input terminal 1
It will be done. AND/NOR gate 524 with logic value 1
The output signal 52408 is sent to the multiplexer 525, 52
6,527 selection terminals, which
Select input terminal 1. signal 52408
42709 has a logical value of 1, and the AND gate 372
given to the input side. The output of this gate is
given to the selection terminal of multiplexer 528
Changes to logical value 1. In Fig. 14G, signals 15202, 61306,
58306 is given to the input side of NAND gate 465.
Ru. Signal 15202 at address 20 is the input to be implemented
Display instructions. The logic zero output signal 46508 is the NOR gate 378
is given to the input side of Output signal 37806 is a logical value
It is 1. In FIG. 14D, the logic 1 signal 76208
and 37806 are on the input side of AND/NOR gate 278
Given. The output signal 27808 is the circle in Figure 14G.
Closing of multiplexer registers 525 to 528
given to the terminal. Output signal 52514, 52515, 52513, 52515, 52613,
52612, 52614, 52615, 52712, 52714, 52713,
52715, 52814, 52815, 52813, 52812 are parite
Parity general that generates signals 52109 and 52209
data 521 and 522. In Figure 14D, signals 27808 and 56406 are
It is applied to the input side of OR gate 562. Output signal
No. 56211 is given to the input side of the inverter 563.
Ru. Output signal 56308 is output from ISL request flop 450.
Given to Klock Terminal. signal 45009
and bus in use signal 20804 is of NAND gate 533.
given to the input side. If this bus is in use
If so, set MY REQUEST flop 534.
The output signal 53303 given to the input terminal is
Set this flop. Signal 56211 is also the clock of ISLUOK flop 446.
given to the tsuku terminal, thereby
A logic 1 signal applied to NAND gate 520.
No. 44609 allows the use of bus parity networks.
shall be. If all inputs of NAND gate 520
If the conditions are met, the output signal 52009 will be MY
Setting the DATACYCLE NOW flop 517
given to the terminal and the ISL receives the information from the communication bus.
Indicates that information is being retrieved. Multiplexers 525 to 528 in FIG. 14G
output signal, and parity generator 52
1,522 is the driver/driver in FIG. 14B.
Inputs of the seaters 219, 220, 222 to 238
given to the side. MY DATA CHENNEL
The NOW signal is connected to the other input side of the driver/receiver.
given and gate this information onto the bus. In Figure 14N, as mentioned above, AND/
Input signal 76208 to NOR gate 286,
When 56803, 47006, 57611 are logical 1, all
Reset the RRQ flop 584 and reset the NAND game.
Signals 37712, 58306, 54008 input to port 582
When is logical 1, reset flop 581
This causes the ISL cycle to end. Remote interrupt control instructions are stored in the registers in Figure 14K.
BSAD17 input signal 19914 for 418 is logic
to the local interrupt control instruction, except that it has a value of 1.
Similar. The logic zero output signal 41806 is an AND game.
is applied to the input side of port 387. Output signal 38706
is a logic zero, output 45413 is a logic value 1, and the output signal is
Force No. 61306 to logical zero. In FIG. 14G, the NAND gate 446
Input signal 61306 to output signal 46508 to logical value
Force enable signal 37806 to logic zero by forcing it to 1
Force. Signals 37806 and 76208 are shown in Figure 14D.
given to the input side of AND/NOR gate 278.
Ru. Logic zero signal 37806 logic output signal 27808
By forcing the value 1, multiplexer 52
Clock input for 5,526,527,528
Disables power. The remote ISL generates ISL cycles and uses this data
back to the local ISL as specified by the command.
vinegar. As in the previous remote ISL cycle, the 14th K.
The decoder 397 in the figure is
Generates signal 39709 that generates an interval request cycle.
However, remote ISLs can centralize data by:
Return to ISL. In Figure 14U, signals 15301 and 90112 are
It is applied to the input side of NAND gate 905. theory
The output signal 90504 of logical value 1 is the input of AND gate 822.
given to the power side. Signal 93214 is AND gate 82
2 to the other input side. This is a remote ISL
Therefore, the logic 1 signal 93214 is caused by the local ISL.
is generated and sent to the remote ISL, where it is used as a remote function.
Indicates that the code is warm. Output signal 82208 is the input side of NAND gate 924
given to. End pulse signal 37606 is input
applied to the input side of converter 800. output signal
80002 is given to the other input side of AND gate 924.
It will be done. Output signal 92408 is locked at the end of the remote cycle.
This sets the flop 923.
Ru. This set flop is
Start transfer cycle from remote ISL to local ISL
do. Signal 82208 is applied to the input side of NOR gate 909.
It will be done. Signal 59012 is the other input of NOR gate 909.
given to the power side. Output signal 90910 is register 8
13 inputs. Signal 92305 is Regis
813 to the clock input side. In Figure 14U, signal 81314 is the local ISL
will be returned to. In Figure 14V, signal 81503
is generated and applied to NOR gate 269.
Output signal 2692 is input to AND/NOR gate 578
given to the side. Signal 27108 is an AND/NAND game.
is applied to the other input of port 578. others
Therefore, as mentioned above, the remote cycle is again performed on the local ISL.
start the file. The first cycle at the local ISL is the remote input service.
It was hot. The cycle starting from local ISL is
Sent to remote ISL and RRQCYR within remote ISL
Start. RRQCYR in remote ISL is local
Generates an RRSCYR (response) cycle in ISL.
Ru. The local ISL starts the RRSCYL cycle and the local
From remote ISL during RRSCYR cycle in ISL
Sends the received data onto the bus. In Figure 14N, in local ISL, remote
Signal 81503 and signal 57206 received from ISL are
Provided to the input side of NAND gate 597, the remote
The response output signal 59710 is the input side of the OR gate 592
given to. Signal 46108 is the output of OR gate 592.
It is applied to the other input side and has a logical value of zero. logical value
1 output signal 59211 is remote response cycle
Display (RRSCYR). As mentioned above, the data bus and
address bus from other semi-ISLs.
and data receivers. obey
In this case, the
Data is interrupt channel and level data
So, is this a remote ISL placed in the transmitter?
These are the ones sent to the receiver. This data bus at the local ISL
Have proper data in the cycle. This de
The data is the data multiplexer 129 of FIG.
The data multiplexer 7 of FIG. 14T consisting of
83 to 798. Local input interrupt
Unlike the control, at this point the function code
The coder output is invalid due to the response cycle. In Figure 14T, signals 29709 and 42708
is the input NOR gate 801 with logic value 1 at this time.
Ru. Therefore, selection signals 78111 and 78208 are logical values.
zero, which causes multiplexers 89 to 7
Select input terminal 0 of 98. This is
Data 6 to 15 signals 33901, 34001, 34101, 34201,
Select 34301, 34401, 34501, 34601, 34701, 34801
Interrupt chips sent from the remote ISL to the local ISL by selecting
Reflects channel and level data. At this point, all the previously mentioned cycles are
in the ISL cycle to enable the code decoder.
It was hot. At this time, RRSCYR cycle or retry
The response remote cycle does not start function code decoding.
stomach. In FIG. 14K, for decoder 397,
The signal 36308 Enable input is a logic one.
Therefore, the remote function code is returned to the local ISL.
Not generated for RRSCYR cycles. de
The data and address information is stored on the bus as described above.
Sent out. In Figure 14N, the RRQ flop 584
is reset and the RRQ TO DO flop 581
is the output command or initial input via gate 582
Reset in the original RRQCYL cycle as in the command
was tested. RRQCYL signal at end pulse
In the cycle, RR TO DO flop 581
Reset. RRQ FULL flop 584 is
It has the function of keeping this route in use,
Therefore, flop 584 is not set and RRQ
FULL signals 53405 and 58406 in their normal state
Flop 581 cannot be set again until it is returned.
Therefore, the reset of this flop at this time is
It has no effect on operation. In Figure 14K, register 418 is OR
Reset by signal 56011 output of gate 560
It will be done. Therefore, flop 584 in FIG. 14N is reset.
Register 418 is reset at the same time as it is set.
is set in register 418 at the beginning of this instruction.
Clear out all control functions that have been
Ru. The input mask data command is basically as shown in Figure 8.
Reading the hit bit information from RAM142
Ru. This instruction is the memory address of RAM125 in Figure 8.
response conversion and reading out the hit bits.
This also reads the CPU destination conversion RAM 131 in Figure 8.
It's being released. Input data commands must be placed in consecutive locations.
Always output address command except when read.
It is preceded by a decree or directive. One input data
The data instruction is followed by another input data instruction. death
However, somewhere in the RAM counter 118 in Figure 8,
Load the address of the starting location to be read
There must be an output address instruction. this is,
RAM sent to RAM counter control register 108
counter, whose output is as mentioned just before
RAM shown in RAM142, 125, 131
used to address. address
The information is used for RAM addressing,
These data from RAM are local to where the command is sent.
or sent to the data bus to a remote ISL.
Ru. Covers circular operation of local ISL input data commands
from the communication bus cycle that issues the command.
Therefore, in this case, the RRQCYL cycle is
An internal ISL cycle followed by another communication bus cycle
take le. Therefore 1 for local input data commands
There are only one internal ISL cycle. remote input data
The data instruction requires three internal ISL cycles. 1st
The cycle of is the address of the RAM location
This is the RRQCYL cycle that sends the ISL to the remote ISL. child
During the cycle, the RAM address is
is sent to the remote ISL according to the function code.
The second cycle is the RRQCYR cycle in
occurs. This data is further shown in Figure 8.
As mentioned, the same as RAM142, 125, 131.
Collected from remote ISL RAM. this data
The third cycle, the RRQCYR cycle,
Returned to the generated local ISL. This RRQCYL
Following the cycle, the data requested this
placed on the communication bus for transfer to the CPU.
Ru. Most of the logic of the instructions are input interrupt control instructions
This is covered in the explanation. The main difference is that
Select multiple inputs to create a data-to-data bus
Data from either local or remote ISLs as specified
Function code decoder to send to selected communication bus
It's in the output. In Figure 14N, flop 584 and
581 is set as described above. Logic value 1 belief
No. 58506 is given to the CJ input side of flop 581.
Then, clock 66405 sets flop 581.
to given to CJ input of flop 584
Signal 58109 clocks PRQ FULL flop 584.
It is set at the falling point of the lock signal 35602. this
Therefore, other directives may be affected by the ISL using the retry path.
Prevent acceptance. As mentioned above, the ISL should detect retry requests.
At the same time, an ISL cycle is generated. Also ISL Cycling
The timing signal is routed through delay line 374 in Figure 14V.
At this time, local commands and remote commands are
Sets the local LSL cycle in any way. Bureau
In the local cycle, if an instruction specifies an address to the local LSL,
Once established, generates timing and data paths.
and sends the data to the communication bus driver.
In Figure 14K, the function code output decoder
397 is an output signal 397 for input data command
14 is generated. Input data function code on communication bus
When the code is issued, this becomes function code 10.
Ru. This function code along with proper control bit configuration.
Code 10 is provided to PROM 399. this
The output of PROM399 is an encoded internal function code.
This is stored in register 400.
Ru. As mentioned above, the output of register 400 is
on the address bus during the developing RRQCYL cycle.
regarding the input to the decoder 397.
The function code is input data/data function 39714.
enable. When sent to a local ISL, this
The function reads data from the specified register.
shall be. During the input data, the data in Figure 14T
The multiplexer selects all appropriate signals via various registers.
Collect all data. Input data signal 39714 is
is applied to the input side of inverter 820. output signal
82010 is applied to the input side of OR gate 782.
Output signal 78208 or multiplexer selector 2
The signal is at logic 1. OR gate 781 signal
Both inputs to 42410 and 80108 are logical zeros.
This is not an interrupt control or interrupt cycle.
Therefore, the signal of multiplexer selector 1
78111 becomes logical zero. Therefore, multiplexers 783, 784, 78
5,786 input terminal 2 is selected. Enter
The force data is the CP destination change RAM function signal 75411,
75409, 75407, 75405. These are the 14th W
This is the output of the RAM 754 in the figure. In FIG. 14W, multiplexer 749
Output signals 74904, 74907, 74909, 74912 are CP line
Give it to the address selection terminal of the destination RAM754.
It will be done. Signals 59012 and 92505 are fed to AND gate 928
It will be done. This is not an RRSCYL cycle, so
The output signal 62806 with a logical value of zero is sent to the multiplexer 74.
9 selection terminals. Therefore, ad
Responses 14-17 signals 14601, 14701, 14801,
14901 is selected. In FIG. 14Q, the RAM counter 74
4,745,746 is the RAM control register in Figure 8.
Inputs of registers 741 and 929 consisting of star 108
given to the power side. This is ISL configuration mode
Since it is remote controlled, the input of AND gate 748
The signals 53910 and 56108 given to the side have a logical value of zero.
Ru. The output signal 74808 with a logical value of zero is the register 741
and 929 into a usable state. These cash registers
The selected output of the star is shown in FIG. 14W as described above.
RAM754 input address selection terminal and
will be reflected. Counters 744, 745, 746 in Figure 14Q
was previously loaded from the output address instruction. In Figure 14R, the channel hit bit is
The channel mask RAM 276 to be stored is
Multiplexer 31 for dress selection input terminal
3,314,315. signal 53
911 is a multiplexer 313, 314, 315
The selection given to the terminal. This is the configuration mode
signal 53911 is logic
Since the value is 1, input terminal 1 is selected. child
These are address bits 8-17 signals 31509,
31504, 31512, 31507, 31412, 34109, 31404,
31407, 31304, 31312. RAM276 channel hit bit 27607
The output is the input of multiplexer 787 in Figure 14T.
given to terminal 2. Memory hit bit
86307 is the input terminal of multiplexer 788
given to 2. This is RAM86 in Figure 14S.
This is the output of 3. Input address 0-9 selection signal
47507, 47409, 47312, 47309, 47304, 47204,
47209 and 47212 are multiplexer 47 in Figure 14R
2 to 475 outputs. Input selection 1
and two signals 48112 and 53911 have a logical value of 1. child
This is the ISL in data transfer mode even in memory verification.
Therefore, the input signal of gate 481
24414 and 53910 are logical zeros. NAND game
The output of gate 481 is a logic one. Therefore, the signals 14001 at addresses 8 to 17,
14101, 14201, 14301, 14401, 14501, 14601,
14701, 14801, 14901 are selected. For this reason,
The output signal 86307 of RAM 863 in Fig. 14S, immediately
Then, the memory hit bit is selected. Output signals of storage conversion RAM 706 to 715
70607, 70707, 70807, 70907, 71007, 71107,
71207, 71307, 71407, 71507 are inside of Figure 14T
Data multiplexers 789 to 798
The two terminals are respectively given to the two input sides. RAM7
06 to 715 are signal address designations in Fig. 14S.
The fixed memory mask hit bit RAM863
Dress specified. For local input data commands, see Figure 14T.
Data from multiplexers 783 to 798
Multiplexer register 525 in Figure 14G
This record is sent to the terminal 1 input side of
The register is the bus interface terminal shown in Figure 8.
Multiplexer register 138. As mentioned earlier, selection signal 52408 is a multiplayer
Input terminals of Kusa registers 525 to 527
select signal 37208, select signal 37208
Input terminal 1 of multiplexer register 528
Select the signal. The rest of the operations on local input data instructions are
from the communication bus at the end of the RRQCYL cycle.
As already mentioned, this is due to the transfer of information. The remote input data instructions are related to input interrupt control.
The operation is the same as described above. That is,
During the RRQCYL cycle, remote to remote ISL
A transfer cycle is generated that generates a strobe.
Ru. The remote ISL uses this signal to start the remote cycle.
generate. This remote cycle is as mentioned before
RRQCYL cycle, the main difference is RAM
Data that gets their addresses from counter control
data multiplexer, channel address, and
The remote ISL, rather than the storage and conversion RAM, is shown in Figure 8.
Block 104, the remote address receiver?
The point is to obtain that address. Therefore, the first
The channel hit bit RAM in Figure 14R and the 14th
Memory conversion RAM in figure S and CP conversion in figure 14W
Address input to RAM is still the same as described above.
This is obtained from the address bits, and these RAM
The output is a local data multiplexer.
is sent to the communication bus data terminal in Figure 14G.
Instead of going to the multiplexer register, the data map
The output of the multiplexer is the local data in Figure 14AA.
Go to the driver. multiplexer register
849, 851, 853, 855 are data mal
Receives the multiplexer output and stores it in this register.
The entire transfer time mentioned previously is stored. 14th
The output of gate 924 of signal 92408 in diagram U is
If this data goes to the local ISL, the remote cycle
This is the signal generated by the 100 nanosecond delay signal of the child
data must be returned to the local ISL and
These four multiplexers are connected to local ISL pairs.
Receives data returned to . Here, as mentioned above,
local ISL is the signal that causes the RRSCYR cycle.
Receive. This RRSCYR cycle is performed as described above.
data from the remote ISL and transfer it to the communication bus.
sends to register and generates further communication bus cycles
and sends this data to the CP that originally requested it.
Return it. The input status command of the ISL device will be explained. child
The ISL input status commands for cycle logic and
As far as timing and timing are concerned, other inputs to the ISL
It is the same as the force command. If the command is for local ISL
only RRQCYL cycles occur if
do. If this command is for a remote ISL,
then three cycles, i.e. RRQCYL local
ISL cycle, this cycle continues RRQCYL far
Every other ISL cycle is performed. The only difference is
It is as follows. In Figure 14K, signal 39711 is sent to decoder 3.
97 output. Signal 39711 is in
applied to the input side of inverter 424. logical value 1
The output signal 42410 is the OR gate 781 in Figure 14T.
is given to the input side of Logical value 1 selection 1 input
Signal 78111 is output from multiplexers 783 to 798.
Select input terminal 1. Selection signal 782
08 is a logical value of zero. Therefore, the input terminal
1 signal is the communication bus and requesting central processor.
selected for transfer to. This for multiplexers 783 to 798
The input data signals (ISL status bits) such as
Verified. Data bit 0 (input signal 87203,
The multiplexer 783) is an operating bit, and this
Bit 0 indicates whether the ISL is in data transfer mode or configuration mode.
Displays whether it is in the code. Data bit 1 (in
power signal 89309, multiplexer 784) is
Displays whether there is an interrupt requested from a remote ISL pair.
Show. This may also lead to monitoring time out or illegal
Display resource error partner. All individual status bit inputs are explained here.
The instruction's data flow is complete rather than
As soon as this is completed, the individual situation will be changed to the 14th T.
I will show what is related to the diagram. As mentioned above, multiplexer 78 of FIG. 14T
Data outputs from 3 to 798 are local ISL input status commands.
Bus multiplexing in Figure 14AA for the command
to the registers 848, 851, 853, 855.
Given. A communication bus cycle is generated and the status
status information is sent to the requesting central processor. Remote input status commands are remote input data and input
This is the same as an interrupt control instruction. This information is
sent out on the bus from the ISL to the local ISL,
From there, it is sent over the communication bus to the requesting central processor.
Served. The explanation below is based on the situation bits shown in Figure 8.
Performed in ISL timer and status device 133
It's about various functions. Data map in Figure 14T
The first status bit for multiplexer 0 is
This is the operation bit signal 87203. In Figure 14I
The signals 62806 and 53910 are input to AND gate 872.
given to the power side. The logic 1 signal 62806 is
other ISLs in the area or local area are linked to the system.
Indicates that power is being supplied. Signal 66243 is routed through connector 662 in Figure 14AC.
connected to the ISL interface bus,
4AC diagram driver 736 input side and +5 volts
given to the bull up register 665 up to
Ru. Therefore, if either ISL is shut down or powered off,
- down, signal 66243 becomes logic 1.
Ru. Output signal 73612 is output from inverter 62 in Fig. 14J.
8 input side. Output signal 62806 is AND
It is applied to the input side of gate 872. signal 53910
is the logical value 1, and the output signal 87203 with the logical value 1 is
Input terminal of multiplexer 783 in Figure 14T
Given to Naru 1. The driver 913 in Fig. 14AB is applied to the input side.
It has a ground signal that can be Output signal 91318 is
Kuta 663 terminal and then other ISL
for the ISLs concatenated by this
Provides a ground signal. In FIG. 14T, the remote interrupt storage signal
89309 is the input terminal of multiplexer 784
given to. data multiplexer bits
A signal of 1 78409 is generated as an output. In FIG. 14X, the distant memory signal 87112,
Monitoring time signal 91616, timeout signal 91402, far
Interrupt enable signal 91415 is AND/NOR gate 8
95 input side. Logical zero output signal
89508 has remote interrupt or timeout,
Setting the flop D-Flop 893
Displays what is given to the client terminal. In Figure 14Y, the end pulse signal
37712 and the logical 1 status signal 42410 are NAND game
is applied to the input side of port 609. The output signal is OR
It is applied to the input side of gate 295. Master
Clear signal 83006 is given to the other input side. theory
The output signal 29506 of the logical value zero is the flop of Figure 14X.
This is given to the 893 reset terminal.
Reset the flop after the status is read by
Ru. In FIG. 14T, multiplexer 785
Input terminal 1 of the
and for data multiplexer bit 2.
The status signal or signal 78507 therefore has a logic zero value.
Data multiplexer 3 signal 78609 is
The activation signal 10115 provided to multiplexer 786
Generated from This signal 10115 is shown in Figure 14J.
This is the output state of hexadecimal rotary switch 101.
The local ISL device is active when the logic value is 1 and active when the logic value is zero.
Indicates that it is in passive state. Data multiplexer 787 output
Plexer Bit 4 Signal 78707 and Data Mal
The multiplexer bit 5 signal 78809 is
Each terminal 1 input of lexers 787 and 788 is
Since it has a logical value of zero, it becomes a logical value of zero. Data multiplexing with monitoring timeout function
Signal 78907 of Kusa bit 6 is multiplexer 7
This is the output of 89. Signal 91502 is a multiplexer
789 terminal 1. Figure 14X
In this case, connectors 104 to 50 in FIG. 14A
Cycle AC or 60 cycle AC signal 10435 is the first
Apply to the input side of the RC filter resistor 112 in the 4X diagram.
It will be done. The other terminal of the resistance signal 11202 is 0.1
Wired to capacitor 113 of icrowad
and Schmitt trigger inverter 261
is given to the input side of Other than capacitor 113
The terminal is grounded. Schmitt Trigger
-The signal 26102 which is the output of the inverter 261 is
It is applied to the input side of AND gate 634. surveillance
Timer enable signal 91407 and monitoring timeout
The output signal 63712 is connected to the other input side of the AND gate 634.
Given. Monitoring timer enable signal 91407
Set during the output timer command described above. surveillance
Timeout signal 63712 indicates if the previous cycle
If the timeout occurs, the timeout
prevent the cycle. Output signal 63406 is
Unta 636's G2 usable terminal and Kurotsu
given to the terminal. Output signal 63602 is
Connector 637 G2 usable and clock
given to the terminal. Output signal 63712 is before
As mentioned above, the input side of the AND gate 634 and the inverter
is applied to the input side of data 915. Output signal 91502
is on the terminal 1 input side of multiplexer 789.
Given. The monitoring timer has a counter 736 and
A logic 1 within approximately 1 second of the start of 737 operation.
signal 63503, then the timer
A time out signal 91502 is generated. counter 7
The resetting of 36 and 737 has already been explained.
Beta. In Figure 14T, the data multiplex
Signal 79009 of Savit 7 is sent to multiplexer 790
is the output of multiplexer 789 and is the terminal of multiplexer 789.
The input of line 1 is grounded, that is, has a logical value of zero. Data multiplexer bit 8 signal 79107
is the output of multiplexer 791. retry data
Im out signal 59005 is multiplexer 791
is given to the terminal 1 input side of. retry tie
time out signal 59905, if on the remote ISL bus
During I/O commands to the controller, the ACK signal is
No. 16001 or NAK signal 24901 marks the start of this directive.
If the finger is not received within 120 milliseconds, this
Indicates a device error to the central processor that initiates the command.
If indicated, it is forced to a logical value of 1. signal
The generation of 59905 has already been described. Data multiplexer bit 9 signal
79209 is the output of multiplexer 792.
I/O timeout signal 45909 is multiplexed.
is applied to the input side of terminal 1 of sensor 792.
I/O timeout signal 45909 is on the remote bus.
An I/O command is issued to the controller of
and that we have received this command, and that we have received this command.
that a second half bus cycle should occur;
The second half bus cycle occurs within 250 milliseconds.
When it is confirmed that there is no one, the logical value becomes 1. Immediately
As mentioned above, the timer can be set via the output time command.
It is true that enabling
It was stolen. Data multiplexer bit 10 signal
79307 is the output of multiplexer 793. Record
Memory timeout signal 50509 is multiplexer 7
93 terminal 1 input. memory data
The time out signal 50509 is
The second half of the bus will be scheduled on the assumption that the cruiser has been confirmed.
If the cycle occurs within about 6 microseconds,
The logical value becomes 1. Flop 505 in Figure 14Y
The effect was mentioned earlier. Data multiplexer bits in Figure 14T
11 signals 79409 and data multiplex
Signal 79509 of bit 12, multiplexer 7
Each output of 94 and 795 is sent to multiplexer 7
Terminal 1 input for 94 and 795 is
Since it is grounded, it has a logical value of zero. data mal
Multiplexer 13 signal 79607 is multiplexer 7
96 output. Illegal resource signal 86905 is multi
applied to the input side of terminal 1 of plexer 796.
It will be done. If the addressed memory location is
If not present in the system during a load operation, this signal
86905 has a logical value of 1. In Figure 14I, the bus NAK signal 24814
is applied to the input side of register 413. Output signal
No. 41307 is given to the input side of NAND gate 544.
It will be done. Memory write signal 52306 and memory request signal 51505
is also applied to the input side of NAND gate 544.
The logic zero output signal 54408 is output from the D-frame in Figure 14T.
is applied to the set input side of loop 869.
A storage location addressed by a more remote ISL
Set a flop to indicate that there is no
Ru. Data multiplexer bit 14 signal
79709 is the output of multiplexer 797.
ISL parity error signal 44409 is multiplexed.
is applied to the terminal 1 input side of the sensor 797. child
The signal indicates that a command issued to the ISL has resulted in unreasonable parity.
When it is included, the logical value is 1. In Figure 14B,
Bus data 0-15 signals are parity generators
232 and 239. odd number pa
The output signals 23206 and 23906 are NOR gate 22
1 input side. Output signal 22108 is OR
It is applied to the other input side of gate 331.
BSREDD signal 25403 data out on the bus
The source detects improper parity before sending the
and is displayed. Signal 33108 indicates that if unjust parity
is detected, the clock timing signal
D-Flop of Figure 14Y set on 36204
444's CD input side. Data multiplexer bit 15 signal
39807 is the output of multiplexer 798 in Figure 14T.
power and terminus to multiplexer 298.
Since the null 1 input is at ground level, the logic value is zero.
Ru. The input ID command command initially indicates that the local ISL is
It makes no difference whether it is issued to any of the two ISLs.
It is separate from other input commands. The cycle is
It's the same. That is, only one cycle is included;
This results in a local RRQCYL cycle. Against ISL
The ID returned by the local and remote ISLs are connected together.
When powered up, it becomes hex 2402.
If the remote ISL is not electrically connected,
The returned ID will be 2400 hexadecimal. In Figure 14K, the output of PROM399
is applied to the input side of AND419. output signal
41906 is applied to the input side of register 418.
The output signal 41802 is on the input side of the NAND gate 545.
Given. This signal 41802 with logic value 1 is an output signal.
No. 54513 prohibits remote cycles from occurring.
Decoder 397 also generates output signal 39716.
Signal 39716 is sent to multiplexer 435 in Figure 14J.
is given to the selection input side of 436, which is a hexadecimal number
Select 24 ID function codes. Signals 42304 and 62806 are inputs of AND gate 417
given to the side. Signal 42304 is ID encoding/decoding
It is a function and has a logical value of 1. About signal 62806
The remote ISL is connected and powered up.
It was explained that the logical value becomes 1 when Output of logical value 1
ID bit 14 of input signal 41711 corresponds to the last hexadecimal number.
gives the hexadecimal number 2. Therefore, this ID code
is hex 2400 for local ISLs to operate,
Hex 2402 for local and remote ISLs
becomes. In FIG. 14G, the signal 42304 with logic value 1
is applied to the input side of AND/NOR 524. theory
The logical zero output signal 52408 is sent to the multiplexer.
Selection terminal of registers 525, 526, 527
is given to the multiplexer register.
Terminal 0 input of stars 525, 526, 527
Select. Selection 52408 is the data mark in Figure 8.
AND gate 372 which is a multiplexer register
is given to the input side of Logical zero output signal
37208 is the selection of multiplexer register 528
given to the terminal, which causes the terminal output
Choose power. Input to multiplexer register 525
Signals 43504, 43410, and 43507 have a logical value of zero and are not input.
The force signal 43509 has a logic value of 1. multiplex
The input signal 43512 of the register 527 has a logical value of zero.
Therefore, the input signal 43604 has a logic value of 1. Maru
Input signal 43609 of multiplexer register 526,
43612 and 43607 have a logical value of zero. Terminal 0 included
Since the power is grounded, the output signal 52615 is a logic zero.
becomes. Signals 52908 and 86606 are input to O gate 513.
given to the power side. Both signals are non-ID function transfer
, these signals have a logical value of zero.
applied to the input side of multiplexer register 527.
The output signal 51303 is a logic zero. A logic zero signal that is the output of OR gate 514
51406 is the input of multiplexer register 527
given to the side. Input to OR gate 514
Since the signal 53006 has a logical value of zero, it cannot be stored or transferred.
and interrupts. Output signal 52814 and
For multiplexer register 528 of 52815
Since the input terminal connected to the
has a logical value of zero. As mentioned above, signal 41711 is
Table for local and remote ISL operations
Show. Output signal 52812 is multiplexer register
Input terminal for 528 is RRQ cycle
Since it is at the ground level, it has a logical value of zero. nine
Lock bus signal 27808 is generated as described above,
This loads the ID into registers 735-738.
This generates a communication bus cycle by
Send ID to central processor requesting data
do. This is shown in Figure 8, which allows 16
The information in the forward rotary switch 140 is directly
sent to data multiplexer register 138
It will be done. This essentially completes the ISL construction mode. In Figure 14K, output signals 40003 to
40006 is wired OR153-15 in Figure 14F
6 and the signals 15301 at addresses 20-23,
Connect 15401, 15501, 15601. Figure 14K
Register 400 receives logic zero signals 41811 and 60306.
be made more usable. About signal 41811
I have already mentioned that. Signals 64508 and 57205 are given to AND gate 603
It will be done. Cycles that should be transferred even if they are remote cycles
Therefore, signals 64508 and 57205 have a logical value of zero.
Ru. Output signal 60306 can be used by register 400
This is given to the input side, which has a logical value of zero. In information transfer mode, the ISL uses the ISL configuration mode.
using all configuration data loaded in the
Ru. The first usage cycle consists of four cycles.
This is the storage request path. MRQCYL cycle is
Initial cycle following storage cycle detection by ISL
and then at that point if this is the memory write
If it were a command, the cycle flow would be interrupted.
MRQCYR occurs in the interval ISL. This is a remote
Data is written to memory on the bus
It is MRQCYL followed by MRQCYR. But what if
If this is a memory read, this ISL is a memory request.
Maintains busy state for routes and provides memory response support.
Wait for Ikuru. Next, the source from which the original directive was issued.
followed by MRSCYR which will be returned to the local side of
A memory response site remote from the original MRQCYL
There is a local area of Kuru. This memory request is the first
request and then wait for a response from memory.
This is from remote ISL to MRSCYL and then MRSCYR
Back to the local area again. This is the basic flow,
2 cycles for writes, 4 cycles for reads
Has a cycle. During the BSDCNN cycle,
ISL is the memory provided to the communication bus from local equipment.
Respond to requests as an agent. this is,
It is carried out during DCN time, and in Figure 14-0,
Selection for writing to register file location
The logic is done via NAND gate 476.
Ru. Gate 476 passes as its input BSMREF.
signal 24414, which is the signal generated by the communication bus, and another communication bus.
The functional BSLOCK signal is a signal generated by the communication bus.
Has 24102. This BSLOCK signal is sent to memory.
Indicates that this is not a test and set instruction for
and the BSMREF signal indicates that this is a store instruction.
Display. Regarding non-test and set lock
The details are explained below. BSMREF signal 24414, both of which have a logic value of 1.
BSLOCK signal 24102 is the input of NAND gate 476.
given to the power side. Output signal 47603 is NOR gate
411 on the input side. Output selection 2 signal
41106 is a logical value of 1. Signal 41106 is inverter
410 on the input side. Output signal 41008 is
The logical value is zero. The signal 25914 with a logic value of zero is an AND game.
is applied to the input side of port 509. Logical zero output
The force selection 1 signal is applied to the input side of the inverter 408.
The output signal 40802 has a logical value of 1. Therefore,
For storage requests, the RAM location in Figure 14-0 is used.
Location 2 is selected. Previously, location 0 is in ISL configuration mode.
selected for code input. In Figure 14N, signal 48706 is multiplexed.
Applied to the input side of lexer 396. selection signal
40903 and 41106 are the selection terminals of multiplexer 396.
is given to the terminal and selects the terminal 2 input.
Ru. Output signal 39607 is the CD terminal of flop 644.
clock signal 36008.
When the DCN cycle occurs for 60 nanoseconds, the flop
644 is set and the output signal 64405 is the JK flop
483 clock input side. logical value 1
The signals 54808, 40802, 41106 are AND gate 489
is given to the input side of Signal 54808 is shown in Figure 14I.
This is the output of the AND gate 548. Figure 14S
The signal 86307 is the output of the memory RAM 863.
and signal 62606 indicates that this is the transfer mode and the text is
Since this is not a strike operation, the logical value is 1. Output signal 48912 is CJ terminal of flop 483
given to Le. Output signal 48305 is D-flop
487's CD input side. against the cycle
At 135 nanoseconds, the clock terminal
The flop signal 35712 given to the flop
87 and the signal 48705 is in the D file.
prohibits further traffic in this location.
Ru. Output signal 48706 is the set input of flop 487
The other DCN signal 35712 is
This flop if given to a terminal
maintain the set state. In FIG. 14S, the storage conversion RAM 706
Signals 70607 to 71507, which are the outputs of
It is applied to the input sides of stars 716 and 717. signal
48305 is the clock register for registers 716 and 717.
signal 48305 becomes logic 1.
When RAM signals are stored in these registers,
Ru. In FIG. 14H, the signal 86307 with logic value 1,
24414 and 41106 are applied to the input side of AND gate 477.
available. Output signal 47706 and signal 46209 are AND gate.
is applied to the input side of port 484. signal 64406
Attaches to the clock terminal of JK flop 462.
available. Output signal 46209 is a logic one. Out
Force signal 48408 is reliable for cycles in 135 nanoseconds.
of register 631 clocked by No. 35809.
given to the input side. Output signal 63115 is a NOR game.
is applied to the input side of port 130. Logical zero output
Signal 13005 is the setter of D-flop 433.
given to the terminal side, which sets the flop.
to Because of this flop setting operation,
by sending a confirmation signal onto the communication bus.
Complete the DCN cycle. At the beginning of a storage read storage request operation, the storage size is
Time out begins for Kru. 14th
In the Y diagram, signal 48305 is connected to D-flop 61.
7 clock terminals. this is
Since it is a memory write operation, signal 26610 is a logical value.
It becomes zero and the flop 617 is not set. Read
In the operation, flop 617 is set and
Signal 61706 is a 6 microsecond one shot failure.
Given to the constant input side. Signal 48603 with logic value 1 is
given to the positive input side of one shot 611.
Ru. A storage request cycle begins as follows. No.
In the 14V diagram, signal 48306 is connected to NOR gate 64.
5 on the input side. Logic value 1 output signal
64508 is applied to the input side of AND/NOR gate 388.
available. Since signal 92306 has a logic value of 1, there is no logic.
The output signal 38808 of the logical value zero is local cycle as mentioned above.
Le Flop 464 and ISL Cycle Flop 4
Set 11. Signal 46405 is register 490
clock signal 48305. storage request storage signal
49002 becomes logic 1 and signal 49003 becomes logic 0.
Become. Signal 49002 is on the input side of AND gate 486
given, if this is not a memory response cycle
For example, signal 49014 has a logic value of 1;
For logic zero, signal 48603 and for logical zero, signal 48502.
A storage request cycle is initiated. ISL configuration mode
Memory requests such as in every cycle shown in
The cycle activates delay line 374 and this
The cycle continues as described above. In Figure 14N, various states on the logic side are shown.
load to end the storage request cycle for the state.
Jitsuku follows. Reset memory request FULL flop 487
Therefore, the logic zero signal 48502 and the timing signal
32610 is given to the input side of NAND gate 482.
Ru. Output signal 48201 with logic value 1 is AND/NOR gate.
is applied to the input side of port 488. Logical 1 flag
Isle write signal 36609 is AND/NOR gate 4
88 to the other input side. Logical zero output
Signal 48808 is applied to the input side of OR gate 283.
It will be done. The logic value zero output signal 28306 is sent to the flop 48.
Reset 7. Others for OR gate 283
Master clear signal 83006 whose input is logic 1
It is. ISL is performing memory write operations.
If so, flop 487 is reset. Frotz
If the ISL is in the middle of a memory read operation,
Not reset. Signal 48201 is applied to the input side of NOR gate 282.
It will be done. Output signal 28204 is the reset signal of flop 483.
is given to the tuto terminal, which causes the flotsu
483. This allows memory requests
It is OFF at cycle time 100, but it is memorized.
MRQ FULL flop only if it is a write operation
Terminates when becomes OFF. If this reads
operation, the MRQ FULL flop is still
and is set. Information for MRQ cycles
Transfer FULL JK flop to send to remote ISL
is set. As mentioned above, in Figure 14U
In this case, the storage request cycle signal 86404 with a logical value of zero is
It is applied to the input side of NOR gate 763. output
Signal 76308 is applied to the CJ terminal of flop 923.
This is set at the falling edge of clock signal 76108.
and load all data and address lines.
address and data driver.
Drive data to remote ISL. The data path is
It is as follows. In Figure 14-0, at DCN time
The signal written to location 2 of the register file is
Selected by read selections 40312 and 40211. Both the memory response cycle signal 49014 and the logical value 1
Retry response signal 90704 is input to NOR gate 402
given to the side. Read selection 1 signal 40211 is
is given to the read terminal of the file. logical zero
The storage request cycle signal 48502 of NOR gate 40
3 is given to the input side. Logic value 1 read selection
2 signal 40312 stores and stores address data.
of the file that controls the signals related to the request cycle.
given to read terminal 2 of file location 2.
available. In Fig. 14T, input selection signal 78111 and
78208 is a logical zero, which allows multiplayer
Select the terminal 0 input of Kusa 783 to 798
do. Also, the selection signal 82706 is sent to the multiplexer 93
0 selection input side. Selection signal 83706 is
Since the logic value is zero, the terminal of multiplexer 930
– terminal 0 input is selected. In Figure 14-0, DFIL0~15 output signals
No. file 364, 177, 647, 365, 3
66 and 389 are the input sides of registers 367 and 368
given to. DFIX in registers 367 and 368
The 0-15 output signals are sent on the data bus. Signal 16803 can use files 161 and 162
output of OR gate 168.
is generated. RRQCYL signal 58305 is NAND
It is applied to the input side of gate 169. this is
Since it is not an RRQ cycle, signal 58305 is a logic value.
0, and therefore the input to the input side of the OR gate 168.
The resulting output signal 16908 has a logic value of 1. information
Transfer mode idle signal 54906 indicates that this is an idle cycle.
The other OR gate 168 with logical value 1 because it is not a
given to the input side. Logic value 1 output signal 16803
The output signals of files 161 and 162 are selected.
prevent that from happening. MRQ cycle signal 48502 is connected to OR gate 167.
given to the input side. This is an MRQ cycle.
Therefore, this signal 48502 has a logical value of zero and the output
Signal 16708 is a logic zero. Signal 16708 is Huai
Available tables for files 163, 164, 165, 166
is given to the terminal, which causes the output AFIL08
~23 signal is enabled. output signal
AFIL0 to 7 are not ready for use. In FIG. 14S, register 716 is
Memory that is the output of the memory conversion RAM 705 to 713
Stores conversion address 0-7 signals. Also, Regis
The conversion address 8 and 9 signals of the data controller 717 are the RAM 71
These are the outputs of 4 and 715. Therefore, the memory requirement size
During the cycle, the address conversion memory signal ADXLM0~
9 is the multiplexer 832, 83 in FIG. 14Z
5,836 on the input side of the terminal 0 input.
It will be done. Multiplexer registers 832, 83
5,836,838,840,842,846
Everything is the falling edge of TRANSFER FULL signal 92306
clocked by OR gate 911 input
When the storage request cycle signal 86404 is a logical zero,
Yes, this allows multiplexers 832 and 835
In order to select the terminal 0 input of
91108 has a logical value of zero. Similarly, OR gate 9
Since the input signal 86404 for 12 has a logical value of zero,
Therefore, signal 91203 is connected to the terminal of multiplexer 836.
Select null 0 input. Signals 72001 to 72901
is by multiplexers 832, 835, 836.
selected and address signals for transfer to the bus
Drivers 833, 834, 8 as LCAD0 to 9
37 input side. Transfer to bus
Therefore, the output signals 83612 and 83613 are as shown in Figure 14AB.
given to the input sides of drivers 847 and 844, respectively.
It will be done. Multiplexer registers 838, 842, 8
The selection input for 46 is a logical 1, which
Select Terminal 1 input. multiplex
The selection input of signal 91003 of signal register 840 is also
This is a logical 1 because it is not an RRQ cycle.
Therefore, at the input to NAND gate 910,
A certain signal 58306 has a logical value of zero. Address signal 14201, 14301, 14401, 14501,
14601, 14701, 14801, 14901, 15001, 15101,
15301, 15401, 15501, 15601 are multiplexers
Registers 838, 840, 842, 846
is given to the terminal 1 input. Also, fail lot
write signal 36407 and file write signal 36609 are
Multiplexer register 846 terminal
1 given to the input side. Output address LCAD10
~23 signals on the ISL interface bus
Driver 837, 83 to transfer to remote ISL
9,841,843 on the input side. signal
84613 and 84615 are ISL interface
applied to the input side of driver 844 for transfer onto the
available. In Figure 14U, register 813 is
Set at the rising point of TRANSFER FULL signal 92305.
will be played. Logical zero storage request cycle signal
86404 is given to the input terminal of register 813.
It will be done. The output signal 81302 with a logical value of zero is the 14th AB.
It is applied to the input side of driver 814 in the figure. output
Signal 81409 is the input of resistor network 655 in Figure 14AC.
given to the power side. Output signal 65515 to remote ISL
Connector 663 for signal transfer
It will be done. Signal 66220 is connected to connector 662 in Figure 14 AC
Signal 66220 enters the remote ISL for the 14th AB.
applied to the input side of the driver/receiver 815 in the figure.
It will be done. The output signal 81507 is the OR gate in Figure 14V.
is applied to the input side of H.269. Logic value 1 output signal
No. 26912 is on the input side of AND/NOR gate 578
Given. At this time, BUS FULL signal 27108 is
Assuming a logical 1, the output signal 57808 is
The logical value is zero. Signal 57808 is applied to the input side of AND gate 558.
It will be done. Output signal 55803 is input to AND gate 571.
given to the power side. Output signal 57106 is a NOR gate
176 on the input side. Output signal 17612 is
It is applied to the input side of AND gate 604. output
Signal 60408 sets flop 4
41 clock terminals. or,
Remote cycle flop 572 is set. In Figure 14V, signals 81507 and 57206 are
Applied to the input side of NAND gate 865.
MRQ cycle remote signal 86513 is a logic one. In Figure 14V, the logic value 1 signal 57205
is applied to OR gate 561. remote signal
56108 is a logic 1, and this remote signal is the 14th
Drivers 881 to 886 in Z diagram, 14th AB diagram
Drivers 803, 809, and Figure 14AA
drivers 889 to 892. local area
Information from the ISL is transmitted remotely via these drivers.
Received by ISL. Address and data information is transmitted via remote ISL.
Received from Department ISL. Address information is local
First 10 bits from storage translator in ISL
Contains tuto. The remaining address bits are
Received by local ISL from central processor and sent remotely
Sent to ISL. Data information, i.e. signals 33401 to
34801 is received by the remote ISL from the local ISL and
14T diagram of multiplexers 783 to 798
- is sent to the terminal 0 input. OR gate 781
and 782 output signals 78711 and 78206 are
It has a logical value of zero for this cycle. data 1
and data 2 are the terminals of multiplexer 930.
Selected via the null 0 input. Output signals of multiplexers 783 to 798
DTMX0~15 are data transferred from local ISL.
reflect the data. In Figure 14C, the local ISL
For address signals received from
Signals 14001, 14101, 14201, 14301 of steps 8 to 11 are
applied to the terminal 0 input side of multiplexer 157.
signal at addresses 12, 13, 18, 19
14401, 14501, 15001, 15101 are multiplexer 1
58 terminal 0 input side. address
Signals 15301, 15401, 15501 and
15601 is terminal 0 input of multiplexer 160
given to power. Signals for addresses 14-17
14601, 14701, 14801 and 14901 are in Figure 14M
applied to the terminal 1 input side of multiplexer 731.
available. Output signal 73107, 73109, 73112, 73104
is on the terminal 0 input side of multiplexer 159.
Given. In Figure 14E, this is an interrupt
Since this is not a read cycle, signal 42709 has a logical value of zero.
The outputs of multiplexers 157-160 reverse the inputs.
make it possible to project. Address input
signal 0 is not the second half bus cycle
The multiplexer selection signal 37806 is selected for
The logical value becomes zero. Multiplexer 157-160
The output of is connected to the input side of registers 508 and 509.
be done. Register 507 input addresses 0-7 are directly
This is received from the address bus of the
Reset signal 42708 is high because it is not a read cycle.
becomes. Multiplexers 783 to 798 in FIG. 14T
data multiplexer signal DTMX0~15
are the multiplexers 525 and 52 in FIG. 15G.
7,528 terminal input side and the terminal input side of Fig. 14W.
terminal 0 multiplexer 780.
In Figure 14G, MRQCYR signal 86513 and
The file write remote signal 39310 is an AND/NOR gate.
is applied to the input side of port 524. Output of logical value 1
The force signal 52408 is sent to multiplexers 525, 526,
527 terminal 1 input. signal
37208 is terminal 1 input of multiplexer 528
Choose power. Logical 1 file write signal
80701 is applied to the input side of inverter 399.
Output signal 39310 is a logic zero. Figure 14W
Output signals 78004, 78007, of multiplexer 780,
78009 and 78012 are the multiplexer rails in Figure 14G.
given to the terminal 1 input side of register 526.
Ru. If the remote side performs a read operation and the file is
If the read signal 80701 has a logical value of zero, then the signal
39310 becomes logical 1. Output signal 52408 is a logical value
zero, which causes the multiplexer register
Terminal 0 of 525, 526, 527, 528
Select input. Select signal 37208 is a logical zero.
Ru. Therefore, in Figure 14J, the hexadecimal rotary
Output generated from signals 101, 102, 103
The signal is multiplexer register 5 in Figure 14G.
It is reflected on the terminal 0 input side of 25 to 528.
Ru. The signal 51303 of bit 10 is the signal of OR gate 513.
Generated by the output side. MRSBIT86606 is
It is applied to the input side of OR gate 513. 14th
In the AA diagram, the FILWRT signal with a logical value of zero
80701 is applied to the input side of the inverter 806. Out
The force signal 80612 is applied to the input side of the AND gate 868.
It will be done. MRQCYR signal 86573 with logic value 1 is AND
Provided to the other input of gate 866. Output signal
No. 86606 has a logical value of 1 for read operations,
Logical zero for write operations, which is a
At the input of signal 51303 to multiplexer 527
reflected. Therefore, for read operations,
MY DATA bit 9 signal 52615 becomes logic zero
Become. MY DATA bit 10 signal 52713 is invalid.
The logical value becomes 1, and the signal of MY DATA bit 11
52715 is a logic zero, MY DATA bit 12 signal.
No. 52814 is logical zero, MY DATA bit 13
Signal 52815 is logic zero, MY DATA bit 15
The signal 52812 has a logical value of zero. In Figure 14D, clock signal 76208 and
Signal MRQCYR with logic value 1 is AND/NOR gate
278 on the input side. 100 na of logical value zero
The second delay time output signal 27808 is the inverter 279.
is given to the input side of Logic value 1 output signal
27908 are registers 507, 508,
509 clock terminal and Figure 14G.
applied to multiplexer registers 525-528.
available. Clock signal 27908 is also a D-flop
Set 271. In Figure 14V,
is the input to AND/NOR gate 578
BUS FULL signal 27108 is another remote ISL cycle
prevent it from starting. If everything in this system is normal and the remote bus
This can occur if a memory request cycle is identified above.
and the various things that may occur if it is not confirmed.
Pattern, if NAK response, this NAK response is different.
legal device, parity error or illegal memory
I mentioned earlier what can happen. this
NAK may be caused by many ties on the memory itself or on the communication bus.
can be generated by any of the following: communication
Bus timeout in bus logic
It has a function. If this cycle is given to an illegal device,
If it is, no response will occur. 5 microseconds
, the central processor on this bus instead of the illegal device
responds to NAK. This allows for other communications
release the bus. The CP on this bus is
Generates an internal trap to the software
Execute the subroutine. If CP on remote bus
If not, the ISL will use this NAK instead of the illegal device.
occurs. There are two ways to generate NAK.
Ru. The first way is that the ISL is in its own DCN.
Generate a DCN on a bus that is not
The goal is to find the DCN. D-F of Figure 14Y
Lop 268 is set. DCND60 signal
36008 is given to the input side of one shot 612.
It will be done. If this one shot 612 is a communication bus
Reset 7 microseconds ago by DCNB signal 21306
If not, signal 61204 is generated and the
268 to set it. if
Signal 36008 is applied to the CD input side of flop 268.
If so, this is still a logical 1.
In Figure 14H, the bus timeout signal
26806 is applied to the input side of OR gate 274.
The output signal 27411 with a logic value of zero is output from the D-flop 449.
Set. In Figure 14B, the output signal
44909 is applied to the input side of driver/receiver 247.
Generates BSNAKR signal 24901 by
do. In Figure 14Y, a NAK response is generated.
The second method is as follows. 60ns delay
DCN signal 36008 and MY DATA CYCLE NOW signal
No. 51707 with 3 microsecond one shot of 100
I gave it to the power side. Output signal 10012 is D-flop 5
35 clock input side. CD termi
The signal 36008 given to the null is a clock signal.
If the logic value is 1 at the end of 3 microseconds of 10012, then
Flop 535 is set. In Figure 14H
MY TIME OUT signal at logic zero
53508 is given to the other input side of OR gate 274.
Then, the NAK signal is generated as described above. 14th
In Figure I, as mentioned above, the data received from the remote ISL is
The NAK signal 24814 is on the input side of register 413.
given to. Output signal 41307 is NAND gate 5
44 input side. MY MEMORY
RETRY REQUEST REMOTE signal 51505
is applied to NAND gate 544, which causes the difference
Generates law memory signal 54408. Logical zero signal
54408 indicates remote ISL has expired
do. In Figure 14T, signal 54408 is an illegal station.
section flop 869 is set. Output signal 86905
is a status signal indicating an illegal resource error. No.
In the 14X diagram, signal 54408 is a NOR gate.
is applied to the input side of port 824. output signal
82406 is the interrupt D-flop 823 clock input.
given to the power side. Disable interrupt signal 82106 is
It is given to the CD terminal of Tsupu 823. signal
82106 is generated in Figure 14M as below:
Ru. Data 10 signal 34301 is input to register 857.
Logical value given to power side for interrupt disable operation
It becomes 1. Output signal 85715 is of inverter 856
given to the input side. The output signal 85606 is a NAND gate.
is applied to the input side of port 821. Level 1-5
Signals 85702, 85705, 85707, 85710, 85712 are
Provided to the input side of NAND gate 858. Out
The power signal 85806 is applied to the input side of the NAND gate 821.
available. Disabled interrupt signal 82106 is registered in register 85
Controlled by data 5 to 10 signals given to 7
be done. If signal 82106 is logic 1 and interrupt
If it is shown that is not prohibited, then in Figure 14X
Then the flop 823 is set. output signal
82309 is applied to NAND gate 607. output
Signal 60708 is interrupt cycle D-Flop 427
is given to the S input side of the
Interrupts in the ISL that interrupt the communication bus issued.
generates a cycle. Local ISL is also remote ISL
has the ability to interrupt. In Figure 14B
In this case, illegal storage signal 54408 is input to driver 870.
given to the power side. Output signal 87018 is the receiver
916 to the remote ISL where signal 66137 is received.
is sent out on the internal bus. Output signal 91616
is applied to the input side of inverter 871. 1st
In the 4X diagram, the output signal 87112 is AND/NOR
It is applied to the input side of gate 895. Interruptible
Signal 91415 is the other input of AND/NOR gate 895.
given to the power side. If the output timer instruction is logical
If sent with data bit 6 of value 1, the signal
91415 has a logical value of 1. Logical zero output signal
89508 sets flop 893. signal 86508
Again, OR gate 824 is used to generate a logic value 1 signal.
Generate 82406 and write flop 823 as described above.
Set it. In the description up to this point, the write command is remote.
Explained the operations sent to memory. this
Remote memory does not exist or does not function, therefore ISL3
A microsecond internal timer expires. on remote ISL
The illegal memory function has been set and the illegal memory display has been set.
Send to every other ISL. Interrupt implementation on remote ISL
Interrupt implementation flop on flop 823 and local ISL
823 has been set. Data 10-15 signal is
Set by central processor to allow interrupts
do. A normal second half read response is confirmed on the remote ISL bus.
is the result of a successful read request that has been granted. first
generated by memory in response to a remote read request.
The DCN cycle sent to the ISL containing the ISL address
sent to. This address is the second half memory response
placed on the intercommunication bus during the cycle. In FIG. 14J, exclusive OR gate 302
Bus address 8-16 signals for 310 to 310
The input is compared with the ISL address 8-16 signals and
If these are logically equal, then exclusive OR30
2 to 310 have a logic value of 1, and AND gate 4
39 input side. This is a memory read operation.
Therefore, the signal 24512 has a logical value of 1 and the output
The power signal 43909 is applied to the CD input side of the flop 440.
It will be done. Timing signal 36008 is clock
ISL address flop 44
Set to 0. In Figure 14-0, the second half bus with logic value 1
Signal 25914 and address 18 signal 20006 are
Applied to the input side of NAND gate 478. theory
The logical value 1 signal 47808 is this second half bus cycle.
indicates that the module responds to storage requests. logical value
The zero output signal 47808 is the input side of the NOR gate 411
is given to the file write selection 2 signal.
Enabling No. 41106. Lock signal 24102 is a logical value
Since it is 1, file write selection 1 signal 40903
has a logical value of 1. Therefore, the data and address
Address location 3 of the file is selected. In FIG. 14N, the signal 40903 with logic value 1,
41106 and 44006 are the input side of AND gate 500
given to. Output signal 50008 is AND gate 49
6 on the input side. This is a double bull operation
Since there is no
The applied signal 21104 is a logic one. Output signal
No. 49611 is the CJ input of the memory response JK flop 492.
given to the side. This write enable signal 64405 is
A clock that sets the flop 492 at the trailing edge.
given to the terminal. In the 14V diagram, the output signal 49206 is a NOR gate.
is applied to the input side of port 351. output signal
35106 is given to register 490. output signal
49206 is also given to the input side of NOR gate 645.
Ru. Output signal 64508 is AND/NOR gate 388
is given to the input side of logical value 1
TRANSFER FULL signal 92306 is an AND/NOR game.
is applied to the other input of port 388. As mentioned above
This is the local cycle flop 464 and ISL
Set cycle flop 441. Output signal
No. 49015 is given to the input side of AND gate 493.
Ru. Since there is no double cycle operation signal 35206,
The other input to AND gate 493 is a logical 1
becomes. The output signal 49303 has a logic value of 1. Memory
Is the purpose of the response cycle storage via remote ISL?
request data on the local communication bus
It is to return it to its source. Therefore, in Figure 14U
TRANSFER FULL923 is set.
to load the ISL interface registers.
Ru. Signal 4309 is applied to the input side of inverter 867.
It will be done. Output signal 86712 is the input of NOR gate 763.
given to the power side. Output signal 76308 is flop 9
Applied to the CJ input side of 23, the falling edge of signal 76108
Flop 923 is set at point. As mentioned above,
ISL interface registers are loaded and
Data is transferred to the local ISL at both ends of the intercommunication bus.
It will be done. Address and local ISL from which address information originates
This address information is replaced by
It should be noted that time is not important. In Figure 14T, input interrupt control, i.e. interrupt
Since this is not a cycle operation, the output signal 80101 is incontrovertible.
The logical value becomes zero. In the input situation, that is, input data manipulation
Therefore, the output signals 78111 and 78208 have a logical value of zero.
Ru. Therefore, the multiplexers 783 to 798
Terminal "0" input is selected. In Figure 14-0, data bus information is
are stored in registers 367 and 368. control information
information is a record whose output signal is always available.
It is stored in the register 391. AND gate 369
The output of
- Since this is not a clear operation, the logical value will be zero. Faith
Nos. 47005 and 46406 have a logical value of zero. Therefore, the cash register
The output signals of stars 367 and 368 are shown in FIG.
given to iad OR gates 332 to 348.
Ru. Is the output of the wired OR gate a memory response at this time?
D files 364 to 366 in Figure 14-0 of et al.
Reverse the data stored in 177, 647, 389.
to project. Therefore, during all transfers, the data in Figure 14T is
Data passing through data multiplexers 783 to 798
is register 84 of the intercommunication bus in Figure 14AA.
9,851,853,855. Dora
The output signals for the drivers 848, 850, and 852 are
Reflected at the receiver in the local ISL. Remote
In this case, the strobe from ISL is local ISL.
Induces remote MRSCYR. In Figure 14U, signal 86712 is in register 8.
13 inputs. Signal 92305 is a logical value
When 1, the output signal 81310 is placed on the internal bus,
Local ISL as signal 81403 in Figure 14AB
sent against. This signal is localized as signal 66219.
Received at ISL and driven as signal 81505
reflected on the output side of the bar 815. In Figure 14V, signal 81505 is a NOR gate
is applied to the input side of H.269. The output signal 26912 is
Flop 441 and remote cycle flop 572
remote support in local ISL by setting
start cycle. In Figure 14N, the signal 81505 with a logical value of zero and
57206 is given to the input side of NAND gate 499.
Ru. The output signal 49901 with logic value 1 is OR gate 49
5 on the input side. MYSCYR signal 49511
is applied to the input side of inverter 494. output
Signal 49404 is a logical zero. In Figure 14X, MRSCYR signal 49404
is a memory tie, which is one of the timers 133 in FIG.
reset the marker 611. MRSCYR signal
49404 is connected to the CD terminal of D-flop 502.
The storage timeout signal 50509 is
Maintains logic value 0, and signal 50508 maintains logic value 1
do. Signal 49404 is connected to NOR gate 378 in Figure 14G.
given to the input side. Output signal 37808 is the 14th D
applied to the input side of AND/NOR gate 278 in the figure.
It will be done. Cycle 10 where signal 76208 is logic 1
0, in time, the clock bus signal
27808 is a logical zero and the clock bus 27908 is
The logical value becomes 1. In the remote ISL cycle in Figure 14T
As mentioned above, the selection signals 78111 and 78208 are common.
is a logical zero, multiplexer 7
Select terminal 0 inputs from 83 to 798.
The data outputs of these multiplexers are
In diagram G, multiplexer register 525
528 input signals. clock belief
No. 27808 is multiplexer register 525 to
528 to multiplex the data.
Clock to lexer register. Signal 27908 too
Also, set the bus full flop 271 to remote ISL.
Any further traffic from the local communication bus
ISL cycle in local ISL to gain access
prevent the occurrence of The address of the source requesting this data is
Data file RAM 364 to 36 in Figure 4-0
6,177,389 and 647.
In this case, location 2 is read. this is
Since it is MRSCYR cycle, NAND gate 4
02 signals 49014 and 90704 are logical 1,
The output read selection signal 40211 has a logical value of zero. Faith
No. 49404 is a logical value on the input side of NAND gate 403
It is zero, and the output read selection 2 signal 40312 is a logical value.
It is 1. The source address is the storage request for the first half.
Written to location 2 from the beginning in the cycle
It is something that During this second half-cycle, the source
Address is RAM364-366,389,64
7 through registers 367, 368, 391
and multiplexer 1 in FIG. 14E.
57 to 160 and to remote cycles as described above.
communication address via registers 507 to 509.
reflected on the response bus. In the 14N diagram, MRQ full flop 4
87 is set during the first half storage request cycle.
No more communication bus data
is prohibited from being written to a memory location in MRQ RAM.
Stop. Signals 76208, 49511, 39006 with logic value 1 are
Provided to the input side of AND/NOR gate 488
Therefore, the flop 487 is reset. logical value
The zero output signal 48808 is the same as the zero output signal 28306.
The input of OR gate 283 which resets pin 487
given to the power side. Not a double memory cycle command
Therefore, signal 39006 has a logical value of 1. data required
Ends the read cycle operation by sending it back to the requesting source.
A communication bus cycle is generated that completes the process. Frotz
By resetting the key memory path 487,
Allows for more communication than that. If a NAK response is received for the first half read request,
If there is an answer, please check the local 6 microphone in Figure 14Y.
One shot 611 in Los Angeles is timed out.
Set flop 502. first half request
has already been questioned and the requester has given the second half of the answer.
A second half-cycle is generated to expect
Uncorrectable memory read events with incorrect parity
indicator is set. For this reason, the requester
data received in the second half-cycle to
Don't let them use it, and let them try again in some cases. Set a number of events that caused flop 502
When the signals 50209 and 43705 are connected to the AND gate 5
01 input side. This ISL is idle
Therefore, signal 43705 has a logic value of 1. output
Signal 50108 is the clock signal of D-flop 505.
set the flop by being given to the terminal
to As mentioned above, the output signal 50509 is the storage timeout.
This is a status bit that displays the current status. Logic value 1 signal
50209 and 50509 are inputs of NAND gate 503
given to the side. Output signal 50306 is OR gate 6
20 inputs to generate a timeout signal.
No. 62008 is set to logical zero. Signal 50306 is inverted by device 504 to
In the 14N diagram, signal 50408 is OR gate 49
given to 5. The output signal is 49511
MRSCYR generates local ISL cycles. this
Cycles are the second half response of remote storage. In Figure 14V, signal 62008 is an AND gate
799 input side. For this reason, the receipt
Full flop 874 is the generator enable signal
This prevents forcing 79911 to a logical 1.
This allows the use of receiver 815 in Figure 14AB.
prevent the state of being incapacitated. For this reason, the remote ISL cycle
Prevent initiation. In Figure 14V, the signal 62008 with a logical value of zero
is provided to OR gate 412. output signal
41206 is given to the input side of NOR gate 176.
Ru. Output signal 17612 is local cycle flop
464 and ISL cycle cycle flop 44
Begins the sequence of setting 1. NOR game
The signal 41206 given to the port 608 is the output signal
60808 to a logical zero, which causes the flop
Forces the CP input to 464 to be a logical 1.
Therefore, flop 464 is set and the remote site is
Prevents the clock flop 572 from setting
We guarantee that Signal 46405 is the clock input side of register 490
given to. However, the signal 41206 with logical value is
It is applied to the input side of OR gate 287. Output signal
No. 28708 resets register 490 and
The clock signal applied to register 490 by
Override 46405. Therefore, the local size
All functions of Kuru will be enabled. Assuming a NAK response is received from memory
However, it is still necessary to respond to the source.
Ru. However, the data received is invalid due to the source.
In order to indicate to the source that the
Generates an "improper parity" condition. In Figure 14G, signal 62008 is the inverter
621 input side. Logic value 1 output signal
No. 62112 is given to the input side of OR gate 349.
Ru. A logic 1 data parity error signal is
It is applied to the input side of register 523. clock
When signal 27908 goes to logic 1, data parity is
The output signal 52302 is the parity generator 521
is given to the input side of 522, which allows even numbers to be
Generate parity. Output signal 34911 is OR gate
392 input side. Output signal 39208 is
It is applied to the input side of register 523. output signal
52309 is given to driver 254 in FIG. 14B.
is transmitted to the communication bus as BSREDD signal 10338.
sent to indicate an uncorrectable error. NOR game
The signal 49404 given to the input side of the gate 378 is
In Figure 14D, the input of AND/NOR gate 278
Usable second half bus cycle given to power side
Generates signal 37806. AND/NOR gate 27
The cycle 100 signal applied to the input side of
Generates lock bus signal 27808, which is the data
and addresses in the regular MRSCYR cycle.
Strobe the communication bus registers to
generates a signal bus request. The retry request (RRQCYL) route is
block, interrupt and special I/O load instructions
I/O request storage using the unique feature IOLD, which is
Used for reading. Receiving a retry request command from the local communication bus
can cause ISL to generate up to 4 cycles.
Ru. This initial cycle starts from the local ISL to the remote ISL.
It is RRQCYL that transfers information to. RRQCYRsa
cycle generates a telecommunication bus cycle.
For output commands or interrupts, this indicates completion of the instruction.
Become. The retry path is based on the actual response from the telecommunications bus.
The Bureau is used for these orders requiring
The section ISL uses the bus in Figure 14B instead of the telecommunications bus.
response to standby signal 26201. Therefore, the actual response
The answer is obtained from the remote bus and the information is stored during the comparison cycle.
is returned to the local ISL which is sent back to the requesting source.
Ru. In the case of a read command, the first half is immediately requested.
is generated on the telecommunications bus, the local ISL is recorded.
Remote second half response as in memory read request.
Wait for the answer. In Figure 14S, in the MRQ cycle,
To start the RRQCYL cycle, as described in
The RAM is cycled during the DCN time
Ru. If this command is
If it is a Tsutolock or an IOLD command, this command is
The command is the conversion data from the output of RAM706 to 715.
data is loaded into registers 718 and 719.
It requires that These registers are
Clock storage signal that is input to converter 738
Clocked with 73806. Input signal 28106 is the 14th
In figure I, the output of AND/NOR gate 281 and
is generated. This input has signals 53910 and 58405
be. Therefore, the clock pulses are as shown in Figure 14N.
RETRY REQUEST FULL flop 584
Generated in data transfer mode when set
be done. This stores the data in registers 718 and 719.
to strobe. This data path is as follows
It is. In FIG. 14R, the NAND gate 481
Bus storage reference signal 24414 input to logic zero
Therefore, the terminals of multiplexers 474 and 475 are
The terminal “1” input is selected. Also, this is
Since it is in data transfer mode, signal 53911 is logic
The value becomes zero and therefore multiplexers 472 and 473
Terminal 0 input of is selected. For this reason,
data bits 0 and 1 and the upper address
Bits 0 through 7 are selected. multiplex
The output signals of the sensors 472 to 475 are as shown in FIG.
Addresses in RAM863 and 706 to 715
is given to the input side of the terminal. In Figure 14R, the channel mask add
The response signal is sent to multiplexers 313, 314, 31
5 is selected. Multiplexer 313,3
Terminal 0 input of 14,315 is selected.
Bus address signals 8-17 go to terminal 0
Given. RAM276 uses these outputs
A channel mass addressed to a logical 1
Bit signal 27607 is input to AND gate 546
given to the side. This is not test mode
Therefore, the function signal 62203 has a logic value of 1. operation signal
No. 53910 and memory verification clear signal 48112 are AND games.
is applied to the input side of port 550. This is the excretion function
However, since it is not a memory standard clearing function, there is a lack of confidence in both
Nos. 53910 and 48112 have a logical value of 1, and the output signal
55011 has a logical value of 1. In Figure 14N,
The output signal 54608 with a logic value of 1 is the output signal of the OR gate 317.
given to the input side. Logical zero output signal 31704
is applied to the NOR gate 566 to output the output signal 56608
Forces the value to be logical 1. As mentioned above, the file selection signal with a logical value of 1
40802 and 41008 are applied to the input side of AND gate 585.
available. Signal 56608 with logic value 1 is AND gate 5
85 input side. This allows writing.
The flop 581 is activated at the same time as the output signal 64405 rises.
condition to be set. In Figure 14-0, this is the second half-bus
Not a cycle, but also a memory reference cycle signal
Signals 25914 and 24414 are moot because they are not 2594 and 2444.
Becomes a logical value. Signals 56506 and 47807 are also logic zero.
It is. Therefore, the data and address in Figure 14-0
Location 0 of dress files 92 and 103 is selected.
selected and the write enable signal 64408 is given.
Information on the communication bus is written to RAM. In Figure 14N, flop 584 is 135
Communication bus cycles in nanoseconds by DCN signal 35602
Set to In Fig. 14Y, signal 58405
is applied to the clock input side of D-flop 615.
It will be done. Signal 41811 is the rising point of clock signal 58405
CD terminus of flop 615 set at
Given to Naru. Output signal 61505 is AND gate
614 on the input side. output timer instruction
set by data bit 7 during
The timer enable signal 91410 becomes a logic one.
Bus timer signal 26102 is a 60 cycle pulse
give. Output signal 61402 is G2 available and 60 cycles
+1 of counter 619 that counts pulses
given to the terminal. This was mentioned earlier.
Beta. Using this timer/counter 619,
Detects malfunction in ISL. If this
If the detector is not used, the local communication bus will
Maintain machine mode. As mentioned above, the RRQ2DO signal 58109 is the 14th U
Transfer full time as illustrated in the figure.
to take the contents of the data and address lines (first
4N diagram) Generate RRQCYL cycle,
TRANSFER FULL signal 92305 is used for data and
clock the address line to the local ISL driver.
This data is stored in the data map shown in Figure 14T as described above.
Go to multiplexers 783 to 798. We will first explain the basic flow of information and
For differences with the main flow, test set
Memory read by lock, interrupt and IOL operations
will be explained. In Figure 14U, RROCYL signal 90002 is
Given to register 813. output signal
GENRRQ81367 is sent to the remote ISL as described above.
Ru. In Figure 14V, in the remote ISL, GENRRO
Signal 81606 is the input side of AND/NOR gate 578
given to. Signals 57410 and 27108 are AND/NOR
It is applied to gate 578 and has a logic value of 1 at this time.
Ru. Output signal 57808 is a logic zero. As mentioned above, delay line 374 is enabled.
and an output clock signal is generated. In Figure 14D, the argument for remote cycles is
Logic value 1 remote function signal 57410, cycle 100 signal
76208, operation signal 53910, and RRQCYR signal
90201 is given to AND/NOR gate 278,
This allows clock bus signals 27808 and 27908
generate. Clock bus signals 27808 and 27908 are
Open timing for telecommunications bus cycles
At the beginning, as mentioned above, during this cycle the remote ISL
Address the specified device on the address bus.
Set. In Figure 14H, all inhibit signals have a logic value of 1.
No. 42103 RRQSET signal 58506 and comparison signal 31808
is applied to the input side of AND gate 447. Out
The force signal 44706 is applied to the input side of the OR gate 629.
It will be done. Output signal 62906 is input to register 631
given to the side. Output signal 63102 is inverter 6
30 inputs. Output signal 63006 is
is applied to the set terminal of loop 452,
This sets the flop. output signal
45309 is given to the driver/receiver 263,
Signal 26201, which is the BSWAIT signal, on the local communication bus
Leave it behind. Local ISL generates a comparison cycle
Until then, wait responses will continue to be generated. 6 In Figure 14I, the telecommunications bus ACK response
Answer signal 17803, NAK signal 2484, or standby signal
26303 is stored in register 413. output signal
41303 and 41306 are applied to OR gate 415.
Output signal 41511 is the input of AND/NOR gate 570.
given to the power side. During the MYRRQR cycle, far
Register 515 when a request is placed on the communication bus
The signal 51515 stored in is a logic one. output
Signal 57008 is applied to the input side of OR gate 270.
This generates bus clear signal 27006.
and reproduce the bus full flop 271 in Figure 14G.
Set. Remote response signal 57008 is the driver in Figure 14AB
894 input side. Output signal 89409 is
14AC to resistor bank 658.
Output signal 65802 for transmission on the ISL internal bus
connector 663. Signal 66237 is
Input to driver 733 in Figure 14AB
received at a local ISL. The output signal 73305 is
ACK/NAK response signal generated on the telecommunications bus
14th to store 73614/73616 in local ISL
applied to the clock input of register 768 in Figure P.
Ru. Signals 73614 and 73616 are NAND gates 579
is given to the input side of Output signal 57913 is register
data 568. If NACK or ACK response
If no response is received, the wait response is
It is stored in register 568. In Figure 14I, the telecommunications bus cycle
In the system, register 577 is the input terminal.
Given to ACK signal 17803 and NAK signal 24814
Ru. Register 413 also has ACK signal 17803 and NAK
Store signal 24814. At the output of register 577
One remote ACK57710 and one remote NAK57707 are the 14th
Provided to the input side of driver 913 in the AB diagram,
These are the force signals 91312 and 91314 and the signals 66241 and 66242
A local signal applied to the input side of driver 736 as
Send to ISL. Output signals 73614 and 73616 are
Given to the input side of NOR579 in Figure 14P
It will be done. If this special signal has a logical value of zero, the output
The force signal 57913 is a regenerated WAIT response logic
The value is 1. Remote response 73305 was received and sent to Regis.
When the C input of the controller 568 rises to a logical value of 1,
Three remote response signals 57913, 73614, 73616 are
It is stored in the star 568. This response signal is
must be sent back to the requesting source on the communication bus.
Therefore, the bus comparator 93 in FIG.
A comparison cycle is generated using remote straw
QUE2DO signal 89610, QUE2DO signal 55604, and
RECEIVER FULL signal 87407 is AND gate 54
given to 3. At this time, the three signals mentioned above have a logical value of 1.
Therefore, the output signal 54312 has a logical value of 1 and the local
Indicating that there is no cycle of active states in ISL.
vinegar. Output signal 54312 is on the input side of OR gate 420
Given. Available idle output signal 42011 is D-
Applied to the CD terminal of flop 437.
During the next DCN cycle, before clock signal 21510
The edge sets flop 437. ISL idle signal 43705 is input to AND gate 311
given to the side. On the input side of AND gate 311
Given is NO CYCLE signal 54312,
TEST REMOTE signal 53914 and COMPARE
ENABLE signal 30108, these are all logical values
It is 1. input to NOR gate 301
REMOTE ANSWER VALID signal 56803 is
Since the logical value is zero, OUTPUT COMPARE
The ENABLE signal 30108 has a logic value of 1. Output signal 31106 is a comparison D-flop 29
This flow is given to the clock terminal of 7.
Set the tup. Output signal 29709 is AND gate
299 input side. All beliefs are logical 1.
Nos. 41008, 40802, and 43705 are also inputs of AND gate 299.
given to the power side. Logical 1 signals 41008 and 40802
indicates that the RRQ location of the D-file is selected.
indicate. Output signal 29908 is output from D-flop 318.
CD terminal, this flop is a signal
60 nanoseconds after initiation of DCN by 36008 and
Set 60 nanoseconds after loop 437 is set.
Ru. During the comparison cycle, the local ISL is shown in Figure 14-0.
stored in data and address files.
Read out the information and use it as a bus comparison controller in Figure 8.
The internal communication port in FIG.
received from comparators 380 to 398 of
Compare against information. bus address signal
BSAD0~23 are given to the B input terminal,
Addresses 0 to 23 signals 13201 to 15601 are comparators.
to the A input terminals of the controllers 384 to 386.
It will be done. Bus data signals BSDT0-15 are B type.
DFIL0 to 15 signals are applied to the A terminal.
- given to the terminal. Output signal 38009, 38109, 38209, 38309, 38409,
38509 and 38609 are 330 ohm resistors 115
Wide OR gate 37 ending at +5 volts at
9 is applied to the input side. If received from communication bus
The information is on the ISL D and A files.
If it is the same as the one stored in RAM,
The output signal 37901 has a logical value of zero. If two sets of feelings
If the information is not equal, the output signal 37901 is a logic zero.
and the source from which this information started the original cycle
or not originally started.
information for different cycles from
Show that. Signals 37901 and 31808 with logic value 1 are AND gate 2
73 on the input side. Output signal 37208 is
is applied to converter 272. Logical zero output signal
No. 27204 is given to the input side of AND gate 542.
It will be done. If the result of this comparison shows equality
If so, the output signal 54212 has a logical value of zero. In Figure 14H, the comparison signal with a logic value of 1 is
It is applied to the input side of AND gate 170. or,
What is applied to the output side of AND gate 170 is
These are signals 56807 and 59906 with a logical value of 1. output signal
17012 is given to register 631 and is 135 nanoseconds.
Stored in DCN signal 35809. Output signal 63112 is
It is applied to the input side of NOR gate 130. logic
An output signal with a value of zero generates an ACK signal as described above.
The ISL ACK flop 433 is set. In case of NAK, signal 56815 is combined with signal 17208 and
and 27308 in NAND gate 171.
The value becomes 1. OR gate 526 logic zero output
Signal 17112 connects signal 53806 to the input side of register 631.
to set the logical value to 1. Output signal 63105 is D-Flow
is applied to the clock input of pin 449.
Set the ISNAKR flop. output signal
ISNAKR44909 is sent on the communication bus as described above.
It will be done. Bus equalization clause that causes ISL to remember WAIT responses
For cases, signal 56810 is an AND/NOR gate.
174 on the input side. Also AND/NOR game
At this time, a logic 1 signal is applied to port 174.
Nos. 27308 and 59906. Output signal 17408 is
is applied to the input side of inverter 175. output signal
17506 is given to the input side of register 631.
Output signal 63109 is the clock input of flop 453
given to the side, which sets the flop.
Ru. This condition causes the BSWAIT signal to be sent on the communication bus.
Ku. If there is no comparison, the signal in Figure 14P
If 37901 was a logical zero, signal 27308 would be logical.
The logical value becomes 0, and the signal 27204 becomes a logical value 1 and becomes reliable.
Force No. 54212 to logical 1. AND/NOR gate 174 in Figure 14H
For signal 54212, NAK RETRY signal 53903,
and address signal 31910 are at logic 1 at this time.
Therefore, output signal 17408 has a logical value of zero. this
As a result, the flop 453 is set as described above,
The BSWAIT signal is sent on the communication bus. If this is NAK RETRY or CP address
signals 53902 and 32008 have a logic value of 1.
and is applied to the input side of AND/NOR gate 541.
available. Signal 54212 with logic value 1 is AND/NOR
Since it is applied to the input side of gate 541, the logical value
1 output signal 54106 is the input side of NOR gate 538
given to. Output signal 53806 is register 631
is given to the input side of Output signal 63105 is ISL
Set the NAKR flop 449 and use
Sends the BSNAKR signal on the communication bus. End of local RRQ cycle for write command
is as follows. i.e. ACK from remote ISL
In the case of a response, the signal 56807 in Figure 14H has a logic value of 1.
It is. As mentioned above, this allows signal 17012 to be discussed.
set to a logical value of 1, which causes ACK to be sent to the internal communication bus.
Return it to the source of the requester above. Signal 17012 is logic
The value is 1, and the write signal 36609 follows the logic in Figure 14N.
The logical value is 1. AND/OR gate 286 outputs
No. 28608 is discussed at the input side of OR gate 293.
This further changes the output signal 29308 to a logical value.
make it zero. The signal on the R input side of JK flop 584
Issue 29308 resets the RRQ feature and therefore requires another
Opens the RRQ path for instructions. In Figure 14AB, ACK for reading
ACK signal 17012 in case of response is file write signal.
80504 to AND gate 732.
Generates force signal 73203. Signal 73203 is for remote ISL.
and returned. Reception at remote ISL in Figure 14N
Signal 73309 taken sets flop 593.
Ru. Flop 593 indicates that the second half cycle is locally
It is allowed to be sent to. The order is also NAK in read or write commands.
End with a response. In Figure 14H, the logical value zero
The output signal 17112 at is the input of OR gate 536.
given to the power side. Output signal 53603 is shown in Figure 14N
is given to the input side of the OR gate 293 at
This resets the flop 584 as described above.
do. In Figure 14H, in the comparison cycle
Then, reply waiting signal 17508 is input to register 631.
given to the side. The output signal 63109 in Figure 14N is
D-Flop 632 clock terminal
available. Output signal 63209 is NAND gate 559
is given to the other input side of . Output signal 55906 is
Set loop 581 and try again as described above.
Initiate the request fulfillment cycle. The RRQ cycle sends a response ACK or
Iterates until a NAK is sent. At this time, the effect of WAIT is
command by keeping push button 584 set.
is to try again. In Figure 14Y
is, the reset input signal 58406 is a logic zero, and
This makes the counter 619 usable.
However, this counter is part of the timer in Figure 8.
Consisting of situation logic unit 133. Signal 61412 goes to 60
Apply Ruth's pulse to +1 and G2 terminals
Ru. If the WAIT response lasts more than 120ms
If so, signal 61907 is forced to a logic one. this
state sets flop 599, ACK received
Therefore, the signal 61608 has a logic value of 1. 1st
In the 4H diagram, the signal 59906 with logical value is AND
is applied to gate 170. Signal 17012 is a logical value
This is zero, which prohibits ACK responses. Similarly, signal 59906 is the input of OR gate 172.
given to the side. The logical zero output signal 17208 is
It is applied to the input side of NAND gate 171. theory
The logical value 1 output signal 17112 inhibits the NAK signal.
Signal 59906 of AND/OR gate 174 is a standby response
is prohibited, so there is no response at all. This results in local
The local center can cause timeouts on the ISL bus.
available for that channel number for the processor
signals that there are no available resources. to this address
However, even if ISL is configured, the timeout occurs.
Understandably, the software will explain why the device is inactive at this time.
state or is this the RRQCYR site?
If you receive a response to a message like an error,
whether you have configured an incorrect ISL to generate
will have to investigate. 14th G
Regarding gate 524 in the figure, the RRQCYR cycle
When a file is generated, signal 39310 is a read request.
The logic value is 1 because the Output signal 52408 is logic
value zero, which allows data multiplexing
ISL address for service registers 525 to 528
Select response input. Also, this is the interrupt cycle
Or, because it is not a memory read request cycle, the data
The signal 51303 at bit 10 is a logic zero.
When a response cycle is received from an external device, the data
Address bit 10 is a logical zero address bit 1.
It is received as 8. This is the game in Figure 14-0.
Forces output signal 47808 of gate 478 to logic value 1.
Ru. In Figure 14-0, the second half bus cycle
is received, signal 25914 will be a logic one.
Bus lock is not set and therefore signal 24102
has a logical value of 1, so file write selection 1
Signal 40903 has a logic value of 1. Signal 47603, 56506,
47808 is a logical 1 and therefore the file write
The selection 2 signal 41106 has a logical value of zero. Therefore, compassion
The information is stored in file registers 92 and 1 in FIG.
The address and data in Figure 14-0 which is 03
Memory location 1, which is the retry response location for the data file.
written to. In FIG. 14N, the signal 41008 with logic value 1,
40903 and 44006 are applied to the input side of AND gate 598.
available. Logic 1 output value 59808 is JK flop
595 given to CJ terminal, write bus
Enable signal 64405 is applied to the clock input,
This sets the flop. Local ISL
When sending an ACK response back to this remote ISL, the clock signal
73309 is forced to logical value 1 as mentioned above, so
A retry responsive flop 593 is set.
Signals 59509 and 59305 are fed to NAND gate 487
It will be done. Output signal 58703 is fed to inverter 58810
It will be done. 14V showing the cycle generator 146 of FIG.
In the figure, signal 58703 is the input of NOR gate 645.
given to the power side. Output signal 64508 is AND/
Provided to the input side of NOR gate 388. logic
A signal 92306 with a value of 1 is applied to the other input side. theory
The logical zero output signal 38808 is output from the flop as described above.
By setting 464 and 441, the local site
Generate cycle and ISL cycles. signal 58810
is strobed into register 490. output signal
49007 is given to the input side of AND gate 590,
This generates RRSCYL cycle signal 59012.
Ru. Next, the ISL cycle runs through the delay line 374 as described above.
Generate a timing signal from. The data path is
It is the same as for the memory response cycle. Remote
Data such as in the cycle is shown in Figure 14U.
Local when send full flop 923 is set
Sent back to ISL. Signal 59012 is applied to the input side of NOR gate 909.
It will be done. Output signal 90910 is input to register 813
given to the side. Generated RRS signal 81315 is local ISL
sent to. Signal 66221 is sent to driver 815 in Figure 14AB.
received from. Output signal 81503 is output from the station as described above.
Start a remote cycle in the section ISL. This de
The data path is connected to the MRS cycle remote ISL as described above.
Same as route. At the local ISL in Figure 14N, the RRQ
The file flop 584 is reset as shown below.
Ru. Signals 59211 and 76208 are AND/OR gate 286
is given to the input side of Logical zero output signal
28606 is applied to the input side of OR gate 293.
Output signal 29308 resets flop 584. At the remote ISL, the RRSCYL site is shown in Figure 14N.
RRS full flop 5 when a crack is occurring
95 and RRS ENABL flop 593 is reset
be done. Signals 59012 and 32712 are NAND gates 59
6 on the input side. Logical zero output signal
59603 is applied to the input side of OR gate 294.
Output signal 29411 resets flops 593 and 595.
to tsut. In Figure 14Y, in the case of reading, the local ISL flap
Loop 616 is set because the ACK is received.
This forces signal 56807 to a logic one.
Signal 27308 becomes a logic 1 after the equalization comparison cycle.
Ru. Signal 61608 with logic value zero is CD of flop 599
is given to the terminal, which causes the flop to be set.
to prevent being attacked. Signal 58406 is a logical value
1, the timer/counter 619 is reset.
Ru. An acknowledgment of the request for a read cycle is received.
The ISL is about 240 milliseconds for read operations after
Wait for 1 second. Output signal of counter 619
61912 is applied to inverter 618. input signal
No. 61808 is the D-flop 456 clock
given to the terminal, which sets the flop.
do. Output signal 45605 with logic value 1 is AND gate 4
55 on the input side. As mentioned above, when the ISL becomes idle, the logical value is 1.
The signal is given to the other input side of the AND gate 455.
It will be done. Output signal 45511 sets flop 459.
to Output signal 45909 is the I/O timer status bit.
It's Tsuto. Signals 45909 and 45606 are inputs of AND gate 457
given to the side. Output signal 45711 is inverter 4
58. Output signal 45711 is OR gate
620 on the input side. Logical zero signal
62008 is the timer and status logic device of Figure 8.
This is the timeout generator signal. this
The function of the signal is to avoid parity errors as described above.
It is to urate. In Figure 14N, signal 46108 is a dummy
OR game that generates RRSCYR cycle signal 59211
is applied to the input side of port 592. The sequence is timed out in Figure 14Y.
It is generated via counter 619. RRQ full
The regularity of the standings ends when the flop is reset.
This counter will be reset. Frotz
615 is reset by signal 29308. theory
Signal 61505 on the input side of logical zero AND gate 614
prohibits 60 hertz timing pulse 26102.
Ru. RRSCYR signal 59211 and end pulse signal
37712 is given to the input side of AND gate 594.
Ru. Output signal 59406 is the input side of NOR gate 432
given to. Output signal 43201 outputs flop 456.
Reset. Reset timer bits
Flop 459 remains reset until the output clear command is issued.
Not set. IOLD is an input/output command that requires two cycles
It is. The first cycle (RRQCYL) is local
ISL and the second cycle (RRQCYR) is far
Located in ISL. The IOLD command specifies the storage address data.
data is one of both the address and data fields.
It is unique in the way it operates. This IOLD finger
The first part of the instruction is the output register part. ad
The response 0-7 signals are used by the controller during DMA operations.
Display the storage address used by. rest
The address 8-23 signals are the data 0-15 signals.
be. The second part of the IOLD command is another I/O command.
is the same as In Figure 14S, as mentioned above, the DCN support
During the cycle, the memory address conversion RAM 1 in FIG.
The storage conversion RAM 706 to 715 consisting of 25
A memory reference having a memory reference register 126 shown in FIG.
data is loaded into registers 716 and 717.
Loading standard I/O commands to data files
During printing, this becomes a retry path command. Memory
The conversion bits are not in registers 716 and 717.
IOLD configuring IOLD register 127 in Figure 8
Notice that it is loaded into registers 718 and 719.
put out. Signal 73806 implements this selection. 14th
In the I diagram, the logic 1 signals 53910 and 57405 are
Inputs of an OR gate with ANDed inputs 281
given to the side. The output signal 28106 is as shown in Fig. 14S.
is applied to inverter 738. Output signal 73806
is the clock terminal of registers 718 and 719.
is applied to the storage conversion RAM 706.
Clock data from 715 to each register
do. Data and addresses in Figure 14-0
RRQCYL cycle following RAM loading
During this period, the available terminals of registers 718 and 719
The signal 48603 given to the null becomes a logical value of zero,
This allows output of registers 718 and 719
Make it. Also, in Figure 14L, the local RRQCYL service
During the cycle, addresses 18, 19, 21, 22
signal and signal 64706 are the inputs of NAND gate 829.
given to the power side. All inputs are logical zero
When signal 58306 is logic 1, output signal 82906 is logic 1.
given to the input side of AND gate 828, which has a logical value of 1.
It will be done. Output signal 82803 is input to AND gate 827.
given to the power side. Signals at addresses 20 and 23
15301 and 15601 are applied to the input side of AND gate 827.
and if these are logical 1, then the logical value
1 output signal 82706 is the input side of inverter 826
given to. The logical zero output signal 82610 is 16
Signal 15301 with address 20 to 23 in base 9,
15401, 15501, 15601.
vinegar. Storage address multiplexer 100 of FIG.
In Fig. 14R showing the memory verification signal 24414
, master clear signal 47006, and operation signal
53910 is given to the input side of NAND gate 481
Ru. Since signal 24414 is a logic zero, the multiplex
The selection inputs of lexers 474 and 475 have a logic value of 1.
Ru. Selector signal 53911 has a logical value of zero;
Terminals of multiplexers 474 and 475
Select 1 input. Therefore, for BSDT0 and 1
Signals 18905 and 19010 are signals 47507 at addresses 8 and 9
and 47409. BSAD0~7 is Maru
Terminal 0 input side of multiplexers 472 and 473
signals 47212 at addresses 0 to 7,
47209, 47207, 47204, 47312, 47307, 47304
selected. In Figure 14S, address 0 to 9 signals are recorded.
Address selector for storage conversion RAM 706 to 715
- given to the terminal. Data 6 to 15 signals
33901 to 34801 are given to the input terminal and are
RAM 706 at the specified address during configuration
715. Output signal 70607~
71507 is the input side of IOLD registers 718 and 719
given to. In Figure 14T, signal 82706 is multiplexed.
is given to the selection terminal of Kusa 930, and this
Address conversion 8 and 9 signals 72801 and 72901
Select. In Figure 14Z, the IOLD signal with a logical value of zero
82610 was applied to the input side of OR gate 911.
Output signal 91108 is multiplexer 832 and 835
is given to the selection terminal, which causes the terminal
Select null 0 input. address translation
Data 0 to 7 signals 72001 to 72701 are address conversion
These are the remaining 8 bits of RAM. of this cycle
The rest are the same as other operation input commands. This de
data is transferred to the remote ISL and standard data and
information to the telecommunications bus according to the address route.
Ru. Next unique path or retry in RRQCYL
The path is a memory test and set lock instruction.
Therefore, this test and set lock are
This is one memory verification instruction that goes through the row path. to this
The reason for this is memory tests and set locks.
The bits on the memory board on the communication bus are
Testing. This bit indicates that the instruction can be executed.
It must be tested before we know whether it is capable or not.
If this system is configured to read each memory location,
Is the lock bit set even if the
You'll know what I do. Proper response is generated and similar
is returned to the I/O output instruction in a suitable manner. this is a memory
Since it is an instruction, proper storage addressing and
Notes for writing information to the correct file location.
Requires a memory conversion path. 14th section for file write selection logic
In Figure 0, Test and Set are unique functions.
on the communication bus. i.e. BSLOCK machine
It is Noh. This is a memory verification and BSLOCK instruction
It is. Also, in the second half bus cycle this
do not have. Signal 25914 is a logical zero and signal 24102 is
The signal 24414 is a logic zero and the signal 24414 is a logic one.
This selects file location 0 for the information path.
Ru. In Figure 14I, signals 62606 and 86307 are
Provided to the input side of AND gate 548. signal
86307 is the first RAM 125 in FIG.
The memory read from the memory RAM 863 in the 4S diagram
It is medium bit. Signal 62606 is the test operation signal
be. The output signal 54808 is the NAND game in Figure 14N.
is applied to the input side of port 480. Logic value 1 signal
24414 is given to the other input side of NAND gate 480.
It will be done. Output signal 56608 is the input of NOR gate 566.
given to the power side. Output signal 56608 is AND gate
Signals 40802 and 41008 given to the input side of 585
is a logical value of 1. Output signal 58506 is clock
When the signal 64405 becomes a logic zero, the flop 581 is activated.
condition to be set, which allows the test and
Opens the RRQCYL cycle for
start As in the previous RRQ cycle, the 8th
Memory conversion shared by the memory conversion RAM 125 in the figure
Data is loaded into registers 718 and 719 as described above.
must be coded. Test and set instructions
is executed in the same way as in the IOLD instruction in Figure 14Z.
data to the local multiplexer register of
must be transferred. In Figure 14Z, this is the RRQCYL size.
signal 58306 because it is a memory verification command.
and 64706 has a logical value of 1. This signal is a NOR game.
is applied to the input side of port 873. Logical zero output
Signal 87311 is applied to OR gate 911. theory
The logical zero output signal 91103 is connected to the ISL interface.
multiplexer registers 832 and 835.
given to the selected terminal, which causes the address
Select conversion signals 72001 to 72701. signal 87311
is given to the input side of OR gate 912, which
Address conversion signals 72801 and 72901 and memory verification
Select signal 64706 and file byte 38910.
The data part of this instruction goes through the regular data path.
sent to transmitter register and driver
It will be done. The rest of the address bits are standard address bits.
bus or internal address bus path. Remote
During subsequent remote cycles in ISL, remote
A few special features that must be set on the ISL bus
There is a control line. In Figure 14G, the local ISL is set as a logical value of 1.
The file lock signal 80401 generated in
It is applied to the input side of gate 466. output signal
46603 is given to the input side of AND gate 443
Ru. Logical 1 since this is not test mode.
The signal 53906 is given to the input side of the AND gate 443.
It will be done. Output signal 44311 is input to register 523
given to the side. Bus lock function is in memory
Keys for testing and reading set bits
- is. This bit is set when the bus lock is turned on.
will be tested. This bit is tested and if
This was already set in memory
is unavailable at this time and no NAK response is given.
This ends the instruction. This response is
sent back to local ISL for use by toware.
Ru. If this bit is not set, this
Set as a result of the instruction and the ACK response is local
Returned to ISL to execute special types of instructions
will be done. An event occurs that does not affect the operation of the ISL
Various types of set and test instructions
be. This test and set command is used for other communications.
Due to the state of memory in use or playback cycle
If you receive a WAIT response due to memory in
There is. In Figure 14I, from the remote cycle
The obtained standby response signal 26303 is sent to register 4 as described above.
13 will be loaded. Output signal 41310
is on the input side of the NAND gate 328 in Figure 14D.
Given. Signals 52305 and 51515 with logic value 1 are
It is applied to the input side of AND gate 602. output
Signal 60203 is applied to the input side of OR gate 633.
It will be done. Output signal 63303 is the other input side of NOR328
given to. The output signal 32806 is
given to the request retry D-flop
Set. The output signal is the input of OR gate 562
given to the side, which causes the communication bus request cycle
Start. controller to central processor on remote bus
However, the interrupt that is started is the RRQCYL restart as shown below.
Control the trial path. This interrupt is a standard I/
This is an O output command. This interrupt is used for retry within ISL.
Higher priority devices than those that already use the line path
Due to the fact that an interrupt can be initiated from
This is an instruction that passes through an ISL that requires special attention. subordinate
Therefore, if this route is in use, the information will be
must be processed before the intrusion is processed. subordinate
Therefore, this interrupt can be triggered by ACK, NAK or wait.
135 digits for a DCN cycle when sent on the
detected and responded to in seconds of response time.
Must be. In Figure 14M, signals BSAD8-12 are
It is applied to the input side of NAND gate 277. child
The output signal 19504 is ANDed similarly to the output signal 27705.
It is applied to the input side of gate 321. this is a memory
Since it is not a verification command, signal 24414 has a logic value of 1.
Ru. If address bits BSAD08-13 are
If the logical value is zero, the output of the AND gate 321 is
The logical value becomes 1. Signal 32106 is AND gate 320
is given to the input side of Operation channel mask signal
No. 54608 is given to the input side of AND gate 320.
Ru. Signal 54608 is connected to AND gate 546 in Figure 14R.
This is the output of Output of RAM 276 with logical value 1,
That is, the signal 27607 is applied to the input side of the AND gate 546.
available. In Figure 14M, output signal 32008 is DCN
RRQ FULL signal 58408 at time 135
It is set at the rising edge. This flop set
indicates that the interrupt is accepted by the ISL.
vinegar. At this time, if there is no comparison operation in Figure 14H,
If so, the signal 54212 with logic value 1 is an AND gate.
422 on the input side. Signal 32008 is
It is applied to the other input side of AND gate 422.
Output signal 42203 is given to the input side of register 631.
It will be done. Signals 54212 and 32008 are also AND/NOR gates
541 on the input side. Output signal 54106 is
Provided to the input side of NOR gate 538. output
Signal 53806 is given to the input side of register 631,
As mentioned above, the NAK response sent on the communication bus is
cause Also, the NAK interrupt function of signal 63119 is
It is applied to the input side of inverter 537. 14th
In diagram X, the output signal 53702 with a logical value of zero is D-
Given to the S terminal of flop 429, this
sets the flop 429. output signal
42905 is given to the input side of AND gate 395
Ru. RRQ FULL signal 58406 is given to other input side
signal when this route is no longer in use.
58406 is set to logic one. Output signal 39503
is applied to the input side of one shot 451.
Output signal 45113 is the driver/receiver in Figure 14B.
is applied to the input side of the bar 258 for 30 nanoseconds.
BSRINT signal 10406 is placed on the communication bus and this
Receives a NAK response re-presenting the interrupt to the ISL.
Check that the route is not in use at this time for the source taken.
and is displayed. If the path for interrupt is in use
Otherwise, the response back to this source is as above.
This means that it was a BSWAIT response. BSWAIT belief
The issuer will continue to issue the command until it receives a non-waiting response.
Let it continue to come out. Meanwhile, interrupts are sent to the remote ISL.
will be processed. In Figure 14M, the CP interrupt signal 32106 or
bus write signal 26510 is input to NOR gate 640.
given to the power side. Output signal 64013 is inverter
641 on the input side. The output signal 64104 is
RAM shown in Figure 14-0 as a file writing function
366 input side. In Figure 14W, the CP destination address map
Terminal 0 input of multiplexer 749 is selected.
It will be done. Therefore, the signal 14601 at addresses 14-17
14901 to 14901 are selected. CP channel address
Signals 74912, 74909, 74907 and 74904 are RAM7
54 address selection terminals.
RAM754 is used when the ISL is in ISL configuration mode.
to the central processing unit previously loaded by the configuration directive.
Store the translated address for. In Fig. 14Z, the output signals 75411,
75409, 75407, 75405 are multiplexer 840
given to terminal 0. Logic value 1 signal
43008 and 58306 are on the input side of NAND gate 910
Given. Output selection signal 91003 with a logic value of zero is
Terminal 0 input of multiplexer register 840
Choose power. Output signal 84015, 84014, 84013,
84012 will now be sent to remote ISL
ISL interface driver 115 in Figure 8
is applied to the input side of drivers 839 and 841.
available. These signals first load the ISL.
Displays the address of the central processing unit. In Figure 14M, signal 91003 is a NAND gate.
is applied to the input side of port 904. data 2 signal
33501 is given to the other input side of NAND gate 904.
It will be done. Also, data 0, 1, and 3 to 5 signals
33401 to 33801 are the input side of NAND gate 903
given to. Data bits 0-5, i.e. the 8th
The data bus 117 in the figure is a logical zero and is connected to another central
Represents one central processor that interrupts processors.
Show. The logic value 1 output signals 90305 and 90413 are an AND game.
is applied to the input side of port 755. Signal 58306 too
It is applied to the input side of AND gate 755. logic
The output signal 75506 with a high value is the output signal of the OR gate 927.
given to the input side. Output signal 92711 is the 14th
It is applied to the input side of register 845 in Figure AA.
The output signal 84505 is the driver 844 in Fig. 14AB.
is given to the input side of Output signal 84407 is an ISL input
signal 84407 to the interface bus.
given by the driver 803 at the remote ISL.
Received as input signal 66244. Output signal 80303
corresponds to the wired OR gate 926 in Figure 14AA.
It is given as follows. In Figure 14W, the output signal 92601 is D-
given to the CD terminal of flop 925.
It will be done. During the RRQCYR cycle at the remote ISL,
Signal 90201 with logic value 1 is input to AND gate 899
given to the side. Cycle 100 time odor
Therefore, the signal 76208 has a logic value of 1, and the AND gate 8
99 to the other input side. Output signal 89911
to the clock terminal of D-flop 925.
Given. Flop 925 is the next RRQCYR support.
It is set until cycle. Functional flop 925
I mentioned it before. Signals 33901 to 34201 of data 6 to 9 are shown in FIG.
configuring the CPU source address register 136 of
on the terminal 1 input side of multiplexer 756.
Given. Selection term of multiplexer 756
Since the signal 53910 given to the null is logical value 1,
Therefore, these inputs are selected. Output signal 75604,
75607, 75609, 75612 are CPU source conversion RAM 75
7 is given to the address terminal and this
The RAM is located at the correct CPU source address, i.e. in Figure 8.
Stores conversion information for selecting RAM113.
Ru. Signal 92601, which has a logic value of 1, corresponds to the data map shown in Figure 8.
The data multiplexer 137
is given to the select terminal of the server 780, thereby
CPU source conversion signal 75705, 75707, 75709,
Select 75711. In Figure 14G, signals 90201 and 39310 are
given to the input side of AND/NOR gate 254.
Ru. As mentioned above, the file write signal 80701 is
Since the temperature was 1, the inverter output signal was 39310.
has a logical value of zero. Therefore, the output signal 52408 is
Data multiplexer/register 13 in Figure 8
The bus data multiplexer register is 8.
Select the terminal 1 input of the
Data 6 to 9 signals 78007, 78004, 78009,
Select 78012. In the RRQCYR cycle,
Along with the outputs of other multiplexers as mentioned above, the
The output signal of multiplexer 526 is reflected on the communication bus.
This terminates the interrupt command. In Figure 14E, the address mark in Figure 8
The address map, which is multiplexer register 111,
The multiplexers 507 to 509 are connected to the local ISL.
Remember this address when sent. Figure 14G
, the data multiplexer signal is
plexer registers 525, 527, 528
is given to the terminal 1 input side. As mentioned above, the book
During loading operation, data 6 to 9 signals are
Terminal 1 input of multiplexer register 526
given to the side. During read operations, the data multiplexer register
Terminal 0 input of registers 525, 526, 527
Select the ISL channel address for this ISL.
Ru. These are the hexadecimal rotary switches in Figure 14J.
The signals are from the channels 101 to 103. As mentioned above
MYDAT10 signal 51303 is not supported for read operation.
logical 1 for write operations, logical zero for write operations
becomes. In FIG. 14D, the logic value 1 signal 57410,
76208, 53910, 90201 are AND/NOR gates 27
8 is applied to the input side of the clock signal.
Generate 27808 and 27908. Signal 27908 is the address
The signals 1 to 31 are sent to the register 507 in FIG. 14E,
Clock to 508,509 and send data 0 to 15.
The numbers are sent to multiplexer registers 525 to 528.
signal 27908 also indicates bus full flow.
271, which causes another remote ISL
prohibited. Output and input interrupt control instructions via ISL
So that a special translation of the CP address may occur:
Detected. Outputs with function codes 03 and 02 respectively.
Detection of force/input interrupt control is found in Figure 14M.
However, here, between interrupt control input/output instructions
Address 18 where AND gate 811 has a logical value of zero
21 signal is detected. This is a memory matching cycle
Since there is no signal, signal 64706 has a logical value of zero. logic
Output signal 81105 with value 1 is input to AND gate 810
given to the side. Signal 53910 is a logical 1;
Address 22 signal 15501 has a logical value of 1. output
Signal 81012 is for function code hex 02 and 03
The logical value becomes 1. Signal 81012 is OR gate 927
One input, this will hold the data during the RRQCYL cycle.
data and address information to the remote ISL.
A converted signal 92711 is generated. Output interrupt command
For instructions, the RRQCYL cycle is
address and data are the same as the
I'll have to take the road. The only difference is for remote ISL
This would be the converted signal 92711 sent out. RRQCYL
At the remote ISL during the execution of the cycle, the data is
Somewhat for signals 33901 to 34201 of data 6 to 9
Take a different route. In FIG. 14W, multiplexer 756
The signal of CP source address 0-3 which is the output of
There are 75604, 75607, 75609, 75612, these are
Address RAM757 that stores CP conversion data
specify. As mentioned above, the output signal of RAM757
is multiplexed due to the logic 1 state of signal 92601.
The selection is made by the bush 780. Output signals 78004, 78007, 78009, 78012 are the 14th
Terminal “1” of multiplexer 526 in Figure G
given to the input. Output information is sent to any central process.
The controller knows whether to interrupt the
Contains translated CP addresses. if
Once the central processor is configured within an ISL, this ISL
is the agent when generating a CP interrupt.
act. For input interrupt control instructions,
RRQCYL cycles are selected at the local ISL,
This was followed by RRQCYR cycles in remote ISLs.
is selected. In Figure 14W, as mentioned above, the remote ISL
Flop 925 during the RRQCYR cycle at
is set, which causes AND gate 928 to
Generates the function conversion signal 92505 given to the input side.
Ru. During the RRQCYR, the first half of the
request is sent on the telecommunications bus. controller is
Sending the second half response will cause this remote ISL device to
The position generates an RRSCYL cycle. output signal
92806 is a logical 1, which causes multiplayer
Select terminal “1” input for Kusa 749
do. RRQCYR without setting conversion signal 92601
Flop 925 remains set until the cycle is generated.
maintain. However, in the case of one input command,
This condition will not occur until there is an answer. multiplexer
749 output signal addresses RAM754
do. The data content of RAM754 is RAM757
holds the inverse transformation of , resulting in an output of interrupt control
The original data is returned to the central processor. In Figure 14AA, output signal 92306 is
Multiplexer registers 851 and 853
Select the terminal “1” input. multiplexer
851 is the CP destination 0 and 1 signal 75411 and
Select 75409. These signals are the output of data 6.
Force signal 85114 and data 7 output signal 85113
It will be done. Multiplexer register 853
output signals 85312 and 85313 of
Select CP destination 2 and 3 signals 75407 and 75405.
Choose. Also, data multiplexers 4, 5, 1
0, 11 signals 78707, 78809, 79307, 79409 are master
Inputs of multiplexer registers 851 and 853
given to the power side. Multiplexer register 8
The outputs of 51 and 853 are given to the driver,
Sent from the source CP when an output interrupt control command is issued.
is returned to the local ISL containing the remainder of the data.
Therefore, in ISL, the resulting communication bus
The cycle inputs data and requests interrupt control instructions.
Give to strike. System memory is the memory throughput
two storage requests for a single storage request to increase the
Send second half response (2 data words)
configured to The first word is the second half of the first
Double bull signal with logic zero during communication bus cycle
Issued at 10404. After about 300 nanoseconds, the second
A half cycle is issued and signal 10404 becomes a logic one. In FIG. 14N, as mentioned above, the logical value 1
signals 40903 and 41106 are sent to AND gate 500
It will be done. Signal 44006 also has a logic value of 1. output signal
50008 is given to the input side of NAND gate 373
Ru. Bus double bull signal 21006 is NAND gate 3
73 to another input. Writing logical value 1
Bus enable signal 64405 is separate from NAND gate 373.
is given to the input side of Logical zero output signal
37308 sets D-flop 352. In Figure 14V, the output signal with a logical value of zero
35206 is given to the input side of NOR gate 351.
Ru. Output signal 35106 is on the input side of register 490
Given. Output signals 49014 and 49015 are memory responses
Specifies the MRSCYC cycle. Signal 35205 and
35380 is applied to the input side of AND/NOR gate 388.
available. Is signal 35308 a logic 1 at this time?
, the output signal 38808 with a logic value of zero is set as described above.
generated ISL and local cycles by
to be accomplished. In Figure 14N, the signal 35502 with logic value 1
and 49015 are applied to the input side of AND gate 354.
It will be done. The signal 35205 given to the CD terminal is
Since the logic value is 1, at the rising point of signal 35411
Clothes of D-flop 353 set by
Output signal 35411 is given to the
It will be done. If TRANSFER FULL signal 64602 is normal
If the logic value is zero in the case of
Setting 53 resets flop 352
let In Figure 14-0, signal 35308 is a register
367, 368, 391 clock terminals
This is given to
RAM364, 365, 366, 177, 64
Stores 7,389 data and control output signals
Ru. The data is the record for the first memory response cycle.
This is latched to registers 367, 368, and 391.
The cycle of RAM364~366,177,6
47,389 memory response locations to a second memory response service.
Open for cycle. In Figure 14N, the first MRSCYL cycle
During this time, the logic number 1 signals 49303 and 37712 are NAND
It is applied to the input side of gate 375. logical value of zero
Output signal 37511 is applied to the input side of OR gate 350.
available. Output signal 35008 is output from flop 353.
is given to the set terminal, which causes this
At the end of the first MRSCYL cycle of the double response
and reset the flop. Second memory response service
During the cycle, output signal 50008 remains a logic value.
1 is applied to the input side of AND gate 496.
The logic 1 signal 21104 is the other signal of the AND gate 496.
given to the terminal. Logic value 1 output signal
49611 floats at the rising point of write enable signal 64405.
492 is set. In Figure 14V, the signal 49206 with logical value
is given to NOR gate 351 and separated as described above.
Strengthen MRSCYC. In Figure 14N
The output signal 35411 is again forced to logic 1
However, since the flop 352 has been reset, the D input
Signal 35205 has a logical value of zero. Therefore, the flop
353 is not set. Data flow within ISL
address flow is the first memory response size.
It is the same as that of Kuru. In Figure 14-0, the first MRSCYC size
During the cycle, data is stored in registers 367, 368, 3.
91. The clock input 35308 is
Forced to logic zero at the end of the MRSCYC cycle
Ru. During the second cycle, flop 353 is set.
When the trigger signal 35308 has a logical value of 1, the second memory response
The register is loaded with data from the cycle. If the interrupt control level register is not zero,
information is loaded and the correct CP address is connected to the channel.
Once loaded into a register, the ISL will
can generate an interrupt instead of itself. In Figure 14N, the interrupt channel register
register 819 and level register 857 are controlled by ISL.
Contains data that is used to generate interrupts.
Ru. Specified interrupt cycles are generated by ISL
This is not an interrupt that goes through ISL. In Figure 14X, as mentioned above, if
storage error or monitor timeout from remote ISL
detected and if the interruptable function is illegally stored or
If set for the watchdog timer,
The output of AND/NOR gate 895 becomes a logic zero.
That will happen. Also, if there is an illegal memory error in the local ISL
Or if a monitoring timeout occurs, the NOR game
The output of the signal 82406 of the gate 824 is a logic 1 and the output is floating.
823. Prohibition signal 82106 is
The logical value becomes 1. Flop 823 is set
The output signal 82309 is the input side of the AND gate 607.
given to. When the ISL becomes idle, the signal
43705 has a logical value of 1, and the output signal 60708 has a logical value
becomes zero, thereby setting the flop 427.
Ru. Signals 43108 and 42504 are logic ones. In Figure 14V, the signal 42708 with a logical value of zero
is applied to the input side of OR gate 412. logic
An output signal with a value of zero is provided to gate 287. theory
The logical zero output signal 28708 resets the register 490.
maintain the condition. Signal 41206 is NOR gate 6
Given on 08. Output signal 60808 is flop 4
64 CD terminals. Signal 41206
It is also provided to NOR gate 176. output signal
17612 is given to the input side of AND gate 604.
Ru. The rising edge of the output signal 60408 is at the flop 46.
Set 4 and 441 for local and ISL cycles.
and the output timing function of the delay line 374.
generate. Certain local cycles are in reset state
is not generated for register 490 held in
It is once again attracting attention. In FIG. 14D, the logic 1 signal 42709
and 76208 are on the input side of AND/NOR gate 278.
Given. Output signal 27808 is the communication bus cycle
data and address information on the bus.
Transfer to. In Figure 14M, the logic zero signal 42708 is
applied to the selection terminal of multiplexer 731.
and select terminal “0” input. output signal
73107, 73109, 73112, 73104 are CPs to be interrupted
Indicates the channel number and the multiplayer in Figure 14E.
It is applied to the input side of the bush 159. multiplex
The terminal “0” input of the sensor 159 indicates that this is the second
selected because it is not a half bus cycle, and the signal
37806 becomes a logical zero. Enable signal 42709 is
Since the logical value is 1, multiplexers 157, 15
8,160 is not enabled and its output is a logical value
It becomes zero. Also, the signal 42708 with a logical value of zero is a register
507 reset terminal, this
sets upper address bits 0 to 8 to logical zero.
to force. On the input side of registers 508 and 509
Bits 14 to 17 are available bits.
The address bus reset is a logic zero, except when
becomes. In Figure 14T, the signal 42708 with a logical value of zero
is applied to NOR gate 801. logical value 1
The output signal 80108 is thereby sent to multiplexer 7.
Select terminal “3” input from 83 to 798.
Ru. Data multiplexer 0-5 signals are logical values
It is zero. Data multiplexers 6-9 are interrupts
Displays channels 6 to 9 signals. data mal
Multiplexers 10-15 display level 0-5 signals
do. Level 0 to 5 signals are processed by the ISL to the central processor.
Displays the interrupt level. In FIG. 14G, the signal 42709 with logic value 1
is applied to the input side of AND/NOR gate 524.
Ru. The logic zero output signal 52408 is multiplexed.
Terminals of service registers 525, 526, 527
select the ``0'' input. However, AND gate
Signal 42709 input to 372 is logic 1
Therefore, the terminals of multiplexer register 528
The null "1" input is selected. Therefore, multiple
Lexer register 528 is a data multiplexer.
Signals 12-14 79607, 79509, 97909, 79809
Select. Multiplexer 527 connects MY DATA10 and
and 11 signals 51303 and 51406. signal 42709
and 79307 are given to the input side of AND gate 529.
Ru. Signal 42709 is logic 1 and OR gate 5
Since the signal 86606 given to 13 has a logical value of zero,
Therefore, signal 51406 is connected to data multiplexer 10.
Reflects the state of signal 79307. Similarly, signals 42709 and 79409 are connected to AND gate 53
0 input side. Output signal is OR gate
514 on the input side. Output signal 51406 is
State of signal 79409 of data multiplexer 11
reflect. In Figure 14J, signals 10307 and 39716 are
It is applied to the input side of NAND gate 434. Faith
Since signal 39716 has a logical value of zero at this time, signal 10307
reflects the state of the ISL channel address 8 signal.
Ru. Hexadecimal rotary switch 140-10 in Figure 8
1, 102, 103 are the output signals ISLA9-1
6 to multiplexer 435 and 436 terminals
Give "1" to the input side. Output signals ISIDA1~8 are
Figure 14G Data Multiplexer Register
526, 525, 527 terminal “0” input
given to the side. Therefore, when a communication bus cycle is generated,
The data present on the bus is accessed by the interrupted CP.
ISL and level that interrupt the CPU.
is the channel address of the file. In Figure 14G, signals 42709 and 80701 are OR
It is applied to the input side of gate 454. ISL writing
Signal 45411 is given to the input side of register 523.
Ru. The output signal 52306 is sent to the communication bus and this
Indicates that the interrupt is a write cycle. ISL is a NAK or ACK response from the central processor
Receive one of the following. If a NAK response is received
then the CPU follows the BSRINT signal 10406 on the bus.
cormorant. In this case the interrupt must be regenerated.
stomach. In Figure 14I, the NAK response signal 24814
is the end of MY DATA CYCLE NOW signal 51608
is applied to the input side of register 413. Output signal
No. 41307 is the clip of D-flop 431 in Figure 14X.
is given to the lock terminal, which allows the
Set the tup. The setting of flop 431 is
The BSRINT signal 10406 is sent to the central processor on the local bus.
No further interrupts from the ISL until received from
Prohibit generation. Signal 10406 indicates that the CP can accept interrupts.
This is the restart interrupt function that the CP generates when the restart occurs. Faith
No. 10406 is generated and the interrupt was previously memorized.
All these devices (because of NAK)
play. Signal 10406 is the dry signal in Figure 14B.
received by receiver/receiver 258. output signal
25806 is the input side of NOR gate 428 in Figure 14X
given to. The logic zero output signal 42801 is
Reset the button 431. If an ACK response is received, signal 41302 is
It is applied to the input side of NOR gate 426. output
Signal 42610 resets flop 823. death
However, in the NAK response, flop 623 is
Maintain the set state. Therefore, the input signals 43705, 43108, and
42504 and 82309 are applied to the input side of AND gate 607.
available. Output signal 60708 sets flop 427.
This causes the interrupt cycle to start as described above.
prohibit. This sequence is generated by ISL.
ACK response is received from the interrupted interrupt cycle
Continue until. The mass given to the input side of NOR gate 426
Clear signal 44806 resets flop 823.
to tsut. Various logic functions are described below. 1st
In the 4H diagram, signals 44512, 33108, with logic value 1,
21710 is given to the input side of NAND gate 555.
data parity errors are detected during ISL commands.
Display what has been learned. Logical zero output signal
55508 is applied to the input side of OR gate 536.
The output signal 53603 is the OR gate 293 in Figure 14N.
is applied to the input side of the signal 29308.
Then the flop 584 is reset. signal 55508
Also on the input side of NOR gate 538 in Figure 14H.
given, resulting in a NAK response as described above.
Ru. Signals 44006 and 25914 are inputs to AND gate 606
given to the side. The output signal 60606 is the second half
that an ISL address was detected during the
Generates an ACK response by displaying . In Figure 14J, signals 93212 and 10114 are
It is applied to the input side of NAND gate 610. theory
The output signal 61010 with physical value 1 is sent to the remote ISL.
The master clear issued on the local bus to be
function. Signal 61010 is sent to the 14th B for sending on the bus.
given for the driver/receiver 242 in the figure.
Ru. In Figure 14Y, the retry clear D-flow
When the button 601 is set, the RRQ of FIG.
Reset full flop 584. 14th Y
The flop 601 in the figure is due to a timeout error.
is set to Signal 17208 is inverter 173
given to. Output signal 17310 is the rising edge of signal 27204.
CD term of flop 601 set at up point
Given to Naru. In Figure 14P, signal 87407 is an inverter.
data 557. The signal 87407 with logical value is
The remote strobe was received and the remote
indicates that the cycle should occur. output signal
55712 is given to the input side of NAND gate 285
Ru. Signal 21510 is the other input of NAND gate 285
When the logic value is 1, this is the bus cycle.
to indicate that it is not a file. The output signal 28503 is
It is applied to the input side of OR gate 296. signal
29803 is given to another input side of OR gate 296.
When the value is logical zero, it indicates that the comparison cycle is complete.
indicate. The logic zero output signal 29608 is a flop
297. Signals 35712 and 27308 are
It is applied to the input side of NAND gate 300. ratio
At the 135 nanosecond point in the comparison equalization cycle, the output signal
No. 30011 is given to the input side of OR gate 298.
is forced to a logical zero value. Signal 83006, i.e.
The ISL master clear signal is at OR gate 298.
given to the other input side. Logical zero output signal
29803 marks the end of the comparison cycle. In Figure 14G, MRQCYR signal 86513
and ISLOCK signal 44311 are inputs of AND gate 642
given to the side. Output signal 64206 is OR gate 4
52 input side. Signal 37806 is an OR game.
is applied to the other input side of port 452. output signal
45206 is given to the input side of register 515.
Output signal 51507 is the second
half bus cycle signal 10402. write
During reset and reset lock commands, signal 51507
This memory resets the test bits.
Show that. ISL test mode capabilities and test mode capabilities
Cycling will be discussed in the main text. two te
In case of storage mode, i.e. memory loop back and
There is an input/output loop back. memory loop x
ISL memory to cycle the ISL.
RAM, memory conversion RAM, and memory storage bits
Use RAM configuration. ISL standard cycline
loaded on local and remote ISL partners.
It will basically be controlled by the configuration. this
The ISL is configured to respond to addresses on the bus.
It will be done. The remote ISL receives address information from the local ISL.
and return this to the local ISL. Therefore, the memory rule
In the case of a loop back, the memory loop back command
The memory cycle associated with is the ISL information as described above.
Existed in transfer mode. As mentioned above, if the ISL
Even in configuration mode, if set, the memory
The cycle is induced in ISL. Receiving storage requests
At the same time, the local ISL is generated to the remote ISL.
resulting in an MRQCYR cycle
Generates an MRQCYL cycle. Remote ISL communication
configured to accept addresses sent to the bus.
This also applies if received from an external device.
If it is, generate an MRQCYL cycle. child
This again causes the MRQCYL cycle at the local ISL.
generate. Specifically, this local bus cycle
Cycle from local ISL to remote ISL and back to local ISL
generate. Either a write or read command
Can be generated. If a write command is generated, the
the system address addressed by the local ISL.
will be written to the memory location of the program. original ad
response is valid for local ISL. child
address is then transferred to the telecommunications bus by the local ISL.
The above is forwarded to an address that is not valid.
Ru. The remote ISL operates on this address and
This is again an address available on the local bus.
and convert again. If the MRQ cycle involved is
If the request is for data, local memory is
data to the local ISL. this response
In the local ISL confirmed as mentioned above,
Generates an MRSCYL cycle and then on the communication bus
MYSCYR to remote ISL sending ISL address to
generate. The remote ISL receives the ISL address
Generates an MRSCYL cycle, which is localized to the ISL.
Generate an MRSCYR cycle in
Send the data again to the CP that originally requested it.
This data is requested from the system's memory and
Sent to local ISL and then remote from local ISL
By being sent to the ISL and returned to the local ISL,
Generate 8 cycles and include all standard data and
and address route. This allows the memory rule to
Complete the back case. For I/O loop back cases, this is a retry.
Both test mode bits
memory routine except that the point must be set.
It works the same way as the back case. Local ISL
The test mode bit is set in
In remote ISL, a remote test model is required.
The code bit must be set. memory le
Unlike the backup case, remote testing
The code bit does not need to be set, but other
Avoiding communications entering the ISL from the telecommunications bus
You can set it like this. Remote testing mode
The code bit handles all responses except those of the ISL itself.
Prevent answers from being answered. standard input/output fingers
In the command, the input/output loop back mode is activated.
At some point, the channel address and function code
is used to pass requests to the local and remote ISLs.
After reverting to the local ISL, the memory location on the local ISL bus is
Specify the dress. Memory location address is I/O read
used for either write or write operations.
Ru. For reads, retry path through remote ISL
is used to pass the requested data to the local ISL.
Let's try again like in the memory loop back test.
and returned to the local ISL. However, the retry request size
Use kuru. The first cycle is a standard I/O finger
Local RRQCYL cycles treated as commands.
Ru. This request generates an RRQCYR cycle.
Sent to remote ISL. As a result, remote
Bits that do not exist on the network but are remote ISL channels
for the channel address configured in the target RAM.
resulting in a communication bus cycle. Bus waiting response
and RRQCYL cycles generated by remote ISL
be done. The remote standby response localizes the remote ISL response again.
Generate for ISL. Local ISL is the same as above.
An attempt is made to issue the same command again, that is, a standard input/output command.
Ru. RRQCYL cycles generated by remote ISL
causes an RRQCYL cycle in the local ISL.
Ru. Once again, the RRQCYR support on the local ISL bus
Ikuru orders from channel command to memory verification command.
change. The memory verification signal is forced to a logical 1.
As a result, the data associated with this command is actually written.
If it is a command, it will be sent to the system's memory;
If the request is a read request, the system memory is
Respond to data. If this is a write command,
Whether this received data is the same as the one sent
Generating a comparison instruction in the CP to check whether
System records that can be read by CP
I should have written it to a memory location. This directive is a system
Since it is confirmed by the memory of
An acknowledgment is sent back to the remote ISL via an interval response signal.
be done. Repeated retry request support from local ISL
When an cycle is issued to a remote ISL, this command
O local CP that requested read or write cycle
receive an acknowledgment sent back to local cis
The acknowledgment issued from the system memory to the local ISL.
A fixed response is sent to the remote ISL and returned to the local ISL. Bureau
Data originating from the local ISL is sent to the local ISL via the remote ISL.
I went back to ISL. This effectively uses a retry path.
channel address and machine for use and storage.
memory request cycle, except that it uses function codes.
It acts as a word. this day
The data path uses all channel data paths.
In the input/output loop back case, the data
The 10 MRS bits are logical zero and follow
address for I/O read loop back.
Bit 18 is on the response cycle from memory.
Then, the logical value is zero. This response is a memory response.
is reflected in the retry response location data file.
Ru. Therefore, the response from system memory is
loaded into the trial location and generates an RRSCYL cycle.
to be accomplished. This RRSCYL cycle is the second half cycle.
The remote ISL is acknowledged because the cycle is
generates an RRSCYR cycle in this ISL
but also in the same remote ISL as in the memory response.
Generate RRSCYL. This is confirmed again,
RRSCYL generates RRSCYR again at remote ISL.
to be accomplished. This RRSCYR cycle requires data.
sends the data to the requested CPU and closes the input/output loop buffer.
Finish the tsuku command. Specific test mode control in Figure 14G
A logic zero signal 53906 to indicate a gate that performs
is applied to the input side of AND gate 443. child
This inhibits lock signal 44311, which
Forbid functionality. As mentioned above, this signal is a memory finger.
Controls a certain function when issuing a command. Signal 53907 is applied to the input side of AND gate 627.
It will be done. Output signal 62708 is input to OR gate 625.
given to the power side. Output signal 62508 is register 5
23 is applied to the input side. Memory verification output signal
52305 is put on the bus, which causes this
indicates a storage cycle. gate 6
It has 27 input signals 53914. In local ISL,
This signal is a logic 1 and at the remote ISL
becomes a logical zero, thus memory verification on the remote ISL
block. Therefore, it is necessary to change the input/output command to memory verification.
I can do it. RRQCYR signal 90201 is signal 90201
is a logical 1 during a retry remote cycle operation.
Enables memory verification. In FIG. 14R, the input to gate 622 is
TSTRMT on the force has a logical value of zero at the local ISL.
and is logical 1 at the remote ISL. Game
The other input to port 622 is signal 51707, which
This means that the remote ISL does not generate communication bus cycles.
The logical value becomes 1. Remote ISL retries from external source
When a row path request is received, the output signal of gate 622
has a logical value of zero. This is the input side of gate 546
is given to the output signal 54608, which makes the output signal 54608 a logical zero.
By forcing a remote ISL to
Forbidden to respond to. In FIG. 14I, the logic zero test
Janel signal 62203 is input to AND gate 626
Given. The logic zero output signal 62606 is an AND gate.
output of signal 54808;
Detection of memory-incorrect bits is prohibited. this is
External source initiates ISL storage request cycle
prohibited. In Figure 14, the input/output loop back
While in mode, the logic 1 RRQCYR signal 90201
Provided to the input side of the NAND gate 623, the remote
Boolean value as a result of remote response detected from ISL
The remote response signal 56802 which is 1 is the NAND gate 62
3 is applied to another input side. Test mode signal
No. 53907 is applied to the other input side of the NAND gate 623.
available. The logic zero output signal 62308 is a flop
Set 297. When the ISL becomes idle,
Signal 29908 is forced to a logic 1, which causes the clock to
At the rising edge of lock signal 36008, flop 31
Condition the setting of 8. This is the comparison site
This is the remote ISL received by the local ISL.
The interval response is sent back to the local bus. In Figure 14K, the logic zero signal 53914 is
It is applied to the input side of AND gate 415. logic
Output signal 44512 with value zero is an ISL on either bus.
prohibited from responding to commands. Functional block in Figure 8 Detailed logic in Figure 14
For convenience, Table 13 lists the
Using the verification number and logic sheet number, the machine shown in Figure 8 is
List the function blocks. The logical sheet number in table 13 is
Used in conjunction with Table 12, the functional blocks in Figure 8
Determine that in Figure 14, which is shown in detailed logical form.
can be determined.

[Table] Bus

Table 14 shows each type of logic component shown in FIG. 14 by common name and model or order number. Elements without an asterisk on the shoulder are manufactured by Texas Instruments, Dallas, Texas, USA. The remaining logic component vendors are listed in the leg of Table 14. Delay line DLY125T, 150%, 200T and
The 6040 was specifically designated by Honeywell for configuration into ISL equipment and is fully disclosed in the following publications. That is, 1 Document No.11040109, Rev.A 2 Specification No.60067122, Rev.A 3 〃 〃04550072, Rev.C 4 〃 〃04550075, Rev.C 5 〃 〃04550079, Rev.B 6 〃 〃04 550081, Rev.B

[Table]

【table】

【table】 [Brief explanation of drawings]

1-3 are functional block diagrams of the architecture of a first data processing system embodying the present invention, and FIG. 4 shows a pair of ISL devices providing a communication path between a pair of communication buses. Functional Block Diagram, FIG. 5 is a partial functional block diagram and flow chart illustrating another logical path through a pair of ISL devices to provide a communication path between a pair of communication buses, and FIG. Timing diagram showing the effect, No. 7
Figure 8 is a functional block diagram of the architecture of another data processing system that implements the present invention, Figure 8 is a detailed functional block diagram of an ISL device that implements the present invention, and Figure 9 shows information between the ISL equipment and the communication bus. Figure 10 is an overall functional block diagram of paired ISL devices interfacing by paired interface buses; Figure 11 is a graph showing the paired ISL
A graph showing the flow of information between devices, Figure 12 is
13 is a logical state diagram illustrating the operation of the ISL device; FIG. 13 is a partial functional block diagram with partial graphs illustrating the flow of information from the local communications bus through the paired ISL device to the remote communications bus; and FIGS. 14A to 14Z.
14A to 14AC are detailed logic diagrams showing the ISL device shown in FIG. 8. 10~11, 30~31, 34, 36, 42~
44,50-51,61,64,73,74,7
6, 78, 81, 84, 86... Intersystem link (ISL) device, 14 to 16, 20, 80, 83...
CPU, 18-19, 89... Peripheral control unit (PCU), 21, 32-33, 35, 40, 52
~53,60,63,75,77,79,87,
91, 96, 105, 107, 116, 117,
120, 122, 130... contact bus, 55, 5
8,92,101,103,108,121,1
26, 127, 132, 134-136...Register, 90, 98, 115, 123, 139, 14
1... Transceiver, 93, 99... Comparator,
94...Master clear generator, 100,
111, 112, 129, 137-138... multiplexer, 106... decoder, 113, 12
5, 131, 142...RAM, 115...ISL interface output driver, 118...addition counter, 133...timer/status logic unit, 139...
Driver, 140...Hex rotary switch, 1
46...Cycle generator, 150...Online state, 151...Stopped state, 152...Cleared state, 153-154...Logic control loop.

Claims (1)

[Scope of Claims] 1. A device connected for communication between a pair of communication buses that provides a common information path for a plurality of electrically connected data processing devices, the device comprising:
consisting of a pair of inter-bus communication link devices interconnected for exchanging information carried by each of said buses, each link device being connected to one of said buses;
the transfer data provided on the connected one of the pair of communication buses in response to a control signal provided on the connected one of the pair of communication buses; an acquisition device for storing in the storage device, in response to the control signal, the transfer data stored in the storage device is to be transferred to a remote one of the pair of communication buses; a decoding device for generating an enabling signal indicating the remote bus; a converting device for converting at least a portion of the transferred data to form output data having a data format compatible with the data convention of the remote bus; and A link device connected to a remote bus is provided with a transfer control device activated in response to the enabling signal in order to transfer the output data together with the transfer data from the storage device. Intersystem communication link. 2. A device connected for communication between a pair of communication buses that provides a common information path for a plurality of electrically connected data processing devices,
consisting of a pair of inter-bus communication link devices interconnected for exchanging information carried by each of said buses, each link device being connected to one of said buses;
(a) each type of bus communication is stored in a separate one of a plurality of dedicated file locations, thereby regulating multiple bus communications of different types in parallel; (b) an asynchronous information acquisition device for capturing binary information occurring on an adjacent one of said local buses at bus speed; (b) binary information at said bus speed to be further processed by said inter-bus link; (c) an information decoding device in electrical communication with said acquisition device for identifying a local address information to a remote address information substantially at said bus speed; (d) an information conversion device in electrical communication with the decoding device and the conversion device for selectively reconfiguring the inter-bus links; ,
and a logic controller responsive to the acquisition device for controlling bidirectional transfer of information from the inter-bus link. 3. In the device according to claim 2,
the acquisition device comprising: (a) a data register responsive to control information on the one bus and the logical control device for storing data in a selected one of the plurality of dedicated file locations; a file device; (b) an address register responsive to control information on said bus and said logical controller for storing address data in selected ones of said plurality of dedicated file locations; - an intersystem communication link comprising: a file device; 4. In the device according to claim 2,
said decoding device: (a) from said one bus at a bus speed;
(b) an intersystem communication link identifier responsive to address information on said one bus to indicate a first half-bus cycle request and a second half-bus cycle response; information received from said one bus in a current bus cycle, and a response received from a remote one of said buses is provided to said one bus. (c) a bus comparator responsive to the acquisition device and the logic controller for displaying to the logic controller that the information obtained is transmitted via the intersystem link at substantially the bus speed; (d) a channel address decoder responsive to address information for displaying information to be transferred to the storage device; and (d) a channel address decoder responsive to address information to be transferred to the storage device via the intersystem link at substantially bus speed. a storage address decoding device responsive to the address information to display the information to be addressed. 5. In the device according to claim 2,
The information conversion device comprises: (a) storage address translation for selectively converting local storage addresses to remote storage addresses to directly address a remote storage device or provide storage addresses to a remote non-storage device; (b) remotely transmitting local CPU address information to address multiple remote central processing units (CPUs);
Selectively converts CPU address information to local
(c) a destination CPU address translation device for selectively changing remote address information for identification by the CPU; and (c) converting local CPU address information to a remote CPU address for addressing a plurality of local and remote CPUs. An intersystem communication link comprising: a signal source CPU address translation device selectively converting into information; 6. In the device according to claim 2,
The logic controller includes: (a) a mode controller responsive to the acquisition device to bring the intersystem link online and into a clear or stopped logic state; and (b) for controlling bidirectional information transmission. a cycle generator responsive to the acquisition device and the mode control device selectively generating intersystem link timing signals synchronized to the bus speed; (c) detecting and bypassing information transmission deadlocks;
and (d) a timing and state logic unit responsive to said acquisition device and said cycle generator for indicating the occurrence thereof; and (d) for indicating on said one bus the occurrence of an external interrupt in said intersystem link. (e) an interrupt device responsive to the timing and state logic device and in electrical communication with the acquisition device; and a function code decoding device responsive to the acquisition device and the cycle generation device for providing a state logic device and the interrupt device; and (f) for selectively reconfiguring the intersystem link. a RAM counter and control unit responsive to the acquisition unit and the function code decoding unit. 7. Each of the plurality of communication buses provides a common communication path for a plurality of data processing devices, including storage devices, peripheral control devices, intersystem link (ISL) devices, and central processing units (CPUs) that interface therewith. Each of the buses electrically communicates with one ISL device, and the ISL devices further communicate electrically in pairs, thereby allowing data processing devices on different communication buses to communicate without interfering with bus transfer rates. In a logical system for converting the address of a data processing device in a data processing system having multiple communication buses for intersystem communication, (a) the type of operation of the ISL device required by applying one storage bit signal; and provide a storage address code translated to any address storage device on one of said remote buses, or a storage address translated to a non-storage data processing device on said one remote bus. (b) a storage address translation device responsive to a binary address code received by a local device of said ISL device from one local bus of said bus to provide a code; I received it from the bus 2
(c) a register device for storing decimal code information and in electrical communication with said one local bus for completing information transfer on said one local bus within one bus cycle time; translated to address or give an address code to a remote CPU on the bus.
(d) a CPU destination address translation device responsive to said register device for providing a CPU address code; and (d) a CPU address for identifying a remote CPU on said one remote bus to a data processing device on said one local bus. a CPU source address translation device in electrical communication with said ISL device on said one remote bus to convert codes; a channel hit bit in electrical communication with said one local bus for providing a channel hit bit signal for identifying the address of a non-storage data processing device on said one remote bus to which decimal encoded information is to be transferred; a storage device; (f) responsive to binary encoded information received from the one remote bus by the one local bus and the one remote ISL device; Translation control logic responsive to the stored mid bit signal and the channel hit bit signal for controlling the operation of the address translation device, the source address translation device and the channel hit bit storage device. logical system. 8. Each dedicated location in the file register of a local intersystem link (ISL) device represents one ISL transaction in response to a request issued by one data processing device on one local communication bus. adjusting the prioritization of ISL transactions in response to requests received by a remote ISL device from the local bus and a telecommunications bus at its bus speed; coordinates the transfer of information between a plurality of communication buses within the processing system, each bus including storage devices, peripheral control devices, ISL devices, and a central processing unit (CPU) electrically interfaced therewith; The dedicated bus provides a common information path for a plurality of data processing devices, such that each of the buses is in electrical communication with one ISL device, and the ISL devices are in further electrical communication in pairs. In a logic system for identifying a location, the local bus is configured to: (a) control operation of the local ISL device by identifying local transactions of the plurality of ISL transactions during one bus cycle; and said remote
(b) a logic controller responsive to binary encoded information received from an ISL device; a first programmable storage device storing a first binary bit signal indicating a storage device on said remote bus to indicate the occurrence of said logic controller; a second programmable storage device at a cell location storing a second binary bit signal indicative of a non-storage data processing device on the remote bus to which the local ISL device is to indicate the occurrence of a retry request; (d) one of the dedicated locations in electrical communication with the local bus, responsive to the logic controller, and selected by the logic controller in response to the first binary bit signal; for one retry request location or one of the dedicated locations selected by the logic controller in response to the second binary bit signal, the storage reference signal, and the bus lock signal. the logical control for either the storage request location or the retry request location, or in response to a local second half bus cycle (BSSHBC) signal generated by the remote ISL device during a remote storage request cycle; Memory response code sensed by the device and the
binary code information received from the local bus for a retry response location or a store response location of one of the dedicated locations selected by the local controller in response to a partner of a BSSHBC signal; having a plurality of locations, each dedicated to one of said one local transaction of said plurality of ISL transactions, for storing said plurality of ISL transactions;
a register device thereby signaling to the logic controller the busy status of one of the dedicated locations. 9 regulating the exchange of information between the communication buses, while the flow of information continues on each communication bus at the bus speed;
Other requests for information continue to be handled by intersystem links (ISLs) that electrically interface with the communication bus within the data processing system and connect storage devices, peripheral controllers, ISL devices, and the like. each of a plurality of communication buses provides a common information path for a plurality of data processing devices including an interfacing central processing unit, each of said plurality of buses electrically communicating with one ISL device; In a logical communication system that electrically communicates in pairs, the apparatus further comprises: (a) electrically communicating with a local communication bus for storing binary information received from said local bus at bus speed; (b) full and active register devices in electrical communication with said local bus and indicating the busy and active states of said register device, respectively; loading the register device with the binary encoded information containing bit signals to the local bus for regulating the flow of further local bus information;
(c) a write selection logic controller within a local ISL device responsive to a BSDCNN signal from said local bus to issue a WAIT signal; and (c) non-storage data on a telecommunications bus to which said binary encoded information is to be transferred. remote to processing equipment
Identify each ISL device and request
(d ) the activity bits, the channel hit bits and the (e) initiating a remote RRQ cycle at the remote ISL device to receive the binary encoded information from the local ISL device; the local ISL device responsive to a binary encoded control signal from the local cycle generator for signaling completion of the local transfer cycle to the local ISL device and thereby regulating further local cycles at the local ISL device; (f) a remote cycle generator at a remote device; (g) a remote ISL device in electrical communication with the remote bus for transferring ACK, NAK, and WAIT signals from the remote bus to the local ISL device; a response logic controller; (h) upon occurrence of equality between the binary encoded information stored in the register device and the binary encoded information on the local bus;
To give ACK, NAK, WAIT signals, the above
a logical comparator in said local ISL device responsive to ACK, NAK, WAIT signals and the occurrence of an idle condition in said local ISL device, thereby identifying a previously issued command from a data processing device on said local bus; A logical communication system characterized by providing. 10 Control access of a plurality of central processing units (CPUs) on a local communication bus to a telecommunications bus to control the access of a plurality of central processing units (CPUs) on a local communication bus to In a data processing system with multiple communication buses, each providing a common information path for a data processing device, a bus or Can occur when cycle requests are issued by multiple CPUs on the local bus
In a logic system which avoids CPU deadlock and in which each of said buses electrically communicates with one ISL device, and the ISL devices further communicate electrically in pairs: (a) a binary code received from said local bus; (b) a register device in a local ISL device in electrical communication with said local bus for storing information at bus speed; (b) a register device in said local ISL device in electrical communication with said local bus; , an ACK received by a remote ISL device from said remote bus to indicate occurrences of equality and non-equivalence between binary encoded information stored in said register device and binary encoded information on said local bus; (c) in said local ISL device, storing a NAK retry bit signal provided by said local or said remote bus in an ISL configuration mode; (d) a mode controller in electrical communication with the register device and the remote ISL device to indicate the presence of a plurality of CPUs on the local bus; said non-equivalent signal for issuing a NAK signal to that of said plurality of CPUs having a higher priority access, thereby giving said lowest priority one CPU access to said remote bus; and said NAK
and a NAK logic controller responsive to a retry bit signal. 11 a remote intersystem link (ISL) device in electrical communication with a remote communications bus, a local ISL device in electrical communication with the local communications bus, and the local ISL device in electrical communication with the remote ISL device; and said local and remote ISL devices are local and remote, respectively.
In a data processing system having an ISL address generator, a local and remote memory bit generator, a local and remote channel bit generator, and a local and remote register device.
In a logic control system for testing ISL retry request (RRQ) logical data flow paths in an ISL device and a remote ISL device, the system comprises: (a) initiating a local retry request (RRQ) cycle and a local transfer cycle in said local ISL device; the binary encoded information received from the local bus to transfer the binary encoded information to the remote ISL device.
local control logic at said local ISL device responsive to decimal encoded information; (b) inhibiting the detection of a memory hit bit signal at said remote ISL device; detecting a generated channel hit bit signal, thereby causing the remote bus to respond to a test mode bit of a power control command received from the local bus to complete the information transfer within a single bus cycle period; remote cycle selection logic at the remote ISL device; (c) responsive to the local RRQ cycle at the local ISL device to initiate a remote RRQ cycle at the remote ISL device;
a remote logic controller at said remote ISL device responsive to the detection of said channel hit bit signal to initiate a local RRQ cycle at said device to transfer said binary encoded information to said local ISL device; d) electrically connecting said binary encoded information to said local bus under the control of said local logic controller by converting address bits of said binary encoded information into storage address commands applied to said local bus; the test mode bit and remote RRQ cycle at the local ISL device initiated by the local control logic in response to the local RRQ cycle at the remote ISL device to regulate writes to storage during communication; channel address translation logic of the local ISL device responsive to the local ISL device. 12 An intersystem link (ISL) device is in electrical communication with a remote communications bus, a local ISL is in electrical communication with a local communications bus, and the local ISL device is in electrical communication with the remote communications bus.
in electrical communication with an ISL device, and said local and remote ISL devices each have a local and remote ISL address generator, a local and remote memory bit generator, a local and remote channel hit bit generator, and a local and remote ISL address generator; and a remote register device, in a logic control system for testing logical data flow paths of ISL retry requests (RRQ) and retry responses (RRS) in local ISL devices and remote ISL devices, (a) initiating a local retry request (RRQ) cycle and a transfer cycle at the local ISL device to transfer first local binary encoded information to the remote ISL device; (b) local control logic at said local ISL device responsive to first local binary encoded information and a local channel hit bit signal generated by said local channel hit bit generator; (b) said remote ISL device; prohibiting the detection of a memory hit bit signal at the remote ISL device, and detecting a remote ISL address signal and a remote channel hit bit signal generated by the remote ISL address generation device and the remote channel hit bit signal, respectively, at the remote ISL device; In order to
(c) remote cycle selection logic at the remote ISL device responsive to a bit; (c) initiating a remote RRQ cycle at the remote ISL device to transfer the remote ISL address signal to the remote bus; said remote upon detection of any of the bit signals.
initiating a local RRQ cycle at an ISL device to store the remote ISL address information received from the remote bus at the remote register device and forward remote binary encoded information received from the remote bus to the local ISL device; (d) remote control logic at said remote ISL device responsive to selection logic of said local RRQ cycle and said remote cycle at said local ISL device; issue a storage reference signal to the local bus during a remote RRQ cycle initiated at the local ISL device by a local control logic unit to provide a storage reference signal to the local storage device in electrical communication with the local bus; (e) a storage reference signal generating device in said local ISL device responsive to said test mode bit for transferring encoded information; said test mode bit and said:
(f) a channel address translation device at the local ISL device responsive to the remote RRQ cycle at the local ISL device; the local ISL responsive to the remote RRQ cycle at the local ISL device to convert to zero;
a storage control word inhibit device in the device; (g) in electrical communication with the local bus in the local ISL device for signaling the local control logic to initiate a local RRS cycle of the local ISL device; Responsive to the MRS control bit, which causes bus second half bus cycle (BSSHBC) requests received from the local bus and retry response (RRS) logic paths from the local storage device to the local ISL device. (h) local write selection logic for routing second locally encoded information received from the remote bus; and (h) identified by the remote control logic for provision to the remote bus and upon receipt from the remote bus. selecting the remote ISL address information stored in the remote register device to
This causes the remote control logic to initiate a local RRS cycle in the remote ISL device and the local control logic to
the second local binary encoded information and the local RRS at the local ISL device to initiate a remote RRS cycle at the device and transfer the second binary encoded information to the local bus;
a remote control at said remote ISL device generated by said remote control logic in response to a cycle.
and remote address selection logic at the remote ISL device responsive to an RRS cycle. 13. A remote intersystem link (ISL) device is in electrical communication with a remote communications bus, a local ISL device is in electrical communication with the local communications bus, and the local ISL device is in electrical communication with the remote ISL device. , and the local and remote ISL devices each have a local and remote ISL address generation device, a local and remote storage medium bit generation device, a local and remote channel hit bit generation device, and a local and remote register device. In a logic control system for testing ISL storage request (MRQ) logical data flow paths at local and remote ISL devices in a processing system, the system comprises: (a) testing local storage request (MRQ) cycles and local transfer cycles at said local ISL devices; a first local control logic unit in the local ISL device responsive to initiating binary encoded information and the binary encoded information received from the local bus for transfer to the remote ISL device; ) disabling the detection of a channel hit bit signal at the remote ISL device and detecting a memory hit bit signal generated by the remote memory hit bit device at the remote ISL device, thereby causing the remote bus to (c) remote cycle selection logic at the remote ISL device responsive to a test mode bit of a power control command received from the local bus to complete an information transfer within a bus cycle; in response to the local MRQ cycle at the local ISL device to initiate a remote MRQ cycle at the device;
a remote logic controller at the remote ISL device responsive to a detected bit of the memory in-bit signal to initiate a local MRQ cycle at the device to transfer the binary encoded information to the local ISL device; d) transmitting the test mode bits to the local bus at the remote ISL device for the transfer of the binary encoded information provided to the local bus;
and a remote MRQ cycle of the local ISL device initiated by the first local control logic in response to an MRQ cycle, thereby performing the binary encoding under control of the first local logic controller. a second local control logic device in the local ISL device that regulates writing of information to a storage device in electrical communication with the local bus. 14. A remote intersystem link (ISL) device is in electrical communication with a remote communications bus, a local ISL device is in electrical communication with the local communications bus, and the local ISL device is in electrical communication with the remote ISL device. The local and remote ISL devices are local and remote ISL devices, respectively.
An ISL storage request (in a local ISL device and a remote ISL device) in a data processing system having an address generator, a local and remote storage bit generator, a local and remote channel bit generator, and a local and remote register device. MRQ) and memory response (MRS) logical data
A logic control system for testing a flow path comprising: (a) initiating a local storage request (MRQ) cycle and a transfer cycle at the local ISL device to transfer the first local binary encoded information to the remote ISL device;
the local ISL device responsive to first locally encoded information received from the local bus and a locally stored mid bit signal generated by the local stored mid bit generator for transmission to the local ISL device; (b) inhibiting the detection of a channel hit bit signal at the remote ISL device; remote cycle selection logic in said remote ISL device responsive to a test mode bit of a power control command received from said local bus for detecting a remote ISL address signal and a remote storage medium bit signal respectively generated; (c) initiating a remote MRQ cycle at the remote ISL device, transmitting the remote ISL address signal to the remote bus, and initiating a local MRQ cycle at the remote ISL device upon detection of the remote storage medium bit signal; and the remote register received from the remote bus.
storing ISL address information and transmitting remote binary encoded information received from the remote bus to the local ISL;
(d) remote control logic at the remote ISL device responsive to the local MRQ cycle at the local ISL device and the remote cycle selection logic for forwarding to the device; (d) the remote MRQ cycle at the local ISL device; transferring the remote binary encoded information to a local storage device in electrical communication with the local bus during a remote MRQ cycle initiated at the local ISL device by the first local control logic in response to a second local control logic unit at the local ISL device responsive to the MRQ cycle at the remote ISL device and thereby regulating reading of second locally encoded information from the local storage device; (e) said local ISL device responsive to said remote MRQ cycle at said local ISL device to convert a storage response (MRQ) control bit of a storage control word generated by said local ISL device to a logic one;
a storage control word generating device in an ISL device; (f) in said local ISL device, in electrical communication with said local bus and signaling said local control logic to initiate a local MRS cycle in said local ISL device; is responsive to the MRS control bit to cause the second half bus cycle (BSSHBC) of the bus received from the local bus to be
(g) local write selection logic for routing requests and second locally encoded information received from the local storage device via a store response (MRS) logic path at the local ISL device; selecting the remote ISL address information stored in the remote register device for presentation to the bus and for identification by the remote control logic upon receipt from the remote bus;
responsive to the local MRS cycle at the local ISL device to the second local binary encoded information and a remote MRS cycle at the remote ISL device generated by the remote control logic; causing the remote logic to initiate a local MRS cycle at the remote ISL device; and causing the local control logic to initiate a remote MRS cycle at the local ISL device to transmit the second binary signal to the local bus. remote address selection logic in the remote ISL device for transferring encoded information. 15 In a data processing system in which each of a plurality of communication buses electrically communicates with one intersystem link (ISL) device, and the ISL devices electrically communicate in pairs, storage devices, peripheral control devices, and central processing an ISL device selectively configured to coordinate information transfer between any data processing device and the one local communication bus, including the device and the ISL device in electrical communication with any of the plurality of communication buses; In an architecture of intersystem link (ISL) devices that can be reconfigured to output control commands and communication bus requests from a CPU in electrical communication with one of said plurality of communication buses to convert said addressed ISL device between a line logic state and a stop logic state; (b) any one of said plurality of communication buses in electrical communication with said one of said plurality of communication buses for regulating information transfer between said plurality of communication buses; a programmable storage device having storage cell locations for storing binary encoded information received from the CPU; and (c) selecting locations of the storage cells of the programmable storage device according to configuration data received from the CPU. configuration control logic responsive to said cycle control logic to change binary encoded information stored in said plurality of communication buses, thereby dynamically reallocating data processing system resources among said plurality of communication buses; An inter-system link device comprising: 16. A data processing system having a plurality of communication buses each providing a common information path for a plurality of data processing devices including storage devices, peripheral control devices, central processing units (CPUs), and intersystem link (ISL) devices. detecting, isolating, and eliminating deadlock in information transfer between communication buses of the plurality of communication buses, each of the plurality of communication buses being in electrical communication with one ISL device, and the ISL devices being electrically connected in pairs; A timer logic control system for an ISL device comprising: (a) a local ISL device in one local ISL device in electrical communication with one local bus of the plurality of communication buses for controlling the flow of information through the local ISL device; (b) the first BSDCNN from the local bus for generating a NAK response if a response to the first BSDCNN signal is not received from the local bus within a first predetermined period of time; a bus timer responsive to a signal to thereby provide an alternative response in lieu of an expected response from one local CPU in electrical communication with the local bus to release the local bus for further information transfer; a logical device; (c) one remote in electrical communication with said remote bus;
generated by the local ISL device in response to a bus cycle request received by the ISL device from a remote bus of one of the plurality of communication buses and connected to the local bus for generating a NAK response to the local bus. a request issued to a local data processing device in electrical communication with said remote bus if an expected response from said local data processing device is not received within a second predetermined period of time; and a timer control signal to the remote ISL device signaling expiration of the second time period, thereby completing a local bus cycle and causing any CPU on the local bus to
Prohibit detecting the expiration of the period of
ISLMYDCNN timer logic; (d) communicating with said local bus for generating a status bit to said local logic controller if a remote MRS cycle is not initiated at said local ISL device within a third predetermined period of time; During a memory read request operation initiated by the local logic controller in response to a bus cycle request from a requesting data processing device in electrical communication with the local
responsive to an MRQ cycle, thereby causing the local logical controller to initiate a remote MRS cycle at the logical ISL device to
(e) store cycle timer logic in electrical communication with the local bus to complete a bus cycle in the device and to indicate an invalid store response to the requesting data processing device;
bus cycle from the requesting data processing device to generate a retry status bit to the local logic controller if a NAK response is not received from the remote ISL device within a fourth predetermined period of time. responsive to a local RRQ cycle at the local ISL device initiated by the local logic controller in response to a request, thereby causing an ACK, NAK, or
(f) retry timer logic in electrical communication with the local bus to inhibit generation of a WAIT response and release the local bus for further information transfer; During a read operation in response to a local RRQ cycle at the local ISL device generated by the local logic controller in response to a bus cycle request, an expected response is returned to the remote bus within a fifth predetermined period of time. generates an I/O status bit signal to the local logic controller to
initiating a remote RRS cycle at the ISL device;
This causes the local logic controller to initiate a remote RRS cycle at the local ISL device, complete a bus cycle at the local ISL device, and indicate an invalid response to the requesting data processing device. 1. A timer logic control system in an intersystem link (ISL) device, comprising: an O timer logic device. 17. Each of the plurality of communication buses includes a storage device and peripherals for regulating simultaneous bidirectional transfer of binary encoded information between one local bus and one remote bus of the plurality of communication buses. In an intersystem communication control system that electrically connects a plurality of communication buses in a data processing system that provides a common information path to a plurality of data processing devices including a control device, a central processing unit, and an ISL device, (a) in electrical communication with said local bus and responsive to a BSDCNN signal on said local bus for identifying a bus cycle request received from said local bus to which one local ISL device of said ISL device is to respond; (b) local bus control logic at said local ISL for controlling the transfer of local binary encoded information received from said local bus and said remote bus to said remote ISL device; (c) local cycle control logic responsive to activity bit control signals from the remote ISL device and transmitting binary encoded information received from the remote ISL device through the local ISL device; responsive to the local cycle control logic to store the binary encoded information for transmission to an ISL device, and thereby to receive remote binary encoded information from the remote ISL device; (d) a local ISL interface and register device in electrical communication with said remote bus to release said device for simultaneous bidirectional information transfer;
the ISL responsive to a BSDCNN signal on the remote bus to identify a bus cycle response received from the remote bus to which the ISL device is to respond;
(e) remote bus control logic in one remote ISL device of the apparatus; (e) said local ISL device for controlling the transfer to said local ISL device of remote binary encoded information received from said local bus and said remote bus; said local ISL device in response to an activity bit control signal from said remote ISL device and received from said local ISL device via said remote ISL device.
remote cycle control logic for passing binary encoded information; (f) responsive to said remote cycle control logic for storing said remote binary encoded information for transmission to said local ISL device; a remote ISL that releases said remote cycle control logic to receive said local binary encoded information from said local ISL device for simultaneous bidirectional information transfer;
An inter-system communication control system comprising an interface register device.