JPS5836313B2 - Periodic signal detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention improves the 4-ratio of signal wave detection by correlating multiple periods of signal waves that arrive with periodicity.

When correlating signal waves, the number of correlations increases Accordingly, the 4 ratio of the detection signal can be improved.

However, if the number of correlations is increased too much, the frequency band of the signal waves that can pass through the correlation circuit becomes narrow, making it extremely difficult to detect the signal waves.

This invention increases the number of correlations of signal waves when the phase of the signal wave is stable when detecting a periodic signal,
On the other hand, if the phase of the signal wave is relatively unstable or the phase is changing little by little, the number of correlations may be reduced to make it easier to detect the signal wave, depending on the stability of the signal wave. Provided is a signal detection device in which the number of correlations changes.

Hereinafter, a case will be described in which the present invention is applied to an acoustic sounder that measures the depth of the ocean floor using ultrasonic pulses.

In FIG. 1, a pulse generator 1 generates and sends out a pulse wave (FIG. 2a) at every fixed frequency XH'ro.

The transmitter 2 is excited by this pulse wave a, and an ultrasonic pulse is transmitted from the transducer 3 into the water.

The reflected wave from the water is amplified and detected by the receiver 4, and then sent to the shaping circuit 5.

A shaping circuit 5 shapes the output of the receiver 4 and sends it to a multiplexer 6.

FIG. 2 b1, b2, b3, . . . show shaped waves of reception signals received by the receiver 4 for each emission period of ultrasonic pulses.

In the shaped waves b1, b2..., B1S, B2
S...... is a transmitted pulse, B1F, B2F are underwater reflectors (for example, a school of fish), B1R, B2R, B3R...
...indicates seafloor reflected waves.

The multiplexer 6 generates shaped waves b1, b2 of each period based on the pulse wave sent out from the pulse generator 1.
. . is switched and sent to each of the storage circuits 71 to 75.

The multiplexer 6 also transfers the write pulse sent out by the write pulse generator 8 to the storage circuit 7 to which shaped waves b1, b2, . . . are sent out in synchronization with the switching operation.
1, 72, . . . , and sends the data.

The write pulse generator 8 sends out n pulse waves every time the pulse generator 1 sends out an output pulse, and the period of the pulse wave is equal to the seafloor reflected pulse B within the time when the n pulse waves are sent out. , R, B2R... are set so that they return.

On the other hand, each of the memory circuits T1 to 75 is composed of n memory elements, and the n write pulses sent from the write pulse generator 8 are each guided to the corresponding number of memory elements.

Therefore, for example, the first period shaped wave b1 is sent to the memory circuit 71.
is led, oscillation pulse B1S, underwater reflection pulse B
, F, seabed reflected pulses B1R, etc. are stored in storage elements corresponding to the depths of the respective reflected pulses.

In this case, each storage element stores, for example, the presence or absence of each of the reflected pulses as a binary signal.

The stored contents of each of the memory circuits 71 to 75 are read out by a read pulse sent from the read pulse generator 9.

For example, n read pulses are generated by delaying the write pulse by a small amount of time.

Each of the read pulses is then sent to each storage element with a minute delay from the write pulse to read out the stored contents.

In this case, the read pulse is applied so as to simultaneously read out the stored contents of the memory elements of the same number in each of the memory circuits 71 to 75.

The respective storage outputs of the storage circuits 71 to 75 read out as described above are sent to the decoder 10.

The decoder 10 has first to fifth output terminals D1 to D, and outputs the stored output to the output terminal corresponding to the number of coincidences of the stored outputs, that is, the number of correlations.

For example, when only one of the storage circuits 71 to 75 outputs a storage output, it outputs the output to the first output terminal D1.

Also, if outputs are sent from two memory circuits at the same time, the second
When outputs are sent from three memory circuits at the same time, outputs are sent to the third output terminal D3. When memory outputs are simultaneously sent from four memory circuits, the output is sent to the third output terminal D3. The output is sent to the output terminal D4 of 4.

When all the memory outputs of the memory circuits 71 to 75 match and are sent out, the output is sent out to the fifth output terminal D5.

Among the outputs of the output terminals D1 to D of the decoder 10, D
The outputs of 1 to D4 are sent from the OR circuit 12 to the output terminal Po via gate circuits 111 to 114, respectively.

Further, the output of the output terminal D, is directly transmitted from the OR circuit 12 to the output terminal P.
.

sent to. And output end P.

The outputs of each period are shaped waves b1, b2, b3...
It is used as a correlation output.

Each of the gate circuits 111 to 114 is controlled according to the stability of the received signal of the receiver 4.

example? f, seafloor reflected pulses B1RPJ to B, J), when they are simultaneously sent out from all memory circuits T1 to 75,
Since the correlation between five periods is possible, the gate circuits 111 to 114 are controlled to be non-conductive, and only the correlation output of the terminal D is output from the OR circuit 12 to the output terminal P.

sent to. If the stability or phase of the signal wave changes and the number of correlations is possible for only four cycles, the gate circuit 114 becomes conductive and the output from the output terminal D4 of the decoder 10 is sent out.

If the number of correlations is only possible for three cycles, the gate circuit 113 becomes conductive and the output terminal D of the decoder 10
3 outputs are sent out.

As in the first half, the number of correlations is controlled by controlling the number of conductions of the gate circuits 111 to 114.

This operation will be explained below.

The gate circuits 111 to 114 are each controlled by the Q output of the corresponding flip-flop 131 to 134,
Each Q output is controlled to conduct when it is at a high level.

Each of the Q and Q outputs of flip-flops 131-134 is inverted to a high level by the pulse output of pulse generator 1 passing through either gate circuit 141 or 142.

That is, when the pulse wave of the pulse generator 1 (FIG. 2a) passes through the gate circuit 141, each flip-flop 1
The Q outputs of 31-134 are inverted to high level.

Moreover, when the pulse wave a passes through the gate circuit 142,
The Q output is inverted to high level.

In this case, the pulse wave that has passed through the gate circuit 141 is guided to each flip-flop circuit via gate circuits 151 to 154 provided for each of the flip-flops 131 to 134.

Further, the pulse waves passing through the gate circuit 142 are guided to the respective flip-flops 131 to 134 via the gate circuits 161 to 164, respectively.

And gate circuits 151 to 154 and 161 to 1
Each of 64 conducts depending on the count value of the reversible counting circuit 17.
Non-conduction is controlled.

In FIG. 1, the reversible counting circuit 17 is constituted by a quaternary counting circuit, and the matrix circuit 18 sends out a high level output to one of its output terminals M1 to M4 in accordance with its count value.

When the count value is 1, the matrix circuit 18 sends out a high level output to the output terminal M1, and the gate circuits 151 and 161 are made conductive by this output.

When the above count value is 2, the matrix circuit 18 outputs the output terminal M
2, and sends a high level output to gate circuit 152 and 1.
62 is made conductive.

Thereafter, in the same way, as the count value changes from 3 to 4, the I/IJ circuit 18 sequentially sends out high level outputs to the output terminals M3 and M4.

The high level output of the output terminal M3 is sent to gate circuits 153 and 163, and the high level output of the output terminal pigeon is sent to gate circuits 154 and 164.

On the other hand, the reversible counting circuit 17 adds and counts the pulse wave a that has passed through the gate circuit 141, and subtracts and counts the pulse wave a that has passed through the gate circuit 142.

Therefore, when the pulse wave a is sent out from the gate circuit 141, the count value of the reversible counting circuit 17 increases.

Then, the pulse wave a is applied to each flip-flop 131 to 1.
Since the Q side of 34 is sequentially inverted to a high level, gate circuits 111 to 114 are controlled to be non-conductive in order from gate circuit 111 as the count value increases.

Further, contrary to the above, when the pulse wave a is sent out from the gate circuit 142, the count value of the reversible counting circuit 17 sequentially decreases.

Further, since the pulse wave a inverts each Q side of the flip-flops 131 to 134 to high level in turn, the gate circuit 1
11 to 114, as the count value decreases, the gate circuit 1
The conductive state is sequentially reversed starting from 14.

Therefore, when the pulse wave a passes through the gate circuit 141, the gate circuits 111 to 114 are turned off in order from the gate circuit 111, so in this case, the output terminal P.

The number of times the signal waves are correlated increases.

Moreover, when the pulse wave a passes through the gate circuit 142,
Since the gate circuit 114 is turned on in order, the number of correlations decreases in this case.

Therefore, as is clear from the above, depending on the stability of the signal wave, the number of correlations for detecting the signal wave can be switched to an appropriate number by passing the pulse wave a through either of the gate circuits 141 and 142. becomes possible.

Gate circuits 141 and 142 are controlled by the output of signal storage circuit 21.

The signal storage circuit 21 is composed of a DT flip-flop 22 and an RS flip-flop 23.

The S terminal of the RS flip-flop 23 has an output terminal P.

A detection signal of is guided, and a pulse wave a is guided to the R terminal.

Now, as shown in FIG. 3, at any period Tn, the output terminal P.

If detection signal B (as shown in Fig. 3) is sent to
The Q output of flip-flop 23 is inverted to a high level by this detection signal B (FIG. 3C).

Then, this Q output C is the D of the DT flip-flop 22.
sent to the terminal.

In the DT flip-flop 22, when a pulse wave is applied to the trigger terminal T, the Q output follows the level of the D terminal.

Further, a pulse wave a' is guided to the T terminal.

Therefore, when the pulse wave A2 of the next period T n +1 is applied, the Q output of the DT flip-flop 22 becomes high level.

(FIG. 3d) Pulse wave A2 is also applied to the R terminal of RS flip-flop 23, resetting its Q output to a low level.

Note that, strictly speaking, this reset operation is performed with a slight time delay.

The Q output of the DT flip-flop 22 is connected to the gate circuit 14.
At the same time, the signal is sent to the gate circuit 142 via the inverting amplifier 24.

Therefore, when the Q output of the DT flip-flop 22 is at a high level, the pulse wave A2 passes through the gate circuit 141, so that the number of correlations in the next period Tn+1 increases by one, as described above.

Then, in the next period T n +1, similarly to the above,
Signal wave B or output terminal P.

, the next pulse wave A3 is also sent to gate circuit 1.
41, the number of correlations increases by one.

Thereafter, in the same way, each time a signal wave is detected, the number of correlations increases by 1.
When the count value of the reversible counting circuit 17 reaches 4, the high level output from the output end of the matrix circuit 18 is sent to the gate circuit 141 via the inverting amplifier 20.

Then, the gate circuit 141 is shut off. Therefore, after that, the count value of the reversible counting circuit 17 is maintained at the state of 4, so that the output terminal P.

Only the output of the output terminal D of the decoder 10 is sent out.

Thereafter, in T n + 2 periods, the output terminal P.

If no signal wave is detected, the Q output of the RS flip-flop 23 is reset by the pulse wave A3 and held at a low level.

Therefore, when the pulse wave A4 of the next period T n +3 is sent out, the Q output of the DT flip-flop 22 is inverted to a low level (FIG. 3d).

Therefore, as a result of the pulse wave A4 passing through the gate circuit 142, the number of correlations decreases by one.

Thereafter, in the same manner, output terminal P is connected. If no correlation output is sent out, the number of correlations decreases by one every time a pulse wave is sent out from the pulse generator 1.

When the number of correlations reaches 1, that is, when the count value of the reversible counting circuit 17 reaches 1, the high level output of the output terminal M1 of the matrix circuit 18 is transmitted to the inverting amplifier 19.
The signal is sent to the gate circuit 142 via.

Therefore, as a result of the gate circuit 142 being cut off, the number of correlations is maintained at one.

As described above, in the present invention, since the number of correlations is automatically controlled according to the stability of the signal wave, it is possible to control the number of correlations of the correlation circuit to the number most suitable for the stability of the signal wave. can.

In FIG. 1, five stages of memory circuits 71 to 75 are used, but this is not limited to five stages and can be set to any number of stages.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are waveform diagrams for explaining its operation.

Claims (1)

[Claims] 1. A first to nth storage circuit that separately stores signal waves of the first to nth periods arriving with periodicity for each period; a readout circuit that simultaneously reads out the storage contents of the storage circuit; and a first to nth output terminal, and one of the first to nth output terminals is provided depending on the number of coincidences of the storage signals read by the readout circuit. a decoder that sends outputs from the first to nth outputs of the decoder;
(n-1) first to (n-1) gate circuits that separately control passage of the outputs of the first to (n-1) gate circuits and the n-th output of the decoder; an OR circuit that sends out the first to (n-1) signals for each period of the periodic signal based on the output when the output is sent from the OR circuit;
gates are shut off sequentially starting from the first gate, and when no output is sent from the OR circuit during one cycle of the periodic signal, the first to (n-1) gates are shut off at the (n-1)th gate for each cycle. n-1) A periodic signal detection device, comprising: a control circuit that performs control such that gates are made conductive in order, and uses the output of the OR circuit as a periodic signal detection signal.