JPS5836081A - Signal composing circuit of solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain composition of picture element signals of two systems without any error, by providing switching elements which clamp signal input terminals succeeding to charge transfer parts selectively at a reference potential. CONSTITUTION:Between respective input terminals of a conventional signal coupling circuit, i.e. bases of transistors TR1 and TR2, and an earth point as a reference potential point, switching elements Q1 and Q2 of, for example, field effect transistors (FET) are connected; when the FETs Q1 and Q2 are driven selectively by a pulse to receive the output of one charge transfer part, the output of the other charge transfer part is clamped selectively at the earth potential. Therefore, a time series picture element signal of one system is composed correctly of an even and an odd picture element signal from the charge transfer parts of two systems without any error in synthesis.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal synthesis circuit of a solid-state imaging device, and more specifically to a two-system charge transfer unit in a solid-state imaging device such as used in a reading unit of a facsimile machine or an optical character reader. This invention relates to an improvement of a signal synthesis circuit that synthesizes output signals from a plurality of devices into one time series signal.

As is already well known, a solid-state imaging device used in a reading unit of a facsimile machine, etc., has photodetector elements #1 to #N, such as photodiodes, arranged in a line to form a photoelectric conversion unit, as shown in the conceptual top view of main parts in Fig. 1. 1 and transport game on both sides)T
Charge transfer units 2 and 8 such as COD are arranged adjacent to each other via G, and an amplifier A1 is connected to the output side of each charge transfer unit 2 and 8 via a DC biased output gate (OG).
and A2 are connected, and the output terminals 4.5 of the charge transfer sections 2 and 8 are provided on the output sides of these amplifiers AI and A2. The charge transfer electrodes of each charge transfer unit 2, 8 are connected to the driving bus lines 01 to 4, and the transfer gate (TQ) is connected to the bus line O.
It is connected to TG.

The charges photoelectrically converted by the light receiving elements #1, #8, '#5, . Also, the even-numbered light receiving element #2 of the photoelectric conversion unit 1. #8...
- The #N charge is transferred to the charge transfer unit 2, transferred, and outputted from the output terminal 4 as an even pixel signal. Two outputs corresponding to odd and even pixels from the charge transfer section of such a two-system cable must be combined into one system of time-series signals by an external circuit.

Therefore, a signal coupling circuit as shown in FIG. 2 is generally used. That is, an emitter follower circuit is configured by a combination of two transistors Tr1 and Tr2 with one load resistor R1 as a common load, and the base terminal 5' of the transistor Trl is connected to the output terminal 5 of the charge transfer section 8 (see FIG. 1). ) and also the base terminal 4' of transistor 'I'rg.
is connected to the output terminal 4 of the charge transfer section 2, and the combined output signal is taken out from the output terminal 6.

By the way, in recent years, in the solid-state imaging device shown in FIG. By transferring the electric charge to a plurality of charge transfer electrodes and transferring the transferred electric charge by the plurality of charge transfer electrodes,
A method of transferring a large amount of charge without increasing the charge storage capacity of each charge transfer electrode has been adopted.

FIG. 8 shows the drive voltage waveforms applied to the transport TG shown in FIG. It is a diagram. Referring to FIG. 8 and FIG. 1, as is clear from the figures, the transfer gate TG is in the open state during the period in which the potential of the bus bar 2TG is positive, and the charge of each light receiving element is transferred to the charge transfer section 8. 2 busbar 02, . 18.04, and the charges transferred to these eight transfer electrodes are sequentially transferred, and the charges from the odd-numbered light receiving elements of the photoelectric conversion unit 1 are transferred to the odd-numbered pixels. The signal is outputted from the output terminal 5, and the charge collection even numbered pixel signal from the even numbered light receiving element is outputted from the output terminal 4.

In this way, when signal charges are transferred from each light receiving element to the charge transfer section, the duty factor of the output signal is 50%. , the odd-numbered pixel signal and the even-numbered pixel signal overlap (see FIG. 8).

FIG. 4(a) shows the photodetector $1 in FIG. #8 is irradiated with the same amount of incident light, and light receiving element #2. #4゜ #6 has the light receiving element $1. $8 is less and the same amount of incident light is incident on the light receiving element #5, and the light receiving element $1. Odd-numbered pixel signal VOO from output terminal 6 and even-numbered pixel signal Vlo from output terminal 4 when a larger amount of incident light is incident than $8
shows. FIG. 4(b) shows the terminal 6 after the signal from the output terminal 6.4 has passed through the signal coupling circuit shown in FIG.
2 is a diagram showing a combined output signal waveform from FIG. Note that the voltage waveform shown by a solid line in the figure is an odd pixel signal of 6tl, and the voltage waveform shown by a dotted line is an even pixel signal. Combined output signal ■ in the signal combination circuit shown in FIG. is input and even pixel signal V
Since a signal voltage matching the lower voltage of EO is output, the light receiving elements + 1 , '# 2 + # 8 . The signals from $5 and 3 are correctly combined and output from terminal 6. However, the drawback is that the voltage #5' of light receiving element #5 is combined as a false output signal at the timing when the signal of light receiving element #4 should be output, making it impossible to obtain a correctly combined output signal. was there.

That is, when the output signals from the charge transfer units 8 and 2 overlap, if the voltage of the false signal is low at a certain timing for some reason, a synthesis error may occur.

The present invention has been made in view of the above points, and has two purposes.
It is an object of the present invention to provide a signal synthesis circuit for a solid-state imaging device that eliminates synthesis errors when combining odd-numbered pixel signals and even-numbered pixel signals from charge transfer units of a system into one time-series signal, and has several characteristics. a photoelectric conversion section in which light-receiving elements are arranged in a fin shape, and another charge transfer section that transfers charges transferred from the electrophotographic elements transferred from each odd-numbered light-receiving element of the photoelectric conversion section; A two-man power type signal coupling circuit with a common load is provided, and the output signals from each of the charge transfer sections are connected to each input terminal of the signal coupling circuit to obtain a synthesized time series signal. In a signal synthesis circuit of a solid-state imaging device, an input terminal connected to the other charge transfer section when receiving an output signal from one charge transfer section is provided between each input terminal of the signal coupling circuit and a reference potential point. A switching element is connected to selectively clamp the voltage to a reference potential.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a circuit diagram showing a signal synthesis circuit of a solid-state imaging device according to the present invention, and the same parts as in FIG. 2 are given the same reference numerals. In the figure, two transistors Trl + Tr2 (0) with a load resistor R1 as a common load constitute an Etta follower circuit, and a resistor R is connected to the base of the transistor Tri.
Odd pixel signal ■ from the charge transfer unit 8 (see FIG. 1) via 2; 0 is input, and the even number pixel signal V from the charge transfer unit 2 is input to the base of the transistor Tr2 via the resistor R2.
The point that EO is input is not much different from the conventional signal synthesis circuit. The major difference between the signal combining circuit according to the present invention and the conventional one is that, for example, a field effect transistor is connected between each input terminal of the conventional signal combining circuit, the bases of the transistors 'I'rt and Tr2, and the ground serving as a reference potential point. (FET) switching elements Q1 and Q2 are connected, and by selectively pulse-driving FETs QI and Q2, when receiving an output from one charge transfer section, the output from the other charge transfer section is selectively switched. This is where it is clamped to ground potential.

The operation of the signal synthesis circuit of the solid-state imaging device according to the present invention will be described below, taking as an example the odd-numbered pixel signal and the even-numbered pixel signal shown in FIG. 4(a). Figure 6(a) shows the fifth
Each gate terminal Oax of FETQI and Q2 shown in the figure
This is a diagram showing the stone clamp pulse waveforms applied to O and Oc2, with symbols corresponding to each other, in which NETQl and Q2 are turned on at the timing of each positive polarity pulse,
Input terminal of signal coupling circuit Transistor Tr 1
r Clamp the base voltage of Tr 2 to ground potential.

Now, the odd pixel signal VOO from the charge transfer section 8 (see FIG. 1) as shown in FIG. 6(1)) is input to the terminal 5' (see FIG. When the pixel signal VFCO is input to terminal 4' (see Figure 5), S
At each timing of the clamp pulse of cx, the base of the transistor Tr1 is clamped to the ground potential, and the base of the transistor Tr1 is clamped to the ground potential.
The base of the clamp pulse transistor Tr2 of c2 is clamped to the ground potential. As a result, as shown in FIG. 6(0), the odd-numbered and even-numbered pixel signals are correctly combined and outputted from the output terminal 6 (see FIG. 6) as a combined signal ``o''. In the conventional signal coupling circuit (Fig. 2), Fig. 4 (b)
), the false signal #5' of light receiving element #5 was output at the timing when the signal of light receiving element #4 should have been output, but in the signal synthesis circuit of the present invention,
The tie ETQl turns on and the transistor Tr
Since the base potential of i is clamped to the ground potential,
The true signals of light receiving element #4 are combined and output.

In the above explanation, an example was described in which the amount of light incident on the light receiving element #5 is larger than the amount of light incident on the other light receiving elements, but this is not limited to this case. It is also possible to prevent signal synthesis errors that occur when the output signal is large despite the same amount of incident light.

As is clear from the above description, in short, the present invention provides a photoelectric conversion unit in which a plurality of light receiving elements are arranged in a line, and one charge transfer unit that transfers charges transferred from each odd-numbered light receiving element of the photoelectric conversion unit. It has a transfer section and another charge transfer section that transfers charges transferred from each of the even-numbered light receiving elements, and further includes a two-man type signal coupling circuit with a common load, and from each of the charge transfer sections. In the signal combining circuit of a solid-state imaging device, the output signal from one of the charge transfer units is connected between each input terminal of the signal combining circuit and a reference potential point. By connecting a switching element that selectively clamps the signal input terminal connected to the other charge transfer section to a reference potential when receiving the odd and even pixel signals from the charge transfer section of the two threads, It can be correctly synthesized into one system of time-series pixel signals without causing synthesis errors, and subsequent signal processing circuits such as amplifiers, sample holds, filters, A/
One system of D converters and the like is required, which has the advantage of making the solid-state imaging system smaller and lower in price.

[Brief explanation of drawings]

FIG. 1 is a conceptual top view of the main parts for explaining the configuration of the solid-state imaging device, FIG. 2 is a circuit diagram showing an example configuration of a signal coupling circuit, and FIG. 8 is the solid-state imaging device of FIG. 1. Figures 4(a) and 4(b) show the drive voltage waveform and output voltage waveform of
) is a voltage waveform diagram for explaining the operation of a conventional signal synthesis circuit, FIG. 5 is a circuit diagram showing an example configuration of a signal synthesis circuit according to the present invention, and FIG. 6(a)
-(0) are voltage waveform diagrams for explaining the operation of the signal synthesis circuit according to the present invention. 1: photoelectric conversion section, 2, 8: charge transfer section, 4, 5: output terminal of charge transfer section, R1: load resistance, Ql, Q2 switching element, #1 to #N: light receiving element. 2

Claims (1)

[Claims] A photoelectric conversion section in which a plurality of light receiving elements are arranged in a line, one charge transfer section that transfers charges transferred from each odd numbered light receiving element of the photoelectric conversion section, and a charge transfer section that transfers charges from each even numbered light receiving element. the other charge transfer section for transferring charges, and further includes a two-man type signal coupling circuit with a common load, and output signals from each of the charge transfer sections to input terminals of the signal coupling circuit. In a signal synthesis circuit of a solid-state imaging device that is connected to obtain a synthesized time-series signal, an output signal from one charge transfer section is connected between each input terminal of the signal coupling circuit and a reference potential point. When receiving
A signal synthesis circuit for a solid-state imaging device, characterized in that a switching element is connected to selectively clamp a signal input terminal connected to the other charge transfer section to a reference potential.