JPS5887963A - Signal synthesizing circuit for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent the mistake in synthesizing odd and even signals, by supplying two systems of signals respectively to a signal processing circuit consisting of a sample-hold circuit and an A/D conversion circuit, synthesizing them at a data selector circuit, and passing through the result to a latch circuit and a D/A converter. CONSTITUTION:An odd number picture element signal VOO and an even number picture element signal VEO respectively amplified with amplifiers 15a, 15b are inputted to sample-hold circuits 16a, 16b respectively, and sample-held in clock pulses SHCK1 and SHCK2. The signals are inputted to A/D converters 17a, 17b, and A/D-converted with clock pulses ADCK1, ADCK2. They are alternately selected at a data selector 18 with a selection signal SEL, and tentatively stored with a latch control signal LAT at a latch circuit 19, and outputted as a digital coupling signal DCO. They pass through a D/A-converter 20 to obtain signals arranged with correct odd and even numbers.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal synthesis circuit for a solid-state image pickup device, and more specifically, for example, a signal synthesis circuit for a solid-state image pickup device used in a reading section of a facsimile machine or an optical character reader. This invention relates to an improvement of a signal synthesis circuit that synthesizes the output signals of 1 to 1 system of time-series signals.

(2) Technical background In recent years, remarkable technological progress in facsimiles, etc. has led to the use of solid-state imaging devices M (e.g. line sensors, etc.)
Increasingly, high performance is required.

(3) Prior Art and Problems As is already well known, solid-state imaging devices used in reading parts of facsimile machines, etc., have main parts as shown in FIG. are arranged in a line to form a photoelectric conversion section 1, and charge transfer sections 2 and 3 such as COD are arranged adjacent to each other via a transfer gate (TG) on both sides of the photoelectric conversion section 1. A DC bar and A2 are connected to the output side of the amplifier Al,
Output terminals 4.5 of charge transfer sections 2 and 3 are provided on the output side of A2. The charge transfer electrodes of each charge transfer section 2.8 are connected to the drive bus lines DA1 to 04, and the charge transfer electrodes of each charge transfer section 2.8 are
G is connected to bus line TG.

In this configuration, the odd-numbered light receiving elements $1. #3. The charges photoelectrically converted in #5 . . . are transferred to the charge transfer section 8, and are outputted from the output terminal 5 as an odd pixel signal Voo. Also, the even-numbered light receiving element #2 of the photoelectric conversion unit 1. #3...
The #N charge is transferred to the charge transfer unit 2, and is output from the output terminal 4 as an even pixel signal Vgo. Two outputs corresponding to odd and even pixels from the two systems of charge transfer units need to be combined into one time series signal by an external circuit. Therefore, a signal coupling circuit as shown in FIG. 2 is generally used. In other words, two transistors Tr with one load low resistance 1 as a common load.
Draw an emitter follower circuit by combining l and Trg,
The base terminal 5' of J.Funjinuta Trl is connected to the charge transfer unit 3.
The base terminal A of the transistor Tr2 is connected to the output terminal 4 of the charge transfer section 2, and the composite output signal is taken out from the output terminal 6.

By the way, in recent years, in the solid-state imaging device shown in FIG. By transferring charges to multiple charge transfer electrodes and transferring the transferred charges through multiple charge transfer electrodes, a large amount of charge can be transferred without increasing the charge storage capacity of each 7W charge transfer electrode. methods have begun to be adopted.

FIG. 8 shows the drive voltage waveforms applied to the transfer gate TG and each of the drive buses 01 to β4 shown in FIG. 3 and 1, as is clear from the figures, during the period when the potential of the bus line TG is positive, the TG is in an open state, and the charge of each light receiving element is The charges are transferred all at once to the charge transfer electrodes connected to the bus lines 2, 08, and 04 of the charge transfer unit 3.2, and the charges transferred to these three transfer electrodes are sequentially transferred to the odd-numbered charge transfer electrodes of the photoelectric conversion unit 1. The charge accumulation odd-numbered pixel signal Voo from the even-numbered light-receiving elements is output from the output terminal 5, and the charge accumulation signal Voo from the even-numbered light-receiving elements is output from the output terminal 4.

In this way, when signal charges are transferred from each light receiving element to the charge transfer section, the duty factor of the output signal is 50%. e[t, the odd-numbered pixel signal and the even-numbered pixel signal overlap (see FIG. 3).

FIG. 4(a) shows light receiving element #1 in FIG. #3 is irradiated with the same amount of incident light, and the light receiving element $2. #4゜ #6 has the light receiving element $1. The same quantity of incident light is incident on the light receiving element #5, which is smaller than that of the light receiving element #8, and the light receiving element $1. The odd-numbered 11]l pixel signal Voo from the output terminal 5 and the even-numbered pixel signal VKO from the output terminal 4 are shown when a larger amount of incident light than #8 is incident. It is also a diagram showing the combined output signal waveform from the terminal 6 after passing through the signal coupling circuit shown in No. Note that the pressure waveform indicated by the solid line in the figure is the odd-numbered pixel signal VEO.
The voltage waveform indicated by the dotted line is the even pixel signal Voo.

The composite output signal ``0'' in the signal combination circuit shown in Figure 2 is a signal voltage that matches the lower voltage of the odd pixel signal ``00'' and the even pixel signal EO input to input terminals 5 and 4. , light receiving elements #1, #2. -#8. #
The signals from #5 and #6 are correctly combined and output from terminal 6. However, at the timing when the signal of light receiving element #4 should be output, the voltage of light receiving element #5 is
However, there is a drawback that the signals are combined as a false output signal, making it impossible to obtain a correctly combined output signal. That is, when the output signals from the charge transfer units 3 and 2 overlap, if the voltage of the false signal is low at a certain timing for some reason, a synthesis error may occur.

(4) Purpose of invention
I! ! It is an object of the present invention to provide a signal synthesis circuit for a solid-state imaging device that eliminates synthesis errors when synthesizing l accumulated signals into one system of time-series signals.

(5) Structure and purpose of the invention is to provide a photoelectric conversion unit in which a plurality of light receiving elements are arranged in a line, and one charge transfer unit that transfers charges transferred from each odd-numbered light receiving element of the photoelectric conversion unit. and another charge transfer section that transfers charges transferred from each of the even-numbered light receiving elements, and in which output signals from each of the charge transfer sections are made into time-series signals, The signal synthesis circuit is connected to a sample holding circuit and an A/
A two-system signal processing circuit consisting of a D converter and an odd-numbered pixel signal output and an even-numbered pixel signal output digitized by the two-system signal processing circuit are determined at the timing at which each pixel signal should originally be output. This is achieved by providing a signal synthesis circuit for a solid-state imaging device, characterized in that the signal synthesis circuit for a solid-state imaging device is mainly configured with a switching means that alternately and selectively switches according to the following conditions.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 5 is a block diagram of a signal synthesis circuit of a solid-state imaging device according to the present invention, and FIG. 6 is a timing diagram showing the operation of the circuit.

In FIG. 5, 5 and 4 are input terminals to be connected to the output terminals 5 and 4 of the solid-state imaging device in FIG.
An even-numbered pixel signal ■EO comes in from. These signals are amplified by amplifiers 15a and 15b, respectively, and the signals Vao and Voo (a) in FIG.
During the period τ in L(b), the pixel signal is partially turned on, and as a result, as described above, the two systems of pixel signals partially overlap, causing a problem.

For this purpose, the amplified pixel signals Voo and Vgo are input to the sample holding circuits 16a and 161) shown in FIG. 5, respectively, and then the terminals 11a shown in FIGS. 6C and 6D.

Clock pulse NU5HCKI applied from 11'b
Sample and hold is performed using 5HCK2.

In this way, the odd pixel signal Voo and the even pixel signal Vg
The parts shown as #1 to #9 and the parts shown as #2 to #10 in Fig. 6, respectively, of o are shown in Fig. 6(e).
and sample holding circuits 16a, 16 as respective consecutive analog signals depicted as #1 to #9 and #2 to #10 depicted as SHI and Sn2 in (f).
'b appears in each output.

Next, these analog signals SHI and Sn2 are input to the A/D converters 17a and 17b of the respective systems, and correspondingly, they are shown as ADCKI and ADCK2 in FIGS. 6(g) and (h). A/D conversion is performed using clock pulses applied from terminals 12a and 12-b. In this way, coded digital signals ADI and AD2 are obtained at the output terminals of the A/D converters 17a and 17b, respectively, as shown in FIGS. 6(i) and (j).

In addition, in FIGS. 6(j-) and 6(j), #l to #9. are also shown for ADI and AD2 for convenience in order to show whether the coded signals correspond. The symbols +2 to #lo have been attached.

The above-mentioned digital signals A, DI, and AD2 are input separately into the data selector 8 as a switching means in FIG. According to the selection signal SEL shown in , the data selector 18 selects the two systems of digital signals ADI,
AD2 is alternately selected and outputted as the selected signal S'L shown in FIG. 6(1).

In this way, as shown in FIG. 6 α), the odd and even digitized logic pixel signals are arranged alternately in the correct order, and each logic pixel of the two systems described above There is no possibility that the signals will be partially incorrect or that false output signals will appear.

However, up to this trench, odd number signals #1 to #9 and even number signal #
There is a risk of selection signal S at the array boundary between #2 and #10.

For this purpose, this sorted signal S'L is further input to the latch circuit 19 as shown in FIG. After being stored, it is output as a digital combined signal DCO shown in FIG. 6(n).

When this digital combined signal]) is input to the COiD/A converter 20, it is digitized as described above from its output terminal 2, and the combined output ACO (Fig. 6 (0 ) is output, and the pixel signals output from each output terminal 4.5 of the solid-state imaging device (see FIG. 1) can be obtained in an ideal shape.

(7) Effects of the Invention As explained in detail above, if the signal synthesis circuit of the solid-state imaging device of the present invention is used, mistakes in synthesizing the odd and even pixel signals from the two systems of charge transfer units will not occur. <
Since it can be combined into one system of time-series pixel signals, great practical effects can be expected.

1

[Brief explanation of the drawing]

Figure 1 is a blank sheet of paper that explains the configuration of a solid-state imaging device. Fig. 2 is a circuit diagram showing an example configuration of a signal coupling circuit, younger brother 8 is a diagram showing the drive voltage waveform of the solid-state imaging device of younger brother 1, Fig. 4 (a) . (b) is a voltage waveform diagram for explaining the operation of a conventional signal synthesis circuit, FIG. 5 is a block tire duram showing an example configuration of a signal synthesis circuit according to the present invention, and FIGS. 6(a) to (0)
interrupts the operation of the signal synthesis circuit according to the present invention. This is a timing diagram for clarity. In the figure, 1 is a photoelectric conversion section, 2.8 is a charge transfer section, 4,
5 is the output terminal of the charge transfer section, #1 to #N are the light receiving polymers, 1
5a and 15b are amplifiers, and 16a. ], 6b is the sample h circuit, 17a and 17b are A/D
Converter, 18 is a data selector, 19 is a latch circuit,
20 each indicates a D/A converter. 2

Claims (1)

[Claims] A photoelectric conversion section in which a plurality of light receiving elements are arranged in a line, one charge transfer section that transfers charges transferred from each odd numbered light receiving element of the photoelectric conversion section, and a charge transfer section that transfers charges from each even numbered light receiving element. In a signal synthesis circuit of a solid-state imaging device, the signal synthesis circuit has a sample holding circuit and a charge transfer section that transfers electric charges, and the output signal from each charge transfer section is a time-series signal. /D converter Karakuru 2
Odd number pixel signal output and even number pixel signal output digitized by the signal processing circuit of the system and the signal processing circuit of the two threads are alternately selected according to the timing at which each pixel signal should originally be output. 1. A signal synthesis circuit for a solid-state imaging device, characterized in that the signal synthesis circuit for a solid-state imaging device is mainly configured by a switching means for switching automatically.