JPS5836055A - Signal discrimination system - Google Patents

Abstract

PURPOSE:To lighten a load on a processor by detecting data transmission is carried on in which phase modulation and frequency modulation modes by the output level of a filter which extracts the data timing signal of a received phase- modulated signal. CONSTITUTION:When which of frequency and phase modulation modes is applied to the reception of the receiver in the figure which receives transmitted data consisting of phase-modulated low-speed data for control procedure and phase- modulated high-speed data such as a facsimile signal repeated alternately is not evident, the demodulation of a low-speed data regenerating device 1 and the timing extraction of the high-speed data of a filter 2 are carried out simultaneously. In this low-speed data processing, when the output of the filter 2 is less than a specified threshold value, the received sequence is the low-speed data and the low-speed data processing is continued. When the output of the filter 2 is greater, on the other hand, the received sequence is the high speed data, so the low-speed data processing is stopped and a high-speed data regenerating device 4 and a D-PLL3 are actuated to perform high-speed data processing.

Description

[Detailed Description of the Invention] The present invention performs digital processing in a data transmission method in which a phase modulation method (including a quadrature amplitude modulation method; hereinafter simply referred to as a phase modulation method) and a frequency modulation method are used in combination. The present invention relates to a signal identification method that can reduce the burden on a processor.

An example of a data transmission method in which a phase modulation method and a frequency modulation method are used in combination is, for example, data transmission in a facsimile.

In facsimile, a system is used in which, prior to transmitting an image, signals for control procedures are first transmitted at low speed using a frequency modulation method, and then image signals are transmitted at high speed using a phase modulation method.

When using such a data transmission method, the signals of both types are generally clearly differentiated between the sending and receiving sides according to the facsimile transmission procedure, but if the normal procedure is deviated from for some reason, such as a momentary interruption of the line, , the receiver cannot determine which system the signal is from. Conventionally, - to solve this problem, the receiving section processes both signals in parallel, and the terminal side monitors on which side the legitimate data can be received. The signal was identified.

Therefore, the receiver is required to have the ability to process both types of signals at the same time.If this is to be achieved analogously, separate hardware is required for each, but if this is to be achieved digitally, the same It was necessary to prepare separate hardware or increase the processing capacity of a digital signal processing processor to multiplex process different demodulation methods. Such a digital signal processing processor consists of a sample value series real-time processing device d mainly composed of arithmetic operation functions such as multipliers, l,
When attempting to perform multiple processing as described above, the burden on the processor increases significantly, making it difficult to create an efficient device.

The present invention attempts to eliminate such drawbacks of the prior art, and its purpose is to ensure that the line is normal in a data transmission system in which phase modulation signals and frequency modulation signals are transmitted alternately. In the processing of signal identification when departing from the standard procedure, it is not necessary to process both types of signals at the same time, and therefore there is no need to provide separate hardware for processing, or to place an excessive burden on the processor performing the processing. We aim to provide a method that eliminates the risk of

The signal identification method of the present invention monitors and keeps the output level of the filter that extracts the data timing signal in the phase modulation transmission signal from the incoming signal in the receiving section that processes the signal of both formula (3) as described above. The signal is compared with a threshold level, and based on the comparison result, a processing mode for the transmission signal is determined and received.

Hereinafter, the present invention will be described in detail with reference to Examples.

High-speed data transmission using the phase modulation method is performed using a synchronous method. Therefore, it is essential to extract the timing component from the received signal. On the other hand, low-speed data transmission using the variable frequency W, +4 method is a start-stop type and generally does not require timing extraction, and naturally, the timing component of reproduced data does not have the frequency band of high-speed data transmission.

Therefore, once it is certain that a signal has arrived, it is possible to identify which system the received signal belongs to by monitoring the timing output of the timing extraction filter in the high-speed data transmission system. Such identification is possible without requiring any special processing, and is not particularly burdensome in high-speed data transmission where the conditions of real-time processing (4) are severe.

FIG. 1 conceptually shows the configuration of a receiving device in a data transmission system in which a phase modulation system and a frequency modulation system are used in combination. Further, FIG. 2 shows a processing flow when the system of the present invention is applied to the configuration of FIG. 1.

In FIG. 1, reference numeral 1 denotes a data reproducing device based on a low-speed data transmission method, which includes a discriminator, a code regenerator, etc., and is capable of processing data transmitted from a low-speed data transmission signal based on a frequency modulation method, such as a fax control procedure. Reproduce. Reference numeral 2 denotes a timing extraction filter that extracts a timing signal from high-speed data using a phase modulation method. 6 is a digital phase-locked loop (D-PLL), which uses the timing signal extracted by the timing extraction filter 2 to
Generates a clock signal for high-speed data reproduction. 4 is a high-speed data transmission system data reproducing device, which includes a demodulator, a roll-off filter, an equalizer, a carrier phase corrector, a discriminator, a code converter, etc.; Regenerates data transmitted from a phase modulation high-speed data transmission signal.

Under normal conditions, the low-speed data transmission method data reproducing device 1, the high-speed data transmission method data reproducing device H4, the timing extraction filter 2, and the D-PLL 6 are configured to perform one of the following depending on the signal transmitted from the transmitting side. is working.

If, for some reason, it becomes unclear which method of reception processing should be performed in the receiving section, the processing is performed according to the flow shown in FIG. That is, the reception section detects the arrival of a signal, and when the reception is detected, the low-speed data transmission method data reproducing device 1 performs demodulation processing for low-speed data transmission, and at the same time, the timing extraction filter for demodulation of high-speed data transmission is performed. Only the timing extraction process in step 2 is executed. In this low-speed data processing mode, if the output of the timing extraction filter 2 is not larger than a certain threshold value (VO), the received sequence at that time is low-speed data, so processing for low-speed data transmission continues. If the output of the timing extraction filter 2 is larger than the threshold value (V,
5, the low-speed data transmission method data reproducing device b', stops the processing in 1, and the processing contents are executed as low-speed data! mode to high-speed data processing mode.

In this way, according to the system of the present invention, both signals can be relatively easily identified using existing processing functions, and processing can be performed according to each transmission system. On this occasion,
In order to perform demodulation processing for low-speed data transmission at the beginning of the processing flow, R5 (Request to 5a
nd) -C5 (Clgar to 5 and) There is an advantage that reproduction data can be kept pupil quickly for low-speed data with a short time. The timing extraction filter can be implemented, for example, by a digital recursive (IIR) filter. Note that when using the method of the present invention, immediately after switching from low-speed data processing to high-speed data processing, the receiving monitor may receive an error υ.
This is a problem because processing using the method ``produces a failure, but does not occur'' is normally performed when the reception 1111 process is not performed normally due to a momentary power outage, etc. (7). There isn't.

A receiving device for a fax or the like can be realized by program processing using a processor. For example, the 4800 IIp
A modem receiver is realized that can process 100 pau high speed data and 300 pau low speed data. This method is already well known, and results have been reported in various places.

The receiving device shown in FIG. 1 can also be realized by storing the above-mentioned two IIAJ processing for the two transmission signals in an external program memory, and having the DSP processor execute the processing according to the instructions in this memory. can. However, if the demodulation processing for two transmission signals is performed simultaneously, the processing capacity is insufficient, so by using the method of the present invention described above, it is possible to perform demodulation without causing a problem in data transmission while reducing the burden on the processor. becomes possible.

(8) FIG. 3 is a block diagram showing the configuration of an embodiment of the signal identification method of the present invention. In the same figure, reference numerals 11, 12 and 16 are program memories (MEM), where the memory 11 stores a processing program for a timing extraction filter in demodulation of high-speed data transmission, and the memory 12 stores timing extraction filter processing programs in demodulation of high-speed data transmission. Stores processing programs for necessary functions other than filters. The memory 16 also stores a processing program for demodulating low-speed data transmission. A latch 14 latches and outputs the level of a timing signal in high-speed data transmission using a clock CK1. 15 is a level difference detection circuit which compares the magnitude of the timing output and the reference level, and sets the output OT1 to a high level when the timing output is larger;
When the reference level is higher, it is set to low level. 16 is a calculation unit (DSP), which operates the modem receiving section according to a program.

performs arithmetic operations and reproduces data. Reference numeral 17 denotes a program counter (p-crR) which provides a memory address and is reset to the original address by a reset signal issued by the DSP 16 when a series of programs is completed. 18 is an analog-to-digital (AID) converter that samples an analog input at a certain frequency, converts it into a digital signal, and transfers it to the DSP 16 via bus 1. 19 is a discriminator (DEC), which is a P-CT
When a certain value of R17 is detected, the chip enables of the memories 11 to 16 are controlled to prevent the programs in each memory from being read out at the same time.

In Figure 3, if the line leaves the normal procedure,
Upon detection of the arrival of a received signal, the memory 11 and the memory 13 are first selected, and as described above, the demodulation process for low-speed data transmission and the operation of the timing extraction filter in the high-speed modem are performed.

The DSP 16 has sufficient processing power for these processes. Furthermore, the memory 11 and the memory 13 are not executed at the same time, and the DBC 19 detects either one.

The output level of the timing filter created by the DSP 16 is output to the latch 14 and latched at a fixed timing such as a sampling period. latch 14
The output of is compared with a reference level in the level difference detection circuit 15, and the comparison result is outputted to the output OT1. When the timing signal output level is smaller than the reference level, the output is 0.
T1Vi takes low level and selects memory 1'5 as it is, thereby causing the receiving section to pull out low-speed processing and execute 1. Conversely, when the timing signal output level is high, output OT1 becomes high level. . This is a high-speed data transmission mode, and when the memory 11 and memory 12 are not in use, the back half of the high-speed data transmission is performed.

The DSP 16 has sufficient processing power even in this case.

As explained above, according to the signal identification method of the present invention, in the case of a data transmission form in which a phase modulation method and a frequency modulation method are used in combination, the characteristics of both signals can be easily identified. Therefore, since there is no need to process both signals in parallel, there is no need to separately prepare hardware to process both signals in parallel, and there is no need to increase the burden on the processor that processes them, which is extremely effective. is.

[Brief explanation of drawings]

Figure 1 shows 1111 views of a receiver visit in a data transmission system in which a phase modulation method and a frequency modulation method are used together.
Fig. 2 is a block diagram conceptually illustrating the ``J configuration''. 1. Discharge speed data transmission system data reproducing device; 2.
Timing extraction filter, 6... Digital phase periodic loop (r)-PLL), 4... High speed data transmission system data reproducing device, 11, 12. i3...Program memory (MEkf), 14...Latch, 15...Level difference detection circuit, 16...Performance>t unit (I) S
P), 17...program counter (P-CTR),
18...Analog-digital (A/D) converter, 1
9...Identification"d5 (1) EC). Patent applicant Fujitsu Limited

Claims (1)

[Claims] Phase change′v! 4. A filter that extracts a data timing signal in a phase modulation transmission signal from an incoming signal in a receiving section of a data transmission system in which a signal of a system (including orthogonal amplitude modulation) and a signal of a frequency modulation system are transmitted alternately. 1. A signal identification method comprising means for monitoring the output level of a signal and comparing it with a predetermined threshold value, and determining a processing mode for a transmission signal based on a comparison result of the comparison means for reception.