JPS5835795A - Precharge circuit for data line of memory - Google Patents

Abstract

PURPOSE:To perform stable memory operation, by shortening first data line pairs at the start of precharge for data lines and then performing the precharge of the data line pairs to the power supply voltage. CONSTITUTION:At memory operation, a transistor (TR) Q11 is activated with a control signal phi5 of high level at the start of precharge and charges on a data line DL are discharged to ground, through the TRQ11. After short-circuit of the data line pair DL, an input signal phi4 goes to high level and a level of a node N4 is further increased through the capacitance coupling between a drain electrode of a TRQ9 and the gate electrode N4, to which the input signal phi4 is supplied. Thus, the node N2 is charged. When a boosting signal phi3 rises with a little delay from the leading of the input signal phi4, the level of the node N2 is boosted to a level, a power supply voltage Vcc or over with a bootstrap capacitance C2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data 1 precharge circuit for a memory, and particularly to a cheater precharge circuit suitable for a dynamic random access memory.

Generally, in a dynamic random access memory, a pair of data il is precharged to the power supply voltage level during standby, and when the corresponding memory cell is selected during operation, a minute signal appears as a pair of data IwK. or amplified by +4 with a preamplifier.

Since this signal has a very low amplitude level, the data lines must be balanced (precharged) as much as possible.

For example, in the conventional data line precharge circuit shown in FIG. 121, a minute signal generated from a storage cell during memory operation is sensitized by the preamplifier 10, and the level of a pair of data lines DL is approximately vo. level, D L% ground fiG
Becomes ND level. When the d storage cell enters the standby state, the data line precharge signal φ1 goes high and II!
! Edge gate tJ field effect transistor (GIFIT or M8FICT) Q4 and Q5 are conductive, both data l! DL and DL are transistors Q4 and Q
Short circuit leaked after 5km.

Next, the boost signal φ3 becomes high level, and the node voltage N2 or II-
Voltage V. . - Also, the level of the NoriCharge signal φl becomes 1 [source voltage v0° level or higher, and 1
A pair of data lines DL and DL or vo. Level 1 by the way
As shown in the operation diagram in Figure l12, the data line DL>! BiDL
When Om is in contact, the voltage at the moving point N2 is at the 1 voa level, so it is a transistor. Charge is supplied to the t-node N3 through 1 node M3, and the level Fi1[l! 1liII pressure V. . From transistor. f#i with the dark value voltage of 3 subtracted
It becomes vo. Therefore, the level of data DL that rarely reaches the memory operation extra-high level cannot be lower than this normal v0, and the level of data @DL or this value V at a low level
. The data line pair DL and DL are not short-circuited until the level reaches 11. This is because when the pair of data short circuits, transistors Q4 and Q5, are turned on, the transistor Q3 is also precharging at the same time.69
, which results in insufficient shorting of data line pairs and unbalanced precharge levels. Due to this imbalance and memory cell force, there is a risk that if the selection is missed, the storage contents of 7 will be read as tv4.

This voice cicada c, oyo-5ri (Hyosada, 9 Kuhana, 1 bunch, erase, precharge the data line in a balanced manner to ensure stable memory operation. Precharge the data line of the memory. The purpose is to provide circuits.

According to the present invention, the purpose of this is to first short-circuit the data line pair when starting precharging of the data line, and then precharge the data line pair to the power supply voltage. This is achieved by separating the charging operation and the charging operation of the line pair.

FIG. 3 is a circuit diagram illustrating an embodiment of a memory data line precharge circuit according to the present invention, in which the same elements as in the circuit of FIG. 1 are designated by the same reference numerals.

In this circuit, a pair of data @DL and DL connected to the preamplifier lO are connected to the MI8) transistor Q.
4 and Ct5C), 4N3trMIi3) 5y source-drain of transistor Q3 11! It is connected to the DC-source v0゜K through it, and also the MID) transistor Qllf)
7- X + - Grounded via the drain path.

The gate electrode of the transistor 11 is 'imitim number φ5
There is a connection leak. As will be described later, there is no need for a path from the node N3 to the ground pressure via the transistor Qll.
0) Ranjistor. Gate 3 I! The ultimate is bootstrap! It is connected to the boosted signal φ3 via 'a2, and is also connected to the node N2 between the transistors Q9 and Q10 via M connected in series.

The source of transistor Q9 is not connected to input signal -4,
The drain of the transistor GLIO is connected to the ground, and the control signal φ2 is connected to the seventh gate cap.

The gate-pole k14 of transistor Q9 is connected to the supply voltage V through the north drain path of transistor QB.

. 6, the connection point N5tc of M113 transistors Q6 and q7 connected in series between and the ground. A control signal φ2 is applied to the gate electrode of the transistor. 7, the gate I [pole is connected to the boost signal φ3 δ
It will be done. Also, the gate electrode of transistor QB is connected to the power supply voltage V
. #jl is missing from 0.

Next, the operation of the circuit shown in FIG. 3 will be explained by referring to the operation diagram shown in FIG. 4.0 First, during memory operation, the control signal φ2 is at a high level at the node N4, so that the power supply voltage 11 is V. . The transistor Q101lr+!+ is charged to a level lower than the threshold voltage Vtht of the transistor q6.
It is interrogated by the 1m signal φ2 of the level, and the node N2i is set to the ground level, and thereby the voltage level is set to 1J+-? - ditransistor q3 becomes non-additional. When a memory cell (not shown) is selected in this state, the data pair DL and the minute signal on the DL are read by the preamplifier IO, and one data listening DL is read.
Is the data on the other side high? IIIDL becomes low level I/c.

Next, precharge No. 11 φl is V. . When the level is reached, transistors Q4 and q5 become conductive, and the data line pair DL and DL are short-circuited through them.

At this time, since the precharge transistor Q3 still maintains the non-conducting state 11t-, this 'tj111; b node 1
The addition of charge 1Iii to 3 is not performed. Therefore, until now, the high-level MAt message data 111IIID
Since L can also be lowered to a sufficiently low level by 1 as shown at point M50 in FIG. 4, the data pair DL and D
The shorting of L is done quickly.

By the way, in the illustrated embodiment, the node M3 is the transistor Ql.
It is grounded through lt-. At the start of precharging, this transistor all is energized by the control signal φ5 at a high level, and the charge of data MDL, which has been at a high level until then, is passed through the transistor CLIIt and discharged to the ground. In this case, as shown by fi+52 in the diagram tJ14, the shorting operation of the data line pair DL and DL is performed more effectively.

After the data line pair DL and DL are short-circuited, the input signal φ4 becomes high level 9, and the drain electrode of the transistor Q9 and the gate electrode of the transistor Q9 to which this human input signal φ4 is supplied, that is, the node The level of node N4 further increases due to capacitive coupling with M4. This is K
Therefore, node N2 is V. . charged to the level. Next, the boosted signal φ3 rises a little later than the rise of the input signal φ4, and the level at point m N20 is set to 1 voltage V by the bootstrap capacitor 02. . The voltage is then increased to i-. This t'LK makes the precharge transistor Q3 conductive, and the data line pair DL and DL becomes vo through the four transistors Q4 and Q5. Precharged to level.

According to the present invention, the precharge transistor Q3 is made non-conductive before starting precharging of the data line pair DL and the data line pair DL The DL communication is carried out smoothly, and the subsequent precharge is carried out with good balance. Therefore, it is possible to correctly read a minute signal when a memory cell is selected in a later memory operation.

[Brief explanation of the drawing]

, Figure 1 is a circuit diagram of a conventional data line precharge circuit, i! Figure 2 is an operation waveform diagram for explaining the operation of the circuit in Figure 1, Figure 113 is a circuit diagram showing the data string precharge cycle according to the present invention, and Figure 113 is a circuit diagram for explaining the operation of the circuit shown in Figure 3. FIG. Q 3.=m1t) M I 8 ) 9y di xp, Q4.
l; L5...1 pair of MI transistors, Q10...
・Transistor from M of 112, qll...MI transistor of 113, 02...Putstrap capacitance, φ1...precharge signal, φ2...control signal,
φ3... Boost signal, φ4... Input signal, φ5...
Control signal. Figure l Figure 21￥l -OF'6'I Figure 4

Claims (1)

[Claims] 1. A pair of M1B transistors connected in series between a pair of data resistors connected to a memory cell. a first MS transistor connected to a reference potential source of one of the interconnection points of the pair of MIS transistors; Restrictions 1
and a second M8 transistor whose terminal is connected to the other reference potential source. +1! 20M engineering 8 transistors conduction I! 1 M
After transilluminating the 8 transistors, the phantom MIS)
1N111 means for conducting a transistor to short-circuit a pair of data Iwt, then conducting the first MIfl transistor and precharging the pair of data mt through the pair of M8 transistor tubes. A memory data precharge circuit which is characterized by including a 2.9 Claims: $1. The precharge circuit according to claim 1, wherein the precharge circuit includes 113 MI transistors connecting the mutual connection point to the other reference potential source, and wherein the control means A data precharge circuit for a memory having a C and tW characteristic that conducts a third MI8 transistor when the first M transistor t-!l is cut off. 3. Feature 111!F Claims In the precharge circuit according to item 1 or 2, the control means is connected to the control 4[l terminal of the MIS) transistor of tpl and
1. A data line precharge circuit for a memory, comprising a booster circuit for rapidly discharging a transistor.