JPS5835651A - Stack preventing circuit for programmable device - Google Patents

Abstract

PURPOSE:To prevent stacking of a programmable device, by performing the reset operation or the nonmaskable interrupt operation by a microprocessor when a program runs away. CONSTITUTION:When the program processing is executed normally, a timer reset pulse 30 is issued from a decoder 3 at intervals of a prescribed time T2 shorter than a prescribed time T1 of a hardware timer 4, and the timer 4 is reset each time, and the output of the timer 4 is not issued. If the program runs away, the timer 4 is overflowed to output the reset operation to an indicating line after the elapse of the time T1 because the timer reset pulse 30 is not issued from the decoder 3. By this output, a microprocessor 2 performs the reset operation. When this operation is impossible, the timer 4 outputs a nonmaskable interrupt signal of the indicating line, and the processor 2 performs the nonmaskable interrupt operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stall prevention circuit for a programmable device using a microprocessor.

Programmable devices that use a microprocessor that is independent of the main device, such as service trunks in conventional electronic exchanges (for example, multi-address service trunks that connect one subscriber to multiple subscribers and provide broadcast services or conference services), require memory storage. When the program runs out of control due to corruption or an illegal sequence, the microprocessor cannot be reset and the programmable device stalls.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit for preventing a programmable device from stalling by eliminating the above-mentioned drawbacks by performing a microprocessor reset or a non-maskable interrupt after a hardware timer overflows when a program runs out of control. It is in.

A programmable device star-start prevention circuit according to the present invention is a programmable device using a microprocessor, and includes a decoder and a hardware timer, and when the program runs out of control, the microprocessor is stopped after the hardware timer overflows. It is characterized by instructing either a reset operation or a menmaskable interrupt operation.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a service trunk to which a stack prevention circuit of a programmable device according to the present invention is applied. In the figure, 1 is a trunk circuit that serves as the main unit and provides services to subscribers, and 2 is a trunk circuit that is connected to the trunk circuit 1 (via an information control line 10) and that executes a program taken out from memory to an input/output VC. A microprocessor 3 sets the address of the input/output device and generates a timer reset pulse 3 during execution of the program.
A decoder 4 that outputs 0 has a counter that counts all 20 clocks from a clock source (not shown), and is reset by a timer reset and pulse 30, and furthermore, when an overflow occurs, it is output via an instruction line 40. Hardware timers 50, 51, which instruct the microprocessor to reset, reset, or non-maskable interrupt operations;
Reference numeral 52 denotes an address line, a data line, and a control line, respectively, which connect the microprocessor 2, decoder 3, and the memory or the input/output device.

Next, the operation of this embodiment will be explained. trunk circuit l
The operation of the microprocessor, S2, and memory or input/output devices is similar to a conventional microprocessor-based service trunk. That is, based on the information from the trunk circuit 1), the microprocessor 2 retrieves the data at the address of the memory designated via the address @SOt via the data line 51 and controls the input/output device via the control line 52. Executes program processing such as Set hardware timer 4 to specified time T1 (for example, 1 second)
Set the No. 1-Dware Tie i4 in advance.
A counter is provided to count 20tl of clocks as described above. When the program processing is normally executed, the decoder 3 sends a Tie signal every specified time T2 (for example, 0.5 seconds) smaller than the specified time T1! Lyceum? ) Since the hardware timer 4 is reset each time the pulse 30 is issued, the output of the hardware timer 4 is negligible. On the other hand, when the aforementioned program runs out of control, the tights reset pulse 30 is not generated from the decoder 3, so after the specified time Tl has elapsed, the hardware timer 4 overflows and outputs a reset signal to the instruction line 40, and the micro Instructs processor 2 to perform a reset operation. In response to this instruction, the microprocessor S2 performs a reset operation, so the restart processing routine runs and the service trunk is restarted.
There is nothing to do. If it is impossible to reset the microprocessor 2, for example if the reset operation of the microprocessor 2 also resets other normal input/output devices, making it impossible to continue processing, the hardware timer 4 Since the microprocessor 2 outputs a non-maskable interrupt signal to the instruction line 40, the microprocessor 2 performs a non-maskable interrupt operation to be described later, and program processing is automatically restarted, so that the service trunk does not become stuck.

Next, FIGS. 2(at) and 2(b) are diagrams for explaining the non-maskable interrupt operation.
o and pl indicate areas of the memory for normal processing programs (LAM and ROM) 1 areas for abnormal processing programs (ROMt), and a and b are the start addresses for maskable interrupts and non-maskable ones, respectively. Indicates the start address due to interrupt, also DI,
EI indicates a disable interrupt and an enable interrupt, respectively, and INT and NINT l;j indicate an interleaved signal (generated by an interval timer or the like) and a maskable interleaved signal, respectively.

In the maskable interrupt operation, an interrupt enable flip-flop (not shown) in the microprocessor is generally activated by an interval timer or the like to execute a normal processing program. On the other hand, in the non-maskable interrupt operation, when an interrupt request occurs, a fixed memory address is set by a program counter (not shown) in the microprocessor, and an abnormality handling program is executed using this memory address as a start address. Note that the stack prevention circuit (
If the output of the interrupt enable program (not shown) is placed in a maskable interrupt, if the program goes out of control,
The output cannot be placed in a maskable interrupt because the output may be disabled.

First, the area P1' is set to ftROM to prevent its memory contents from being destroyed due to program runaway. The normal processing program is executed by inputting the start address aK to DI (disable interrupt in normal operation), and when this processing is completed, it becomes interruptible by the enable interrupt EI, and other program processing is performed. It spins idly (indicated by the dotted line in Figure 2(b)). Next, jump to the start address a by the interwoven signal INT, and repeatedly execute the above normal processing program (indicated by the arrow in Fig. 2 (b)) (normal processing operation) at 0%, and when there is an abnormality, that is, execute the above normal processing operation. If, for example, the program goes out of control at time t (as shown by the dashed line in FIG. 2(b)), the stack prevention circuit is activated and the non-maskable interwoven signal NINT changes to the start address when the specified time Tl has elapsed. Enter b, and the abnormality processing program is executed (abnormality handling operation). After this abnormality handling operation is completed, if area po is ROM, the contents of the memory will be destroyed. If area po is RAM, the contents of the memory will be destroyed. Therefore, after reloading the normal processing program into all areas Po, the normal processing program is executed by jumping directly to the start address (as indicated by the arrow in FIG. 2(b)).

Next, FIG. 3 is a diagram showing an embodiment of the decoder and hardware timer in FIG. 1. In the address comparison circuit 31, a hardware timer (counter) 4
The address assigned to address line 50 is compared with the input address from address line 50, and when the two addresses match, output 32 is given to AND circuit 33. For example, if the hardware timer 4f is reset when the data line 0 is @1, the data line 5 is connected to the AND circuit 33.
The data, tabit, is given through 1. Note that when the data is don't care, the data 1s51 is unnecessary. Furthermore, the AND circuit 33 has a control line 52f! :
A write instruction for the input/output device (hardware timer 4 in this case) is given via the input/output device. AND circuit 33Fi above 3
Enter the species (input 2 types if the data is don't care)
t-AND, and the timer reset pulse 30 is applied to reset the hardware timer 4 and to the t terminal R8T. A hardware timer (counter) 4 counts a clock 20 inputted to a clock pulse terminal CP, and is reset each time it receives a timer reset pulse 30. Since the timer reset pulse 30 is not input when the program runs out of control, the hardware timer 4 overflows after the predetermined time Tl has elapsed, and a reset signal tA from the overflow terminal OVP to the instruction line 40 outputs a non-maskable interrupt signal.

As is clear from the above explanation, according to the stack prevention circuit of the programmable device of the present invention, even if the program runs out of control during program processing, the program processing can be stopped by performing a microprocessor reset operation or a non-maskable interrupt operation. This has the effect of preventing the programmable device from getting stuck.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a service trunk to which a stack prevention circuit of a programmable device according to the present invention is applied; FIG. 2 is a diagram showing one embodiment of the decoder and /S-ware timer in FIG. 1. 1...Trunk circuit, 2...Microprocessor, 3... ...Decoder, 4...
Hardware timer, 10...Information control line, 2
0...Black, 30...Timer reset pulse, 31...Address comparison circuit, 32
...Output, 33...AND circuit, 40
...Indication line, 50...Address line, 5
1...Data m, 52...Control line.

Claims (1)

[Claims] A programmable device using a microprocessor, comprising a decoder and a hardware timer, and instructing the microprocessor to perform either a reset operation or a non-maskable interrupt operation after the hardware timer overflows when a program runs out of control. A programmable device stack prevention circuit characterized by: