JPS5835634A - Data communication network - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data communication system whereby a plurality of host converters are connected to a particular type of processor.
The present invention relates to a data communication system capable of communicating with a data communication terminal by means of a data communication I10 subsystem using a device.

This filing is technically related to a number of patent applications and previously issued patents. The related patent application was filed on June 27, 1979 and was filed by inventor R.O.
Catller and Br1an Forb
r M 1c of serial number slip No. 052.687 by es
ro -P rooeSSOr 5VStlSI
Facllltatlng Repetltlono
Application filed with f In5tructlons J: 1
Filed on June 27, 979, inventor Robert
Serial No. 052.477 by Catller r M 1orqprocassor S V
Stel W 1th 5source
Address S electronJ Application filed on June 27, 1979 by Rob
ert Catller and B rlan F.
Serial number slip 052.478 r by orbes
M 1croprooess.

r HaVlnl) Word and By
te HandllnO' and the original I: Invention filed on June 27, 1979 @ Robar
t Catller and 3 rlan l:
Serial number slip No. 052.336 by orbes "[)
Igltal system ror
Data
ng universal l nl) utlo
utput M 1 Application layered with oroprooasaor J; Invention filed on June 27, 1979 @ Roba
rt Qatller and B rlan F
orbes consecutive number slip 052.350 r
M Ioroprocess.

r 5yste ■ With S peolal
lzed I n5tructlon Ferma
t J and I: Invention 11 Ronald Ma
rMesoryControl by thews
C1rault for S ubsy
stes Oontroller J. Application: Inventor RObllrt Catll (Ir, C
ralOHarrlS and Ronald Math
r Subsystem-control+ by ews
Application entitled ter J: and December 14, 1979
rIlo Subsyate serial number 103.739 by inventors Kenneth Baun and Oonalti Mlleral, filed on
gi U slng D ata L
Including applications entitled Ink Processors J.

This issued patent, which involves the use of an input/output subsystem to connect a main host computer and a remote terminal, is incorporated herein by reference.

Inventors: oarwtncook and D.O.L.
r I nt by ld Ml 11ers I
ellgent I nput10utput I interfaoe---Q 0ntrOI
Ll nlt for Inputio
No. 4,142,520 entitled U.S. Pat. This article describes the peripheral/II controller, known as the line 111311 processor, which controls and handles data transfers between any peripheral terminal and the main host system.

Inventors D arvtn 000 and Donald
M 13- “M odular 81ook” by Iers Seal
Ll nlt forl 10 8ubsyste
mJ tW1t67me! J j) Combined 1/1m Patent No. 4.
No. 074.352, this case describes a base module device that houses and supports eight peripheral-control groups and interfaces them to a main host computer system.

Invention 11 [)r by onald Mllersl
Interfa08 S )lstel P
rovldlng interfaces t.

Central Prooesslna U
nlt and Modular P
rooesllor C0ntr0116rS f
U.S. Pat. We describe the coordinating I10 translator or ll1l in the main host system, designated as "IOT".

Inventors D arwln Cook and Donald
I +vut/ Output by MIltars Summer
S ubayste-f.

r D Igltal () ata pro
U.S. Pat. No. 4,189.769 entitled ``Oessor System'',
This incident involves multiple (called line control processors)
II number of peripheral-controllers describes a subsystem consisting of a base module for data exchange with the main host system. The peripheral-controller and base module form an input/output subsystem for controlling data transfer to/from a number of peripheral locations to the main host computer system.

Invention 1: enneth w, Baun,
JIIIG, r by 5unders
Data L Ink Proaes@or
for Maonetlo Tape
Data Transfer3ysta
United States Patent No. 4゜280.1 designated as s J
No. 93, this patent is called a data link processor,
An improved J11 side handles data transfers between the main host computer and connected magnetic tape peripherals.
I will tell you the first thing.

The above issued patents form the basis and background of this application and are incorporated herein by reference. These patents describe many data communications networks in which the main host computer provides an I10 descriptor command and a data link word task, and receives a reverse result descriptor word indicating the completion or non-completion of any job task. Describe and discuss the elements of and their m-operations.

These patents also describe the use of a base connection module device that houses a slide-in card that forms a processor controller, a distribution control card, a maintenance card, and other slide-in card devices. Each base module 1iIll has one or more processors w4I
II- and provides a distribution-1 (DC) for connection or disconnection to the main host computer, and also provides a maintenance card for diagnostic testing of the circuitry in its base module. These card devices were previously described in the above-mentioned patents, which are hereby incorporated by reference.

"Communications Standard" means a set of rules or standards governing the message format used by a particular remote peripheral in data transfer operations over communication lines to a center stage communication with a main host computer. Some of the factors that differentiate the various communication standards are: synchronous operation, synchronization, asynchronous operation, beginning and end of a message sequence, length of message segments,
Including.

Since there is no standard communication standard common to all peripheral data communication terminals, the system requires separate communication control I/O.
It has generally been necessary to adapt the system to the individual standards being processed by the system. Furthermore, new types of peripheral devices with emerging standards are often developed, which in turn requires that new communication controls III be designed for the system and adapted to this type of device.

The objective of these manufacturers and users of data communications networks and subsystems is to
The goal is to increase the throughput of data per amount of Iw and reduce the number of elements required while also providing highly reliable data communication to and from remote stations in the most efficient manner. It was also about simplification and economy.

Many data communications subsystems not only handle the individual characteristics of the various types of data communications peripheral terminals, but also allow the main host computer to handle each step of the process, including data transfer to and from the terminal stirrup. In order to have a continuous and positive relationship with others, use control.

As shown in the above-mentioned patents, one way to reduce the complexity and cost of a data communications network, in addition to obtaining better controllability, is to remove most monitoring and control functions from the main host processor. The main purpose is to release data, maintain the communication ability with the connected terminal, and maintain the communication ability to send data to or receive data from the main system at certain times. - placing them in the hands of the controller.

Often, the architectural and functional structure of the network provides the most effective use of its components for data communication between remote terminals and a central main host computer or multiple such host computers. All questions arise as to how to configure it.

The data communications networks described herein, in which one or more main host computer systems operate a large number of remote terminals for data communications purposes, provide a means for data transfers, thereby providing a means for data communications between remote terminals. Up to 16 data communication lines from the device are connected to 16 line adapters that are part of a line support processor that includes:
It checks that the various emerging line communication standards are met and then provides a common line standard for operation with network support processors. The network support processor receives initiation of a data transfer instruction from either a main host processor or one of a plurality of up to four main host processors, and is configured to ■Perform the necessary data transfer using the data terminal device. Communication between line support processors and network support processors is standardized and is not subject to the wide variety of standards required for remote data communication line installations. The network support processor and its satellite line support processors constitute the front end control over which distributed processing functions are made to occur in the architecture of the communication network. ' The data communications network described herein coordinates and performs data transfer operations between a plurality of main host computers and a number of interlinked peripheral devices connected by telephone or other forms of data communication line channels. A base connection module is provided into which slide-in card components can be inserted to form a front-end processor.

The present invention describes a data communication network that uses a specialized network support processor to handle data communication functions between one or more host processors and a plurality of remote data terminals. The plurality of main host computers individually connect via message level interface buses to separate distribution control cards contained within the base connection module. The base connection module provides a bus, designated as a data link interface (DLI), that connects to network support processors. network support processor
Communicates with the main host system via the data link interface. It controls communication with external devices via a message level interface (MLI) that connects to a distribution card (DC) in another base connectivity module that supports one or more distribution cards.

The outer distribution card has a data link interface (
DLf), whereby each distribution card supports up to four line support processors (DLf).
SP) and each of its processors can be connected to
It is capable of controlling and processing 16 line adapters communicating with 16 remote data terminals 21.

By using the I10 descriptor command and data link task identifier, the main host computer can:
You can start a network support processor that receives data from or sends data to a selected remote terminal, and the network support processor determines whether a particular task is completed or not completed by the main system. A result descriptor message is provided along with the task identifier word to inform the task.

The network support processor, designated here as NAP, is a dual processor, general purpose minicomputer programmed as a front end data communications processor. As discussed in the patents cited above, certain main host computers have been designed for systems that provide what is known as a message level interface (ML).

It is these types of main host computer systems that are compatible with the use of network support processors and their 22-data communication capabilities.

Thus, a data communications subsystem is included herein that utilizes the message level interface described above and includes a series of data communications processors. These data communications processors are sometimes referred to as data communications frame processors, and are based on the concept that each provides data communications and control capabilities to a series of data communications lines that connect to a communications terminal or modem. , used herein as the official name for Line Support Processor (LSP).

Any data communications subsystem is controlled by a network support processor. The operation of message level interfaces and their use are described in the above-mentioned patents, which are incorporated into this disclosure.

In this data communications subsystem, the host computer has about four network support processors (N
SP). Furthermore, each of the network support processors can support as many as four line support processors (LSPs), while each line support processor supports up to sixteen line adapters. In this way, one host computer
It can be seen that H.256 has the ability to control which data communication lines. It can also be seen that one network support processor can interface with four separate host computers, as shown in FIG. 1A.

Referring to the first AII, an overview of the data communication network can be seen. The network support processor 80 has II* 1001 - shown as an emergency data link interface, whereas the other side connection 100 - is shown as a message level interface. 100” = 100 b * 100
A series of host computers, designated as c and 100d, connect a connection line 15, designated as the MLI line.
(15a, b.

o, d), each of which is connected to a distribution card as described in the above-mentioned patents incorporated herein by reference. The connection module 106a includes 20a, 20b, 2
Shown with support for four distribution cards designated 00 and 20d. These distribution control cards (DC) are
These distributed control cards, which define the connection-disconnection functionality of any host computer system to a particular network support processor, are described in the above-mentioned patents.

On the other side of the network in FIG. 1A, a connection module 106b is shown that supports a distribution card, shown as a typical distribution card DC20. This distribution card 20 includes 300a, 300b, 3000 and 3
Provides controlled connection and disconnection to at least four line support processors, denoted 00d. Each of the line support processors connects to a block labeled "Electrical Interface" which may consist of up to 16 line adapters. Electrical interface equipment
400a, 400b, 400c and 400d.

25- As shown in Figure 1A, each host computer:
It can be configured with up to four connection modules similar to 106a, thus further extending the continuity of the network.

As stated in the above-mentioned patents, the main host computer operates on a routine basis, thereby
10 commands are sent to the front end 10 processor for execution, where the front end processor sends "result descriptor" words back to the main computer to indicate task completion or any exceptional conditions. The network support processor communicates with the host computer system at the "message level." This transfer process frees the host computer from much of the overhead required to support a data communications network. NA
P receives messages from the host system, translates them if necessary, and uses an appropriate data communication protocol to transmit the messages to the host computer & the desired data communication device after the tsumugi descriptor has been returned. 26- to ensure that it is sent.

If it happens that a message cannot be sent, the network support processor maintains integrity by ensuring that the message is not lost. This is done by temporarily storing the message and returning the appropriate result descriptor word to the main host computer.

Messages coming from a data communications network definition language are edited and translated, if necessary, and the edited messages are then placed in a queue so that transmission of the message does not occur until the host computer indicates a request to send the message. is started when

Referring to FIG. 1B, the hardware orientation of the network support processor is shown as consisting of nine to twelve cards. Base module device 106 is a housing facility for slide-in connector cards. - All in all, distribution card DC20
can be seen, and in perfect order can be seen a maintenance card 2o- having the features described in the above-mentioned patents. The network support processor 8o is in a dual-processor manner and includes a processor 50a and an NDL (Network Definition Language) designated as an MLf state machine.
It will be seen that the second processor 50b is shown as a state machine, and each of these processors has a memory control card shown as 66a and 66b.

The MLI state machine processor 50a is
interface card 1051, which connects the message level interface to line support processor 3.
It has a foreplane cable 105p connected to 00. ms to and from the host system is
via the backplane of the base module 106 and via the distribution card 20. A series of RAM circuit cards provides a "shared memory" facility and is shown as element 90.

Thus, the network support processor in the hardware configuration includes two processor cards, each of which has a universal input/output state machine (L
IIO8M). Each of these processors has a separate memory control card (MEMCTL) shown as 66a and 66b. Interface card 1051 (Figure 1B) then provides an external data link interface and a message level interface (DLI/MLI).

Additionally, 4 to 7 RAM to provide shared memory
There is a card 90.

FIG. 2 shows a block diagram of a network support processor, state machine cards 50a and 50b are
The same card, but shown as the ML state machine (master processor) and the NDL state machine (slave processor). The only difference between the two processor cards is the included jumpers and FROM.

Each processor card has a 1629-bit processor element with 32 bytes FROM in addition to various control registers.

The master processor or MLI state machine 5Qa is
Along with its associated microcode, it is responsible for communication with the host computer via the interface card 105:. Master processor 50a communicates with slave processor 50b (NDL state machine) via shared memory 90 and control line 661.

The slave processor 50b (NDL state machine) and its microcode are installed in the host computer 100.
is the source of all NSP messages exchanged with Additionally, the general programs required for interfacing to line support processor 300 are executed by the NDL state machine. Each memory control (MEM
CTL) cards 66a and 66b are “CI-IAz
” Contains 16 bytes of RAM memory, however, only the processor associated with a particular memory card has access to its local memory.

The memory control card (either 30- of 66a or 66b) also has logic circuitry that allows the associated processor to override access to the shared memory 90 on the RAM card of FIG. 1B. MLI memory control card 6
The logic provided on 6a acts to resolve right processor memory access conflicts. This card also. Has programmable speed generator and interval timer.

Shared memory 90 in FIG. 2 is comprised of RAM cards each having 32 bytes. This memory is divided by two (mask and slap) processors on state machine cards 50a and 50b. Access to "shared memory" 90 is controlled by memory control cards 66a and 66b.

Interface card 1051 (described below with reference to FIG. 8) contains logic used to interface with host computer 100 and line support processor (LSP) 300 cabinet. The interface card 105 has a part called DLI, or a data link interface for mutual exchange between the distribution card 20 and the host computer 100.

The Inter 7 Ace Card 1051 is also a message level Inter 7! 20, through which it connects to a distribution card, such as 20, and also to a line support processor 300. In addition to these external interfaces, the Inter7Ace card 105I includes logic circuitry for device clearing, interrupt request handling, and master clock control (8 MHz) for all network support processors.

As shown in FIG. 3, each processor of the NAP's dual processors communicates via three buses. (1) There are 10 paths 10, a memory address bus 16 (MADDR), and a memory data bus 12 (MEMOUT).

The I10 bus 10 is written to the host computer's main memory or to the state machine processor (50a,
50b) register cabinet or memory control card 6
6a, 66b and interface card 1051
ME, which carries the data to be transferred in the upper register cabinet
The MOUT bus 12 transfers information retrieved from memory (shared memory 90). This information may be executable instructions or memory operands or data.

Memory address bus MADDR16 indicates the current memory word to be written or read.

As shown in Ill2III, the NSP dual master slave processor system consists of two parts: an MLI processing part and an MDL processing part.

L l processing minutes: Referring to Figure 2, N8
The MLI processing part of P80 is master processor 5
0a (MLI state machine), an ML1 memory card 66a, and an interface card 1051.

, the processor has RAM in addition to the memory system @66a and the RAM stored on the card in the system 33-ad memory 90.
Driven by ROM. MLI state machine master 50a determines the type of host data transmission to be coupled and also controls the ML of interface card 1051.
Controls data transfer of line support processors via I port 105p. The MLI processing portion of the NSP is connected to the slave processor 50 via a shared memory 90.
b (NDL state machine). Inter 7I
The card 1051 has a FROM that allows the card to interface the M11 state machine to the host computer 100 in a high level mode. Interface card 105I handles the details of the actual data transfer.

N Processin: As shown in Figure 2, N
The DL processing part is the NDL memory card 66.
The state machine PROM (Program Memory) consists of a Slave Processor 534-Ob (NDL State Machine) driven by local memory located above B or driven by data from the Shared RAM Memory 90-a Network Support Processor is initially Once configured, it has a bootstrap that loads program information from the host computer into local memory (on the memory control card) and into shared RAM. This program then
to drive.

The NDL processing part is line support processor 3.
One communication providing communication with 00 is an interface card 1051 under the control of MLI state machine 50a.
This is done via the shared memory 90. Data transfer to and from line support processor 300 is controlled by direct memory access (DMA) logic circuitry located in Inter7I card 1051 (also shown in FIG. 7 and its description). This DMA logic operates under the control of MLI state machine 50a.

When MLI state machine 50a has a block of data for LSP 300, the data is placed in shared memory 90. NDL state machine 50b
notifies the MLI state machine 50a by an interrupt signal that the LSP is available. MLI50
The a state machine then connects the LSP3 from the shared memory 90 to the interface card 1051 via a message level interface channel 1051).
Instruct the data to be transferred to 00. Similarly, the line support processor 300
0b, the data is M
It is located in shared memory 90 under the control of LI state machine 50a.

MLI state machine 50a then signals NDL state machine 50b by an interrupt signal that line support processor data is available for trial use.

Network Support Processor Memory: A network support processor (NSP) contains two basic forms of memory: programmable read-only memory (FROM) and random access memory (RAM).
), the FROM configuration of the MLI state machine is configured to hold 8 bytes, while the NDL state machine is configured to hold 2 bytes. FROM is accessible only to the processor state machine in which it is located.

Each memory control card 66a and 66b has 18 bytes of local RAM that is accessible only to the associated state machine processor. Shared RAM memory 90, on the other hand, is available for either of the two processor state machines.

During the memory access operation, clock (8 MHz) periods are extended to yield proper memory timing. All memory write operations require three clock periods. All FROM and local memory read operations require one clock period, whereas shared memory 37-read operations require two clock periods.

Universal Input/State Machine: The main functional elements of the universal input/output state machine card are illustrated, as shown in 3rd m. Both the master processor state machine and slave processor state machine cards are logically identical. Each card is
It has processing logic that controls the sequence of operations for the network support processors. The processing aim includes memory addressing logic 1141, program memory FROM 50, and data manipulation logic 32.
33 and 34, an instruction execution logic 23, and an external bus logic 60L. Processing logic interfaces the state machine to other circuits in the network support processor.

Memory Addressing: A processor state machine memory addressing circuit is shown in FIG. The addressing logic consists of a program counter (PC>41), a memory reference register (MRR) 40, a stack memory 45, and repeat counters 38-42. PO 41 and MRR 40 are used as memory address pointers.

PO41 indicates the current instruction or operands for that instruction. When each instruction is executed, PO21
Automatically increments and then directs the next command. The instructions reside either in state machine FROM 50 or in local memory 66--or shared memory 90 in FIG.

Memory reference register (MRR) 40 indicates that the operand address is PC+1 (incremented program counter 41
) is used to store the address of the next operand. For example, when a program must examine the contents of a word of data, MRR 40 is loaded with the address of the data word.

This causes any of a variety of state machine instructions to be executed using this data word as an operand.

Repetition counter 42 is a register that allows an operation to be repeated up to 256 times. A repeat counter 42 is loaded with a value between 0 and 255 and is decremented with each returned operation. When the repeat counter underflows (i.e. has a value less than 0), the repeat operation
and the next instruction is fetched. The address source of the memory operand (which is MRR 40 or PO 41) is automatically incremented on each execution of the repeated operation. Stack memory 45 is used to hold the current program address when a subroutine is called, and then used to store that address again when the subroutine exits with a "return" instruction. Stack memory 45 can hold any address of 16, providing storage for 16 nested subroutines.

FROM: The FROM 50 used in the processor state machine is an 8 byte storage element in the preferred embodiment.

5, a block diagram of the data manipulation logic of the UIO state machine processor is shown. This data manipulation logic (represented by element 30)
6 general purpose accumulators and 31 operand registers
, an arithmetic logic MA unit (ALU) 32 , a byte-swap circuit 34 , and a shift logic IIB path 33 . The accumulator 16 pit registers of accumulator 30 are used to store information for operations and are used to hold the results of various operations.

Operand register 31 holds the operand of the current instruction. The ALU 32 is an operand register 31
and receives data from accumulator 30. Various logic and manipulation operations are performed based on that data, as described in the above-mentioned patents. AL
U32 is byte swap theory ma path 34 and shift theory WI
An output is given to the l path 33.

The byte swap logic output is used to replace the sequential order of byte sequences provided by ALU 32. Byte Swirler 41 - In pink, the most significant byte of the ALU output is replaced by the least significant byte, and similarly the least significant byte is replaced by the most significant byte in sequential order.

Shift logic circuit 33 can be used to shift or invert the ALU output to the left or right. Also, the shift logic WIl path can transfer the ALLI output directly and unaltered.

:u to mem, UIo state master A block diagram of the instruction execution logic of the synchronized processor is shown below.

The instruction execution logic circuit consists of an instruction register 22, a FROM instruction decoder set, and a latching register for the FROM output of element 23. instruction register 2
2 holds the current state machine instruction. This current instruction is FROM5 in that state machine.
0 or from either local 66- or shared memory 9°. Instruction decoder RPOM
23 is addressed by the instruction register 22. F.R.
OM 23 decodes the instructions into 40 different control signals that control the operation of the state machine processor (eg, chip enable, counting control, etc.). The output of decoder RPOM 23 is latched by a register if timing or signal stability is required.

Outside” luster! - Referring to FIG. 7, the main external bus of the state machine processor 2 is the interface card 105.
1 and memory control card 66. These buses extending outward to the state machine card 2 are the ■10 bus 10 and the memory address bus (MADDR).
) 16 and memory data out bus (MEMOUT) 1
2 and the put/get enable mat 609Gl.

As shown in FIG. 7, memory address bus 16# and I10 bus 10 also have their own local memory 661.
is connected to the memory 11311 card 66 that holds the . Memory data out bus 12 can also receive data from memory control card 66 along bus extension 12'. Memory 11311 card 66 has a data bus and an address bus to shared memory 90. I10 buses 10 and 10' connect local memory 6
6- and shared memory 90. The I10 bus 10 is also used to return instructions and data to the state machine processor card 2.

The memory address for MADDR path 16 is (a)
Occurs either in the state machine processor card 2 or in the other (b) interface card 1051. State machine 2 addresses either local memory 66-, shared memory 90, or FROM 50 (FIG. 4). The interface card addresses local or shared memory for direct memory access (DMA) only. It will be seen from FIG. 2 of these applications that two control registers 37, 38 are mentioned in the aforementioned patents which include a universal I10 state machine processor and which are hereby incorporated by reference. are called application IIJIII registers and are used to store information for logic external to the state machine processor 2. These application control registers are unique in that they receive data generated in state machine processor 2, but the data in the control registers is clocked by signals generated in cards other than state machine 2.

In FIG. 7, the interface card 1051 is
Data link interface (DL I ) to host computer 100 and line support processor 30
Message Level Interface to 0 (ML I
). Furthermore, the interface card has an interrupt line and interrupt recognition between itself and the state machine card 2. Memory control card 6
6 also has a control line 661 for exchanging signals with the NDL processor 50b.

Inter 7! Chair card: Interface card 10
The main elements of 5I are shown in the diagram of FIG. 8. A distribution card 20a connects to a data link interface 1!100i via a data link interface (DLr).

The distribution card 20 connects to the ML1 via the bus 105E).
Connect to 1100 So. MLI memory system-card 66a
connects to message level interface logic 100- by buses 16 and 12. A message level interface (MLI) state machine processor 50a connects the D
LI logic 1001 and PROM sequencer 100ps and M
LI theory 11100m! I will wear it.

Interface card 1051 provides a data link interface (FIG. 7) between host computer system 100 and network support processor;
and it also includes a network support processor and a line support processor ('L8P') that it controls.
) is provided with a message level interface (Fig. 7). 8-46 = To summarize the figure, the interface card has an ML1 part 100-, a DL1 part 1001, and a FROM sequencer 1oops. As shown in FIG. 1B, the interface card communicates with other N88 circuits via the foreplane connector.

Message Level Interface Wlooo: Data transfer between the network support processor (N-8P) 80 and any individual line support processor (LSP) 300 is performed by standard MLI logic 100 on the interface card 1051. .

This is Figure 7.

As shown in FIGS. 8 and 9. This data transfer performed is either in DMA mode or non-DMA mode.

In DMA mode, the DMA address counter is initialized by MLI state machine 50a as a "pointer" to the first word in memory to be transferred. At the same time, the transfer counter is updated to the state machine processor 50 with the complement of the number of words to be transferred.
It is initialized by a. DMA logic handles data transfers without further intervention by state machine processor 50a. As each word is transferred, the DMA address counter is incremented and the DMA "transfer counter" is decremented. The DMA operation then normally completes when the DMA "transfer counter" overflows, eg, when its value is "0". DMA logic, e.g. DMA timeout or unexpected L
DMA mode is exited when an abnormal condition such as an AMP status signal is detected.

All direct memory access operations (DMA) are
It is initialized by the MLI state machine processor 50a and controlled by the DMAllPROM. D
During MA operation, the clock to the state machine processor is disabled and the clock to the state machine PUT register, GE
The T register and I10 bus are disabled.

Left"11LΔjL:"Mi" - In non-DMA mode,
The data is stored in a line support processor (LSP) 300 (
Specifically, the selected LSPs 300a, 3oob,
aooc or 300d) word by word.

In this non-DMA mode, data transfers are performed under direct control of MLI state machine processor 50a. Data is transferred from the I10 bus 10 to a holding register (FIG. 9) and then to the 18P300 via the MLI circuit 100 of the interface card 1051. .

Message level interface logic 100 is shown in the block diagram of FIG.

DMA register 120 receives data along a fast foreplane memory bus carried to transmitter TX and from there to receiver RX and to state machine processor card 50a. Line support processor 300 connects to connection module 106b via DLI and to electrical interface El (line adapter) via MLI logic lines to receiver RX. State 49--The machine processor 50a receives the DM via the ■10 bus 10.
A address register 160 and holding data register 60! III. address register 160
The output of is conveyed via memory address bus 16 to memory control card 66 and state machine 50a.

12 link interface logic (DLLLLIl)
loIIl is the data link interface theory 118111 first shown in FIG. 8 as l1111001.
FIG. This data link interface logic WIII is the DL1 circuit associated with the MLI state machine processor 50a of FIG. In the first oaa, first-in, first-out FIFO) stack register 1
0013 is shown. This is a 64 word register with 16 pits in each word. This register holds data to be transferred to the host computer 100 or otherwise received from the host computer. 3-state driver-receiver 11m1
10011 sends and receives data to and from the combination 50-user 100 via the backplane. It also receives data on the internal data bus.

Other sources of data include the three-state driver receiver 10
The memory control card 66a has a foreplane connection to 015. This 3-state driver receiver 100
15 connects via an internal data bus to a holding register 10012, which provides input to a stack register 10013. stack register 10
The output of 013 is the 3-state driver receiver 10015
and 10011.
Sent to 014.

FROM sequencer: FROM sequencer 100ps
is shown in a block related to the eighth all interface card 1051. This FROM sequencer is designed to relieve state machine processor 50a from the overhead operations required to perform standard DL summer operations directed to the host computer system. The logic path in the FROM sequencer is designed to provide and follow standard MLI protocols for host system data transfer. The FROM sequencer receives a starting FROM address from a starting address register that is initialized by the state machine processor. This FROM sequencer then generates a series of -
- Step through the states and provide control signals to perform the necessary data transfer operations.

Sequencing continues until the FROM sequencer completes its assigned task or until an unexpected condition is detected. The state machine processor is notified of the unexpected condition by an interrupt signal and a status register signal.

The status register specifies the reason for the interrupt.

Memory Card MCL Network support processors 80&t, memory control cards 66a and 66 as described above with respect to FIG.
tl, and each of these control cards has two state machines (
50a, 50b) Prose, associated with certain of the saccades. A block diagram of the basic elements of the memory control card drawer 6 is shown in FIG.

111II, the memory control card 66
gives 8 a word of local memory.

This local memory is for exclusive use by its associated state machine processor, i.e. the memory control card 66a is for the exclusive use of the MLI processor 50a, and the other Memory control card 86b is exclusive for use by NDL processor 50b. The memory-based card also contains logic circuitry that allows a particular state machine processor to address up to 132K words of shared memory 90.The actual shared memory provided in network support processor 80 is N.S.
Limited to 115 words due to P software limitations. Communication with other cards in the network support processor is through the foreplane connector shown in FIG.

53- Maintenance card signal (PRI) shown in Figure 11
F, D81M, M^INT, 5EL) are described in the above-mentioned patents, which are hereby incorporated by reference.

As shown in FIG. 11, the memory control cards in each case include an MLI memory control card 66a with an added module selection logic mgi shown in one break.
They are the same except that they have *.

Only the module selection logic within the dots of the memory control card (66a) is required. This is because one of the state machine cards is the master processor (50a), whereas the other state machine card is the master processor (50a).

This is because the NDL processor 50b is a slave processor. Thus, the module selection logic distinguishes master processor cards from slave processor cards and is selected when each card is capable of using shared memory 90.

Memory address bus 16 from state machine processor
is the arithmetic theory 1! to logic memory 861! The data output is sent to the ALU 66u, and is also sent to the address selection register 66s, which register 668 receives the data output from the ALU 66u.
The ALU 66u provides a memory address that is sent to the shared memory 9o for access. The simulated test signal from the maintenance card 20- also has an output carried to the base address register 66' sent from the ALU 66u and the local Memory 6 rows may be gated.

I10 bus 10 sends data into base address register 66r, to local memory 66-, and to data bus 10db.

Local Memory: The local memory 66 of a memory control card 66 (Figure 11) contains 8.192 bits of RAM for the particular state machine processor associated with that card.
Gives 17 pit words.

This RAM memory receives address information from memory address bus 16 and also receives input data from I10 bus 10. Data output from the local memory 66 is connected to the common memory data out bus, MEMOUT.
via l2.

Shared Memory: The shared memory "control" portion of the memory control card 66 includes circuitry that allows the addressing capabilities of the state machine processor to extend to 131 words. The logic circuit is the MAP generator FROM
(1% Il not shown) and 16 base address registers (
BAR) 66r and 17 Pitt Arithmetic Theory I! Scissors holder (ALU)
It consists of 66u.

The MAP generator is a 32x8 PROM that decodes the top four pits of memory addresses on bus 16. This decoding determines whether the share tome 90 should be addressed.

The base address register (BAR) 66 is divided equally into two groups of 8 BARs. In this way, 16
- These base address registers are: One group of these (BARO-BAR7) is used when shared memory 90 is addressed by state machine program counter 41. The other group of base address registers < BAR8-BARI
5) is used when shared memory is addressed by the memory reference register (MRR) 40 of the state machine processor.

If any of the base address registers 66r are loaded by software via the I10 foreplane bus 10 and they are
Specifies the base address surrounding the area. ALU
The base address register output to 66Ll is selected by decoding state machine memory address bus control line 16. This decoding selects one group of eight base address registers.

By decoding the three upper memory addresses <14:03), one of the eight base address registers in that particular group is selected.

(ALU): Memory control card 6 The ALU66tl of 6 is a 17 pit adder.

Six inputs are drawn from the base address register, 57
- and the B input is pulled from the memory bus 16.

Data output is a shared memory address bus (XMAD)
H). The 16-bit base address register is set to 1 at pit position 16:14 of the arithmetic logic 11@@A input.
There will be 4 pits (15:14). Bit positions @0 and 1 are grounded. 16-pit memory address bus (M
ADDR) 18 is the pit position 12 of the arithmetic logic unit B input.
12 pits (11:12) will be set up at 11:12. The pit position 16:05 will be grounded. The ALU output, which is the sum of the top 14 pits of the selected base address register and the bottom 12 pits of the memory address bus 16, is the 17-pit shared memory address XMADR, which selects one of the words at 115. .

MEMORY WAIT R: Under certain conditions, the memory control card 66 stops the series of state machine clocks connected to the memory control card. This clock is stopped whenever WA_ITl@ is "active". One of the WAIT conditions occurs when a memory control card 58--drawer 6 is written into or read from shared memory 9o. Since the shared memory is too slow to keep up with the faster operation of the ST1~machine processor and memory control card, the memory control card inserts an appropriate WAIT signal to provide an appropriate delay.

Another condition occurs when both memory control cards 66a and 88b attempt to access the same shared memory card 9o at the same time. Priority generation II (PRIG
EN) FROM or MLI memory 1m card 66
a resolves the conflict and generates the appropriate WAIT state.

A third condition occurs when the state machine processor detects a memory parity error. The WAIT signal resulting from a memory parity error is "ungated", i.e. it does not pass, as per WA I 761:
There is up to 1R where the state machine clock is stopped until the state machine is clear.

ffl friend:'L In Figure 12, in Figure 1B. RA indicated by 90
A schematic diagram of an M card is shown.

Each of the cards has a 32 KB document for use as a contributor to shared memory 90.

The complete memory capacity of RAM 90 is divided between two state machines 50a (MLI) and 50b (NDL). As shown in Figure 1B, its capabilities are:
It can be provided in any of 4 to 7 RAM cards.

One particular arrangement of the shared memory RAM card is that it has termination registers for the shared memory address lines and for the memory out (MEMOLIT) bus. It is unique in that it is This particular card is called a RAMII card and is 32KB
Denoted as RAM TER. The termination RAM card must be located at the end of the memory bus in the network support processor.

The RAM card contains 68 4096x IRAM chips, each card has one data and one 7 dressing port (Figure 12) connected to the MLI memory control card 66a, and the second The data and addressing ports are connected to NDL memory control card 66b. This allows shared memory to be accessed by any of the state machine processors. 3. Communication with the memory control card. done via a foreplane connector.

As shown in FIG. 12, the addresses from the memory control cards of the ML state machine and the NDL state machine are B port 90ab and A port 90ab, respectively.
0aa and then for example 90. R like
Connected to the AM card address input. The data from the first and second state machines (master 50a and slave 50b) in the incoming data pulses are sent to ports Bdl and Adl, from where they are at the data inputs of card 90. The data output of the RAM card 90+ is sent into ports Bd2 and Ad2, and
1- From there they are sent on data lines to the MLI state machine memory control and NDL state machine memory control respectively.

Aspects of the Network Support Processor The integration of the various AMs of the network support processor is done using a bus and consists of three bus links, as shown in FIG. These links are MLI links, N
These are DL link and INTER link. These links allow the combination of cards that make up the network support processor to function in a unified manner as an overall device.

Network support processor <NSP> 80 is essentially a multiprocessor computer.

One processor (denoted as MLI control-) is designated as ML! It consists of a state machine card 50a, an MLI memory card 66a, and an interface card 1051.

(NDLllllI150b,!: し T 6 6) The second processor is the NDL state machine card 50b6
2- and NDL memory controller 6b.

- Both of these processor controllers are configured in the same manner and both have access to shared memory 90.

The three main buses that carry information and addresses through the various cards (Figure 13) are the f10 bus 10, the memory address (MADDR) bus 16, and the memory data out bus (Figure 13).
MEMOLIT) 12. Additionally, additional control information is sent to each controller's card cabinet by a foreplane connector (shown in FIG. 1B).

As shown in No. 1311, the MLI link
Iljllll's three cards (105i, 66a.

50a). It also provides connectivity for MLI equipment and shared memory 90 cabinets.

An NDL link connects cards 86b and 50b. INVER links connect shared memory 90 to 66a and 66b.

Enter / (Ilo bus: I10 bus 10a is
This is a common data bus that connects the three cards of MLIIljllll-. Information on this bus includes:

(a) From MLI state machine 50a to Inter 7
Control information for the Eighth Card 1051.

(b) Control information from state machine 50a to MLI memory control card 66a.

(0) Status information from the interface card to the state machine.

(d,) Interface FIFO register (first
Data received from the host computer 100 on the DLI is stored in the DLI (FIG. 0) and then sent to either a state machine or memory 90.

(.) Data from either the state machine or memory sent to the Inter7Ace card 1051 for storage in FIFO registers for subsequent transmission to the host computer via the DLI.

(f) receiving from LSP 300 on MLI and state machine, memory 90 or D in non-DMA mode;
Data sent to any of the memories 90 in MA mode.

(0) Data from either state machine 50a or memory 90 sent to interface card 1051 in non-DMA mode for transmission to line support processor 300 on the MLI.

(h) Data from state machine 50a to be written to local 66 or I address memory 90.

Memory Address MADDR Bus: Memory address bus 16a is a common address bus connecting three -III cards for the MLI controller consisting of cards 50a, 66a and 1051. The following information is sent on memory address bus 16a.

(a) State machine program counter 41 output (or memory reference register 40 output) during addressing
Output) FROM [III on state machine 50a or local memory 66-0 on memory control card 66a 65- (11) Inter7 used to address local memory 66- on memory control card (MEMCTL) 66 DMA address register (9111th) on the Eighth Card 1051.

(0) Address module selection logic (FIG. 11) on memory control card 66a to address shared memory 90 and base address register (BAR6).
6) MLI interface (911th
) on the DMA address register 160 or state machine MRR 40 output or program counter 41 output, the module selection logic of FIG. used for.

Memory address bus 16b is used as a common address bus connecting the NDL controllers (state machine card 50b and memory w4w66b).

Here, the following information data is transferred on the bus 66- sent.

(a) For addressing local memory 66- on memory control card 66b or NDLPROM 5
Program counter 41 output (or M
RR40 output).

(b) N to transfer information to logical and base address register, BAR 66r (FIG. 11) on memory control card 66b to address shared memory 90;
Program counter 41 output (or MRR 40 output) of the DL state machine.

Memory bus MEMOLIT): Memory output bus 1
2a is MLI system-1 3 cards (50a, 66
a, 1051). The information on this bus consists of:

(a) Either the DMA register 120 (FIG. 9) or the state machine 50a (for program information or data) on the interface card 1051 for transmission of data to the line support processor (LSP) via a message level interface. Output of local memory 66- on memory control card 66a to

(b) Output of the shared memory 90 to the state machine 50a or Inter 7 Ace card 1051 and LSP 300.

(o) Output of local memory 66- on memo 911w card 66a to transfer either program information or data to MLI state machine 50a.

(d) Output of shared memory 90 transferring information to NDL state machine 50b.

Similarly, MEMOLJT path 12b provides similar functionality to NDL state machine 50b (1311th).

Memory Interface: The MLI memory control card 66a uses a base address register (BAR>
and the memory address (MADDR).

The MEMC:TL card 66a also handles a bidirectional shared memory data bus 10a that transfers write data to shared memory 90 and returns read data from shared memory 90. Write data is provided by one 110 path 10a of the MLI link. The read data is transferred to the memory out bus 1211 of the MLI link in FIG. 13 via an isolator.

NDL memory card 66b has a base address register (BAR) that is programmed to generate a shared memory address that selects a memory word from memory 90.
) and the memory address. Memory-card 66b also handles a bidirectional shared memory data bus that transfers read data to shared memory 90 and returns read data from shared memory 90. Write data is provided by the NDL link's I10 bus 10b. Read data is sent 69- through the memory out bus 12b hair isolator of the NDL link.

NDL Link: The NDL link shown at 13I11 connects to two cards of NDLIIIIIIB consisting of 50b and 66b. This link also includes NDLM
III and shared memory 90 connections are also provided.

NP interleaving: MLI control III (card 50
a, 66a and tF1051) and NDLI13mm
111 (forces 50b and 66b) and the only “
Data" communication is done via shared memory 90.

The MLIII control communicates with shared memory 90 via a shared memory interface in the MLI link. The MLI link illustrated in item 1311 is connected to the three cards of the ML1 controller and is also connected to the controller with shared memory 90. Similarly, NDLI
l-1 communicates with shared memory 90. Each RAM card (No. 1211) in the shared memory 90 has separate ports, two (ML I and ND
L)-70- has its own boat selection logic for each shared memory interface W8MS.

The port selection logic (FIG. 12) is controlled by signals generated on the MLI memory control card 66a. Control flags (FIG. 13) are sent to the two memory control cards 66a and 66b to control access to memory 90. These flags determine when the MLI control requires access to the shared memory 90.
I-link port is selected. If not, ND
L link boat is activated.

The same RAM card 90 has MLI control and NDII
JIjli cannot be accessed by both at the same time. A logical WIL path on MLI memory control card 66a prevents this simultaneous access. However, the two true RAM cards in shared memory 90 that are being accessed at the same time have the same RAM.
Unless it is an AM card, it is accessed simultaneously by MLI and NDL control wW.

+++ 5% 1st 31st
As mentioned in sections 1 through 1.e.m., the state machine processor operates in either a "foreground" or "background" mode. Foreground mode is used for normal operation and can be interrupted by signals from interface card 1051. Background mode is used when the state machine performs "external" interrupts.

When in background mode, the state machine cannot be interrupted again until it is first returned to foreground mode by the program.

The logic to 5611 those two modes is 8-7.
The accumulator consists of 16 accumulators assigned to each mode, a flag register assigned to each mode, and one MRR save register 47 that holds the contents of MRR 40 when the state machine is switched from foreground to background mode. 14th W
As shown in A, the foreground accumulator is indicated at 30t, whereas the background accumulator is indicated at 30b. The foreground flag register is indicated at 35, while the background flag register is indicated at 36, and the MRR save register is indicated at 47.

When a state machine operating in "foreground" mode detects an interrupt, the state machine's status is saved. First, the contents of program counter PC 41 are saved in stack memory 45, second, program counter 41 is loaded at the address provided by the source of the interrupt (interface card 1051), and third, foreground accumulator 301 is fourth, the background accumulator 30b is enabled;
foreground flag register 35 is disabled and background flag register 36 is enabled;
And fifth, MRR40RAM card save register 4
7 (FIG. 14) at 73-.

In this way, the pre-loaded state of the state machine is stored unchanged for future use.

A state machine can execute interrupt service routines. The state machine status is stored again by reversing the status save procedure after interrupt servicing is complete. The firmware routine that was in process when the external interrupt was detected resumes execution at the point where the interrupt occurred.

In the network support processor (NSP), M
Only LI state machine 50a is interruptible.

The interrupt is placed in the FROM sequencer 1051 where it requires the help of a state machine to determine the 0th order step to occur in the interface card 1051.
When an ops is hooked, an interrupt occurs. This location includes the complete transmission of the message to the host computer 100 and the complete reception of the message from the host computer.

74-Interface card 1051 forces MLI state machine to address 0002. This address is
Hold branch to interrupt service routine.

Among the first instructions in this routine is an instruction to retrieve the contents of interface card status register 200.

This information is used to determine the appropriate response to the interrupt signal.

Two flag registers 35 and 36 are seven pit registers on the state machine that determine whether to perform a conditional branch operation and perform a conditional call or return, or whether to call or return to a subroutine. It is.

There are two sets of pits in the flag register. One set of three pits is the "external" flag.

This set is used to receive data that is external to the card. The second set consists of 4 pits. This set holds the state of the slow ALU output of the dominant arithmetic operation. These pits indicate that the full ALυ output is O
(states of ml upper and lower ALU output pits) and whether or not it is the state of ALLI "carry" output.

The state machine includes a background-foreground control flip-flop (fourteenth
11). This flip 70 tube is NSP I
When pressed, it is automatically set to foreground mode. It is set to background mode by an external interrupt. While flip-flop 70 is in background mode, no further interrupts are allowed; the flip-flop is reset to foreground mode at the beginning of the interrupt service routine. A new interrupt is then acknowledged.

The state machine can hide two program interrupt instructions:

(1) Instruction for disabling interrupts.

(2) Interrupt detection - command for work.

These instructions are independent of the presence or absence of external interrupts. The 0 interrupt instruction protects areas of the program from external interrupts. In FIG. 14, FROM sequencer 100
NSP interrupt logic is shown where ps is initiated by the starting address from the PUT instruction.

Memory Arresting: As shown in FIG.
, 66b) and MLI11 Goki (50a, '66a
) The main elements of N5P80 will be explained.

There are three main types of memory on a network support processor:

(a) Each state machine card has a FROM that holds portions of the state machine program. In FIG. 15, the NLI state machine 50a has 8K FROM 5 for storage of its programs.
Similarly, the NDL state machine 5
0b is FROM5 for storage of that program with word 77-
0n.

(b) Each Memory III (MEMCTL) card comprises a portion of the state machine program and local memory for each state machine. For example, in FIG. 15, MIL memory control 66a is shown having 16 word RAMs 66- for its local memory, and similarly, NDL memory control 66b is shown having 16 word RAMs 66-- for its local memory.
Each memory control card in FIG. 15 has its own local memory 661 including K RAM and
It also includes FROM, which contains part of the state machine program and is part of the local memory 66-.

(0) Memory 90 in FIG. 15 (and FIG. 1B) is a series of RAM cards each having a capacity of 32 kilobytes. These RAM cards can hold parts of the program for both the state machines, and they can be accessed by either the τ state machines by their associated memory control cards. Gives Airt Memory 90.

A state machine can have as many as 16 program words in FROM memory. In the preferred embodiment, MLI state machine 50a has program words at 8 and NDL state machine 50a has program words at 8.
b has a program of words in 2. Each memory control card has eight words of local memory available to the associated state machine. The number of words in shared memory 90 varies with the number of RAM cards installed in the network support processor shown in FIG. 1B. Shared memory is addressed by either state machine.

If there are 4 cards, as in the example of the preferred embodiment shown in FIG. 1B, the shared memory will be 65.
Given 536 words and 131.072 bytes, if there are 5 RAM cards, the shared memory is 81.9
Equipped with 20 words and 163°840 bytes, 6 R
For an AM card, the shared memory is 98.304 words and 196°808 bytes; for 7 RAM cards, the shared memory is 114.688 words and 22
It is 9.376 bytes.

FROM and Local Memory: FROM memory and local RAM are divided into blocks of four words for addressing purposes. FROM consists of four addressable blocks: FROMO, PROM 1. PR
OM2. PROM Divided into 3 parts. Not all FROM addresses are necessarily used. The local RAM is divided into two addressable blocks: RAM0-4 and RAM4-8K.

FROM or local RAM is located at memory address MA
Only 16 bits are directly addressed from the DDR bus 16. The most significant pit (15:4) on the memory address bus is used to select a block of four words.

The word within that block is then selected by the 12- least significant pit (11:12).

Shared memory address processing: (memory address bus)
The top 16 bits address up to 64 words.

Since network support processors have up to 162 words of memory, a way to extend the basic address range is needed.

In the 11th wJ, the memory control card includes logic circuits (66s, 66r, 66u) for the translation of 16-pit memory addresses to 17-pit "shared memory" addresses.
). This logic circuit consists of 16 base address registers (BAR66r) and a 17-pit ALU66u. The BAR is preloaded by software with the base address provided to the input of ALU 66u. The lowest twelve pits of memory address bus 16 are provided to eight inputs. These two values are summed together in the ALU to provide a 17-pit address to shared memory 90. Fourteen base address registers (BARs) are used and they can be preloaded by base address control software. The BAR addresses and obtains all areas of shared memory. However, this is done with two addressing controls as described below.

(a) The base address loaded into the BAR is '
, must be a factor of 4 since the lowest BAR input to the ALU is forced low.

(b) The base address is the share address provided.
4 memory blocks within the limit of 90.

ALU66Ll is 17 pits wide and BA
Since R is 16 bits wide, the BAR input to the ALU must be offset by one pit.
1! In other words, the BAR pit 15 is provided to the ALU pit 16. As a result of this offset, the shared memory base address is twice the absolute value held in the BAR. Extra pit to ALU (
Pit - 〇) is grounded. ALL from BAR
Pit-1 to J is also grounded to prevent timing failure on the shared memory board.

The base address register 82 (BAR) of the memory control (FIG. 11) is loaded by the I10 bus 10 from the date machine by the PLIT 5 TROBE 1 instruction. As an example of this, the following PUT command is exemplified.

PLJT XVVV XX0Onnn nnn
nnn nno.

Here, the It is.

The specific base address register BAR (66r) is
selected for addressing by a combination of memory address bus 16 and MRR output enable signals (<15:04). When the memory address is retrieved from the program counter, PC41, the MRR output enable signal is sent! (MRROE) is "false" and its pit selection is from BARO to BAR7.

If the memory address is taken out from the MRR 40 (FIG. 4), the MRR output enable signal is true, and the pit selection is BAR8 to BAR15. 15:04 Base address register access as a function of - One note: BAR6 is not used.

Table 1 below shows base address register selection as a function of MRR40.

85-Direct--L Memory Standard Addressing The 17- address pits provided to the shared memory 90 are divided into three groups. One group (
16:03) is one of eight possible RAM cards.
used to select one. The second group (13
:12) is used to select one of the four word blocks within the selected page. A third group 86-(01:02) is used to select one of the four pages on the selected card.

Program Arrest: The program FROM 50 located on each state machine holds the first 16K of memory addresses. However, only that portion of FROM containing program information is stored in the program counter, PC41 or memory reference register, MRR40.
directly addressed by either. As mentioned above, the MLI state machine has -8 words of FROM, while the NDL state machine has -8 words of FROM in the preferred embodiment of the network support processor.
It has ROM.

1 plate! What provides the data communication capability to the Network Support Processor (NSP) is 'firmware'. 'Firmware' is the instructions stored in the program FROM 50, and firmware is 'software IA in hardware form'. The stored instructions cause the hardware to execute as a front-end communications processor.

Within host computer 100, NSP communications are handled by an MCP (mask control program) routine known as DCC or data communication control. A separate host computer DCC routine exists for each and its NSP in the data communications subsystem, designated as 100at or input/output data communications subsystem. The DCC initiates messages to the Network Support Processor (NSP) and receives messages from the N8P.''The message is a vertical parity word (LPW) that checks the validity of the message content.
This is the block of information before.

Overconfidence is handled by messages called 'requests' and 'results'. The messages (indicated on the faceplate) are appended as data components of the I10 descriptor word. Request messages are handled by messages called 'requests' and 'results'. When started, host computer 1
Sent from 00 to NSP. GET the result message
Message I10 Descriptor is Sent from NSP to Host Computer When Initiated In both cases, a result descriptor is sent from the NSP to the host computer that describes the particular I10100 result. The result descriptor is the same “result message” as shown in table
isn't it.

89- Host computers and network support processors (NSPs) use eight different message formats as shown in Table 1.

I10 descriptors are commands from host computer 100 that instruct N5P80 to perform certain operations. This command is followed by a descriptor link (D/L) which is used as a “job identifier”, the ship identifier is:
Information is transferred as a result of the I10 descriptor and returns to the host computer at the beginning of each period in which the descriptor link initially follows 90-. The result descriptor is a message that describes the result of the I10 descriptor cycle. Result descriptor and descriptor link and I
The 10 descriptors were discussed and explained in the above cited patent wheel, which is incorporated by reference.

The remaining five message types are data transfers performed in response to various types of I10 descriptors.

Three specific message formats are 1. C0DE FILE (code file): 2. DUMP FILE: 3. NAP 5TATE (NSP state).

is shown.

Code file messages transfer firmware data from the host computer to the network support processor. Dump file messages are used to dump portions of NSP memory to the host computer. NSP state messages are used to report the current state of the network support processor to the host computer.

All remaining messages are ``requests'' or ``results''
It is a message. Valid messages are shown in Table V and ■
is shown in the following. In those tables, message codes not shown are not used and II SEQUENT messages are sent as the data portion of the 5END message operation. The result message is returned to the host computer as the data portion of the GET message operation.

The ADD GROUP message adds one group of subsystems. The group is stage gin set l! It's Mari. A station set line is defined as a set of stages that can be jointly and physically received. Each stage group is associated with a unique stage set.

Each stage set is associated with only one group. Thus, when a group is given to a subsystem, the entire collection of station sets and the stage date in each station set is given to the system.

i Table V Request message code Message format Meaning 01 A d
d Controller Adds the line control processor code file to the subsystem.

02 oe+ete C0ntrOII@r70 Remove the line control process after the process is no longer used.

03 Add Editor Add editor code file to subrestem.

Q 4 [) 5tate E dltor
Remove an editor from a subsystem when the editor is no longer 93- or no longer in use.

05 Add GrouEl Crew 7
Add to trs7 system.

06 Delete Group Crew 7
The associated station set, station run, and line are removed from the subsystem.

07 Add Line Adds a line to the subsystem and activates the line control process for the line.

08 Delete Line Delete a line from the subsystem.

09 Add 5tatlon Add a station to the bale subsystem with the corresponding stage 94- version set added.

OA Delete 5tatlon Removes a station from the subsystem after it is no longer used.

OB A dd S tatlonset Adds a static lance set to the host system to which the corresponding group has been added.

OCD delete S tatlonset Removes the station lance set and appropriate station from the subsystem after each station is no longer used, and removes the station lance set after all stage items have been removed.

OD A dd TransIatel
Subsystem Chimney Translation Table Add a translation table.

OE Dellet6 T ranstate
Table Chihaya Table Remove the Tawara translation table that is no longer used.

OF C1ear Adapter yVtotfi5i>7 Clear adapter armware.

10 D ulp A adapter Dumps the line data area in the line adapter.

111 n1tlallze Adall)te11
'Initialize the line adapter.

12 Te5t Adapter Test line aftano state.

13 Ack 5tation Su? - recognize receipt of a system input result message;

14 Chanae 8 talon Previous Add EdltOE ditor
Change the station editor to the editor loaded in the NSP by the r request message.

15 Make S tatlon station NOT RE ADY at 7Net Ready 7-Muraea.

16 Place the Maka Stalon station in the Ready armware and make it READY.

17 0tltptlt Send output message to station.

18 C1ear LSP Sends selective CLEAR to LSP controlled by NSP.

19 S at A ttrlbute Specific f) 5i> Set the value of a certain parameter in a station or station serato.

IA S at External Serat the value of a specific node or line external variable.

1B Set Globa! siri o-
t<le x98- Set the value of the specific variable.

I C5tatus riot<hZrit! Requesting cutiptedes information or a specific line system - either a process, editor, group, station set, system run, translation table or certain value of a line.

JL Table ■ Request message code Message format Meaning 01 C1e
Ared 5tation Station has been cleared.

02 E rror Failed attempt to receive from or send to a station.

03 I nput Returns the input message received from the station.

04 Message [:dlt Sf-
s>f) E rror Restores tolerance for abnormal termination in the second editor activation.

05 Q output Status Acknowledges the station's output request when necessary.

06 *Puroed Outout Since the stage engine has been cleared, a request for purged Stysilane is output.

07 * Unprocessed Output
Since the station has been cleared, output the discarded stage familiarization request.

OF Llne 5usspended Main line>fM control process is stopped.

10 Line EOT Main line control process ends normally.

1 1 D un A adapter
D un A adapterRepl
y Returns line adapter data information for the line in response to the message.

12 T est A adapter T
est A adapter R61EllV
Returns status information for the line in response to messages.

13 Switched L In6 Returns information about changes in the status of a switched line.

14 A bnorral T 5rstnatto
nN8 Pt or L8P S--Process terminates abnormally.

15 Ack Request The request is processed normally.

16 Rejected Request*st A request rejected due to incorrect information or unsatisfied preconditions.

17 Dilated line m11
7o Seth, editor.

group, stay Jilinset, Su Translated by Teji Shonan table or la Inn as requested ms will be sent to ms.

102-18 5tatus ReDIV Returns status information in response to a status request.

19 un5uccassful I/O Returns information related to failed I10 attempts.

Note: The mark indicates that the result message is given only to the firmware and not to the hardware.

Within the network support processor, several firmware components work together to ensure communication between the host computer and the line support processor (LSP). These firmware components can be categorized as follows:

(a) Manager (b) Host-dependent port (HDP) control (C)
Executive (d) Editor (e) Line Control Process The host computer message level interface 15 (MLI) in FIG. 1A is used for communication between the host computer and the network support processor (NSP), and Processor message level interface 100s
(MLI) is used for communication between network support processors and line support processors (LSPs). FIG. 16 shows how separate firmware components are used to transfer information between the line support processor, network support processor, and host computer.

In FIG. 17, a firmware block diagram is shown illustrating where the relevant components are located and their relative sizes.

In the message transfer block diagram of FIG. 16, line support processor 300 is connected to network support processor 80 via message level interface 100-. N5P80 has execution firmware 80θX and line control process firmware 80+
cp and editor 80ed. N5P80
is connected to the host computer 10 via the host ML 115.
0, it is equipped with firmware DCC (Data Communication Control).

The firmware block diagram of FIG. 17 shows network support processor 80 as comprised of two controllers: an MLI controller and an MDL controller. Both of these controllers share memory 90.

The NDL controller has a 2K FROM on the state machine shown as bootstrap 80b, and also has a 32K FROM on the operating system kernel 80, shown as
Has AM.

The MLI controller is designated as Manager 80I11.
K PROMe available, ka") t tc HD P
It has 32K RAM indicated by control l80h. The Makiya 80 connects to the host computer 105 - computer ioo via the MLI 15 . HDP@1l180h is
Line support processor, MLlloo to LSP300
- Connect via.

MANAGER: The MANAGER (FIG. 17) is a software module that controls the communication between the NSP and the host computer across the message level interface ML1 15. It has MLI's lll1l and performs 110 operations. Most of the firmware code 80m is held in eight words of MLI state machine FROM, indicated at 50.

Seal "1" - Sting JLLHD P control (17th I11) is,
drives the network support processor and message level interface, and executive 80e
give an interface to The firmware to HDP control resides in the RAM portion of the memory (661) control card associated with a particular MLI state machine.

Executive: Executive (Figure 16) is NS
This is the 106- software module that performs most of the P data brokerage. That is 0LITPU
Process all request messages from the host computer except T-request messages. This particular message is sent over the line control process device W801. When the host computer requests a status result,
Executive is 0UTPUTI! 0 after the request is completed
LITPLJT ST^TU8 Returns result message. The executive sends result messages to the host computer in response to both previously received request messages and concurrent subsystem events.

The components that make up Executive 80ex are:
It is broadly classified as a permanent independent runner, an interpreter-1S-processor, and an operating system.

The firmware code for the executive 80ex resides in RAM 66m of NDL memory card 66b, and also as part of shared memory 9o. The remainder of the shared memory is allocated and allocated dynamically, such as activity in network requests.

A permanent independent runner performs handler functions for N5P80. These features are independent of network configuration and station type. The code for this standalone runner is loaded during initialization and resides in a fixed location in shared memory 90. There are three permanent stand-alone runners:

(a) HDP handler (b) I! request handler (c) Status handler The functionality of each handler is summarized below.

Danshi” Seo and Z Danpo: HDP handlers are N5P80 and L8P300 of the garden! 10100 and analyze each operation for I10 errors. It is I
HDP control 1ll()7-Muraair) for correct routing to line support processor 300 of lo. It receives all result descriptors from LSP 300 and analyzes them, and also
Reports the status of all N5P-LSP I10100 to 00.

/S>”5 The second request handler is the host computer 10
Process the request message queue from 0 and (OUTP
service all request messages (other than CIT request messages). 0UTPUT! ! The request message, if one is specified, is sent to the appropriate editor component, which is then sent to the appropriate station forwarding destination. The request handler receives unqueued request messages from the manager component 80-.

Status handler: The status handler is
The main function of this handler is to execute the !10100 for the HOP handler. Specifically, the status handler These I10100 tests,
and the correct status of the required line adapter in the LSP
It folds in. It uses this information to enable the 'HDP handler to complete the first 110 operations.

S-Process: An S-Process is a collection of user-defined code. Its capabilities are dependent on the configuration of the network and the type of station, and its code is
Defined by the NDL program for a particular network. Code for the S-processes is loaded separately into the executive 80eX to perform specific tasks for the network, and is deallocated when no longer needed. Execution of each 8-process requires an interpreter to be called. The interpreter allows code in the S-process to be executed by the NDL state machine 50b. Editing and line control functions are examples of typical S-processes. The scope of the S-process can be expanded 1111 by means of the editor and line control process 110--by ms.

Interpreter: An interpreter is a "temporary" standalone runner. The permanent standalone runner is a temporary standalone runner μ, which is called for each S-process that is activated and exists only as long as the S-process exists.

The interpreter translates the code contained in the S-process and provides an interface to the operating system team routines.

Operating system: Operating system support is provided to the network support processor in the form of two routines: (a) a kernel routine; (b) an auxiliary routine; A collection of routines or procedures that perform a single operating system task. For example, to acquire space in shared memory 90, G E T -S pao
A procedure called θ is activated, and a procedure called Foroet-space is activated to space the cutout. The kernel routines are organized into seven levels or subgroups to increase the modularity of the design. The NDL memory control card 66 is installed in the partition 80.
It is located in the high-speed RAM (66-) part of b.

&2f>2 Auxiliary routines are collections of routines or procedures that each provide a central subsystem function. These are for example Qlear-Adapter, C1e
ar-3talon #3 and Not1-cho V L
ine-like task and is coupled by procedures belonging to this group.

Editor: Editors are user-provided and user-defined routines within NDL programs.

It is used to manipulate the text portion of request and result messages according to the requirements of the particular terminal type in the data communications network.

The code for the editor resides in shared memory 90 as a collection of S-processes. in this way,
The code is taken from a user-written NDL program for the network, and it is dependent on the network configuration. The NDL compiler ensures the transformation of the editor into a collection of S-processes.

As specified by the NDL, the editor receives control from the executive component when a "request message" is sent to the terminal by the host computer.

This causes the editor to edit the text portion of the "request message". The collected messages then pass through the firmware line control process 80+CP and are sent to the terminal. A similar process occurs in the opposite direction when host input is received from the network. The editor receives control from the line 11w process and is capable of editing the text of the host input "Result Message".

Line Process: This firmware component 80+CD is also user-provided and user-defined in the NDL program. The line-process is
It handles both the line and all terminals connected to the 113-subsystem via that line. It is responsible for satisfying line protocols, handling error recovery, and other functions. For this component A'-F is the shared memory 9 of NSP 80 as a collection of S-processes.
Exists at 0. The S-process representing the line control process originates from the user-written NDL program for the network and is dependent on the network configuration. N.D.L.
The compiler ensures the transformation of the line control process into a collection of S-processes.

16th vAk: The line control process in J5 is activated for each line presented to the network, and is N as long as the line remains attached to the network.
Execute in SP 80. It receives requests messages from the executive component or from the editor component, if specified. In turn, it formats the INPUT “result message” and sends it to the host computer 100.
-i i 4- Send it to an executive or editor for submission to.

Line control process is NSP 80 and LSP
Primarily responsible for 300 communications.

This communication consists of messages called “signals” from NSP to LAP (Figure 116) and messages from LSP300 to N
A message called a "reply" to the SP 80 is used. Although communication between the host computer and the NSP cabinet is completely defined by the NSP firmware,
NSP and LSP 300 covert communication is defined by the user via the network NDL program.

A “signal” is a message created by a line control process and that is sent to LSP 300. Line support processor (LSP) 300 directs the signal to the appropriate destination within the network. A signal has the following two fields.

(a) Message dext, field (b)
The control field message text field consists of the text of the output request message from the host. The control information field consists of light route designations and other information as defined by the NDL program.

A “reply” is formed by NSP 300 and sent to line control process 80+OEl in network support processor 80.

“Reply” consists of the following two fields.

(a) Text field (b) Control information field The text field consists of the actual text that entered the network. The control information field that accompanies the text field is used by the line control process 80+O1) to properly process the text and send the text to the host computer 100.

Host computer network messages to the network are transmitted at host computer 100 . The message traverses the MLI and is sent as a "request" to network support processor 80 by a 5END message merge operation. If an editor is specified in the NDL program, the NSP can aggregate the text portion of the message. The edited message is prepared for sending to LSP 300. Preparation is done by reformatting the message into a signal under the control of the line control process firmware. The signal then
MLI for NSP 80 and LSP 300 cabinets
100- to line support processor 300.

Line support processor 300 receives the signal and directs it to the correct destination in the network.

The network support processor (LSP 300) from the network to the host computer receives text from the network and the network support processor (LSP 300)
format it into a reply message for transmission to NSP 80). When the network support processor receives a reply-117- message, it replaces the text portion with “
Reformat the input result message. The text portion is edited if an editor is specified. The edited "input result message" is then prepared for transmission to main store 100. The host computer 100 crosses the MLI from the NSP 80 to “
In order to receive an "input result message", a "GET message I10 descriptor" must be provided by the host computer 100.

? The -7k II translation table provides a mechanism for translating the EBCDIC character set used by the data communications subsystem into the character set used on a particular data communications line. These translation tables are commanded by the NDL program.

The Data Network I10 Data Communications Network (IODC) subsystem can interface up to 256 data communications lines to the host computer. This maximum configuration has four network support processors (NAPs) per host computer (as shown at 118 in FIG. 1A) and four line support processors (LSPs) per network support processor (NSP). , line support processor (L
This is done by interfacing 16 electrical interfaces (line adapters) for each SP.

The Burrows data communications protocol allows data communications@stomachs to be connected in series or parallel, so that each data communications line can service a large number of wheel loads (typically no more than 10). Logically, it is possible to install 256,011 data overconfidence devices in one host computer.

The limiting factors in the interface device are the throughput that can be adjusted and the software used. In the case of a 1ooc subsystem, the limiting factor is the line support processor (LSP) bandwidth. The LSP300 can process approximately 50 pits per second. A network support processor (NSP) is a 10
Can support up to 15 terminals, 96
Works with any mix representing a 00 port or equivalent workload. The exact number of terminals that can be accommodated depends on the average terminal throughput. This in turn depends on the average message length and the format of the data (keyboard or recorded) and acceptable response times, etc.

Line support processor 300 is a device consisting of several slide-in cards that can be installed within a base module. This device consists of a card for the UIO state machine processor and four line adapters formed into the card.
” and an interface card labeled MLI/LA, which represents the line adapter interface to the Message Level Inter 7I bus.

A data communication line adapter is basically a device that interfaces to a data communication line electrical interface on one hand and to a state machine processor (UIO-8M) on the other hand.The main function of this line adapter is to store byte information. Continuing pit information from or to byte information, providing timing, generating service requests, providing RAM memory storage, automatic call interface, or) providing connections to level changers and matching data communication lines. ξ.

The basic configuration of the byte unidirectional line adapter is
That is, it can be arranged in a 4-line adapter and a 1-line adapter. A line adapter is part of the line support processor 300, shares the same circuit board with the MLI, and is always needed regardless of the amount of communication lines being controlled by the line support processor. A 4-line adapter card includes 4-line adapters on one board. These boards are 121-slide-in boards that plug into the pace module backplane.

The line adapter card is a state machine processor (L
l 10-8M> by a front plane cable. Connection to the data communication line is made through an electrical interface board that connects to a line adapter. Connection into any combination on a 4-line adapter
There are different types of electrical interface boards at the exits to be used, thus only the electrical interface boards need to be modified depending on the electrical characteristics of the data communication line.

1 to 16-line adapters may be addressed by the state machine processor of the line support processor. Each line adapter is uniquely jumpered to identify its address.

Similar addressable components are included on the line adapter with which the state machine processor can communicate in the form of write/read data or "status" and for key control. The addressable components in the controller 122-in adapter are: (a) USART.

(b) timer, (c) autocall output, (d>autocall status, (e) component requester, (f) memory.

The USART (Universal Synchronous/Asynchronous Receiver/Transmitter) receives data bytes from the state machine processor and converts them into serial pits for transmission; it receives serial pit data and converts it into parallel data bytes. The device is initialized by writing into two control registers that specify the manner in which it operates. The various pits of the control register are specified as follows = (l) synchronous/asynchronous mode, (:1
) pits per character, (Ill) parity, (1v
) port speed; (v) transparent mode; (vi) echo mode. Thus, the combination of a line adapter card, a state machine processor card, and a line adapter interface card connects the backplane and frontplane connectors of the base module. form a line support processor connected to the network via. The data communication line adapter used here is LSP300
It is an application-dependent device controlled by a state machine processor. There are two basic types of line adapters available: (a) character oriented and (b) pit oriented.

Each of these may have electrical interfaces to various data communication lines.

One to sixteen line adapters may be serviced by one LSP state machine processor. Each line adapter has addressable components and can be serviced by a state machine processor with PUT or GET instructions. Components on a line adapter are, in some cases, serviced with one instruction or a series of instructions that provides sequential control to the components.

[Brief explanation of drawings]

FIG. 1A is a network block diagram of a data communications network using a network support processor. FIG. 1B is a diagram showing a mechanical configuration of a base connection module and a slide-in card that constitutes a network support processor. FIG. 2 is a block diagram of a card device that constitutes a network support processor. FIG. 3 is a block diagram showing the basic elements that make up the network support processor. FIG. 4 is a block diagram illustrating elements of the memory address logic of the state machine processor. FIG. 5 is a block diagram illustrating elements of the data manipulation logic of the state machine processor. FIG. 6 is a block diagram illustrating elements of instruction execution logic for a state machine processor. FIG. 7 is a block diagram illustrating the external bus connections of various elements of the network support processor. FIG. 8 is a block diagram showing the relationship of the interface circuit to the state machine processor. 125--FIG. 9 is a block diagram illustrating the message level interface logic of the interface circuit. FIG. 10 shows data link 8 (
FIG. 2 is a block diagram illustrating the interface logic. FIG. 11 is a block diagram showing the memory control circuit of the network support processor. FIG. 12 is a block diagram showing port connections to and from a RAM card of external shared memory means. FIG. 13 is a block diagram of the complete network support processor showing the path lines and links interconnecting to external host computers and external line communication processors. FIG. 14 is a block diagram illustrating a state machine processor in relation to an inter-7142 circuit for interrupt operations. 15th! g! 126 is a block diagram illustrating the location of various memory resources in elements of a network support processor. 1611 is a schematic block diagram illustrating the direction of message transfer between the host computer, network support processor, and line communication processor, as well as certain firmware packets used in the network support processor. FIG. 17 is a block diagram of the network support 70 processor showing certain firmware packets used in the mask and slap processors. In the figure, 100 is a host computer, 80 is a network support processor, 300 is a line support processor, 400 is an electrical interface, and 106 is a connection module. Patent applicant Burroughs Corporation! Ig127- Procedural amendment (method) 1. Indication of the case Patent Application No. 115323 of 1982 2. Name of the invention Data communication network 3. Person making the amendment Relationship to the case Patent applicant address Michigan, United States of America , Detroit Barrows Brace (no street address) Name Barrows Corporation Representative Walter Jay Williams 4 Agent address 2-3-9 Tenjinbashi, Kita-ku, Osaka Yachiyo Daiichi Pill Voluntary Correction 6, Amendment The drawing drawn in the subject drawing 7 and the content layer of the amendment is shown in the attached sheet. that's all

Claims (10)

[Claims] (1) a main host computer including a main processor and main memory; and a base connection module for housing and connecting a slide-in circuit card, the base module having: backplane connection means for providing electrical connections to the slide-in circuit card; and a slide-in circuit card for connecting to the backplane means, the slide-in circuit card having a distribution-gI circuit for connecting and disconnecting the slide-in circuit card to and from the main host computer. and a maintenance card that provides diagnostic and test signals to the slide-in circuit card and controls a network support process that executes data transfer commands from the main host computer and returns result messages to the host computer. the 70 processor system is provided on a slide-in card connected to the backplane connection means, the processor vJIllIl connects together a plurality of slide-in cards in the base connection module, and further comprising a frontplane connection means for connecting to a line communication processor, the line communication processor controlling a plurality of line adapters, each of said line adapters servicing a data communication line to a remote terminal; A data communication network, further comprising: a plurality of line adapters connected to a communication processor; and a data terminal connected to each of the line adapters via a data communication line. (2) the network support processor controller comprises: an interface circuit that provides a connection to the main host computer via the distribution--circuit card and in general provides a connection to the line overconfidence processor; and a mask controller. - a master processor for executing data transfer instructions and communicating with the main host computer via the interface card; and a master processor connected to the master processor and providing access to external shared memory means. a master memory control circuit; and means for connecting the master memory control circuit and the sleip memory control circuit for control and interrupt signals, the network support processor controller further comprising a sleip controller, and the sleip controller a sleip processor that performs data transfers to/from the line communication processor and sends ms messages to the main host computer; and a sleip memory control circuit connected to the sleip processor and providing access to external shared memory means. 2. The data communications network of claim 1, wherein said network support processor controller further comprises shared memory means connected to said master and said slaved memory control gls. (3) The master processor and the slave processor each have: an internal program memory; memory address logic for selecting an instruction from the internal program memory or the external shared memory; and an instruction for executing the selected instruction. execution logic; data manipulation logic for performing physical, logical, and bit shifting operations based on the data to be processed; and bus means, the bus means comprising: an I10 bus; a memory address bus; , a memory data output bus, each bus providing a connection between the interface circuit, the master processor and master memory control circuit, and the slave processor and slave memory circuit. The data communication network according to paragraph 2. (4) said memory address logic comprising: a program counter for selecting addresses from said internal program memory; and a memory reference register for selecting addresses from said external shared memory means, said memory reference register as a source of addresses. or the selection of the program counter is determined by a signal from the instruction execution logic. (5) When both a master and a slave memory control circuit simultaneously request access to the same area of the external shared memory means, the master memory control circuit determines whether the mask or the slave memory control circuit has access to the external shared memory means. 6. Should access to shared memory means be granted? 4. The data communications network of claim 3, comprising module selection logic for selecting s. (6) The master and slave memory control paths each include: local memory for exclusive use of the associated master/slape processor; and access logic for addressing any area of the external shared memory means. A data communication network of the IIm fourth tomb record software as claimed in the patent. (7) The access logic I1 circuit includes pace address register means, and the base address register means is configured such that the external shared memory means receives the output of the program register via the memory address bus. a first group of registers for use when being addressed; a first group of registers for use when said external shared memory means is addressed by an output of said memory reference register via said memory address bus; a second group, said access logic circuitry combining an address in a selected base address register with a current address in said memory address bus to provide an address to be accessed in said external shared memory means. 7. A data communications network as claimed in claim 6, further comprising means. (8) a plurality of main host computers each connected to a selected distribution control card in the base connection module via its own separate bus; and a first base connection providing a backplane and connecting a slide-in connector card; the am module;
The module provides network support processor control for selected ones of the main host computers.
a network support housing a plurality of distributed control slide-in connector cards operative to connect and disconnect to the device and connected to a selected one of the plurality of host computers via the distributed control cards; further comprising a processor controller, wherein the four-way work support processor control variable operates to receive a data transfer command from the main host computer and execute the data transfer command, and controls selected line support processors to be connected to separate buses. to the network support processor via
and an auxiliary distribution--a second base connection module for supporting a card i; and said auxiliary distribution--a plurality of line support processors for selective connection to cards; Each of said line support processors provides connections to a plurality of line adapters, further comprising a plurality of line adapters each servicing and controlling data transfer to a remote data terminal on a separate data communication line. network. (9) The network support processor controller includes: a master processor that controls data transfer to/from selected host computers via the interface circuit card; and a master processor that controls data transfer to/from selected host computers via the interface circuit card; a memory control 811I that provides access to said master processor, said slave processor and said interface circuit card to said master processor, said slave processor and said interface circuit card; and a shared memory connected to said memory system 11m1; 9- a restorage means and an interface circuit card, said interface circuit card for transferring data to/from a selected host computer or for transferring data to/from a selected Life Support 1 port processor; The claimed SW+8th software overconfidence network includes logic means for data transfer. (10) Each host computer includes means for generating an I10 descriptor data transfer command word for transmission to the network support processor; and a descriptor link word identifying a data transfer task for transmission to the network support processor. and means for generating a result descriptor for each data transfer task for transmission to the host computer to signal whether the data transfer task is complete or incomplete. 10. A data communication network according to claim 10, comprising means for generating a word.