JPS5835374B2 - Method for manufacturing hybrid integrated circuits - Google Patents

Method for manufacturing hybrid integrated circuits

Info

Publication number
JPS5835374B2
JPS5835374B2 JP52133328A JP13332877A JPS5835374B2 JP S5835374 B2 JPS5835374 B2 JP S5835374B2 JP 52133328 A JP52133328 A JP 52133328A JP 13332877 A JP13332877 A JP 13332877A JP S5835374 B2 JPS5835374 B2 JP S5835374B2
Authority
JP
Japan
Prior art keywords
hybrid integrated
integrated circuit
oxide film
manufacturing
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52133328A
Other languages
Japanese (ja)
Other versions
JPS5466460A (en
Inventor
武雄 近藤
勝利 内田
明 風見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP52133328A priority Critical patent/JPS5835374B2/en
Publication of JPS5466460A publication Critical patent/JPS5466460A/en
Publication of JPS5835374B2 publication Critical patent/JPS5835374B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Description

【発明の詳細な説明】 本発明は混成集積回路の製造方法に関する。[Detailed description of the invention] The present invention relates to a method of manufacturing a hybrid integrated circuit.

既に特公昭46−13234号公報でアルミニウム基板
の表面を陽極酸化して酸化膜を形成した混成集積回路基
板を提案した。
Japanese Patent Publication No. 46-13234 has already proposed a hybrid integrated circuit board in which an oxide film is formed by anodizing the surface of an aluminum substrate.

斯る混成集積回路基板は良熱伝導性であるため放熱性が
良く高出力の混成集積回路を実現できる。
Since such a hybrid integrated circuit board has good thermal conductivity, it is possible to realize a hybrid integrated circuit with good heat dissipation and high output.

しかし々から斯る基板の電気的な絶縁は主として酸化膜
に依存しているので、酸化膜にクラック(割れ)が発生
するとクラック内に水分あるいは半田付工程でフラック
スが侵入して基板上に形成された回路部品とアルミニウ
ム基板との間にリーク電流を発生させたり最悪の場合シ
ョートする危惧を有している。
However, the electrical insulation of such a board mainly depends on the oxide film, so if a crack occurs in the oxide film, moisture or flux from the soldering process may enter the crack and form on the board. There is a risk that a leakage current may be generated between the circuit components and the aluminum substrate, or in the worst case, a short circuit may occur.

本発明は端上した欠点に鑑みてなされ、絶縁性の良好な
混成集積回路の製造方法を提供することにある。
The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a method for manufacturing a hybrid integrated circuit with good insulation.

以下に図面を参照して本発明の一実施例を詳述する。An embodiment of the present invention will be described in detail below with reference to the drawings.

第1図に示す如くアルミニウム等の良熱伝導性の金属板
1の表面に陽極酸化により酸化膜2を形成した混成集積
回路基板3を準備する。
As shown in FIG. 1, a hybrid integrated circuit board 3 is prepared by forming an oxide film 2 on the surface of a metal plate 1 made of aluminum or the like with good thermal conductivity by anodizing.

酸化膜2例えばアルミナは金属板1との熱膨張率の違い
によってクラックが入り易い。
The oxide film 2, for example, alumina, is prone to cracking due to the difference in coefficient of thermal expansion between the oxide film 2 and the metal plate 1.

混成集積回路基板3の一主面には導電路とiる銅箔4が
接着され、銅箔4の表面には表面を保護するためにニッ
ケルメッキ層5が形成されている。
A copper foil 4 serving as a conductive path is bonded to one main surface of the hybrid integrated circuit board 3, and a nickel plating layer 5 is formed on the surface of the copper foil 4 to protect the surface.

斯る混成集積回路基板3は第2図に示す如く所定の導電
路を形成する如く銅箔4がエツチングされ、銅箔4上の
ニッケルメッキ層5も半田層よび導電塗料が付着される
部分が選択的に除去される。
In such a hybrid integrated circuit board 3, a copper foil 4 is etched to form a predetermined conductive path, as shown in FIG. Selectively removed.

続いて導電塗料および抵抗塗料が所定部分にスクリーン
印刷され、夫々の塗料は焼成されて導体6および抵抗体
7を形成する。
A conductive paint and a resistive paint are then screen printed onto the predetermined portions, and the respective paints are fired to form the conductor 6 and the resistor 7.

焼成は200℃6時間行なわれる。Firing is carried out at 200° C. for 6 hours.

この焼成工程で酸化膜2に最もクラック8が発生し易く
、これ以降の工程では斯る長時間々加熱工程はないので
更にクラックが新らたに発生することはない。
Cracks 8 are most likely to occur in the oxide film 2 during this firing step, and since there is no such long heating step in subsequent steps, new cracks will not occur.

またクラック8内の水分も本工程で除去できる。Moreover, the moisture inside the crack 8 can also be removed in this step.

本発明の特徴は第4図に示す如く酸化膜2に発生したク
ラック8にシリコンオイルの如き液状絶縁物9が含浸す
ることにある。
The feature of the present invention is that, as shown in FIG. 4, cracks 8 generated in the oxide film 2 are impregnated with a liquid insulating material 9 such as silicone oil.

前述したクラック8は極めて微小のものであるが、液状
の絶縁物9を用いることにより毛細管現象により容易に
クラツク8全体に注入することができ且つ注入した液状
絶縁物9をクラック8内に毛細管現象により固定できる
The crack 8 described above is extremely small, but by using the liquid insulator 9, it can be easily injected into the entire crack 8 by capillary action. It can be fixed by

斯る液状絶縁物9の含浸は第6図に示す如く常温で10
mHf程度の減圧容器20内に配置した液状絶縁物9の
入った器21に多数枚の混成集積回路基板3を2時間ぐ
らい浸して行々われる。
The impregnation with the liquid insulator 9 is carried out at room temperature for 10
This is carried out by immersing a large number of hybrid integrated circuit boards 3 in a container 21 containing liquid insulator 9 placed in a reduced pressure container 20 of about mHf for about two hours.

この真空含浸法に依ればクラック8内の空気が完全に排
斥でき、クラック8内に完全に液状絶縁物9を充填でき
る。
According to this vacuum impregnation method, the air within the crack 8 can be completely excluded, and the crack 8 can be completely filled with the liquid insulating material 9.

含浸工程の終了した混成集積回路基板3は表面に付着し
た液状絶縁物9を有機溶剤で洗浄して除去し、クラック
8内のみに毛細管現象により液状絶縁物9を残し固定す
る。
After the impregnation process has been completed, the hybrid integrated circuit board 3 is cleaned with an organic solvent to remove the liquid insulator 9 adhering to its surface, leaving the liquid insulator 9 only in the cracks 8 by capillary action and fixing it.

然る後第4図に示す如く銅箔4上に半田クリームをスク
リーン印刷し加熱して半田層10を付着する。
Thereafter, as shown in FIG. 4, solder cream is screen printed on the copper foil 4 and heated to adhere the solder layer 10.

この加熱により半田クリームに含1れるフラックスが飛
散するがクラック8内には液状絶縁物9があるため侵入
できない。
Due to this heating, the flux contained in the solder cream scatters, but cannot penetrate into the crack 8 because there is a liquid insulator 9 therein.

更に第5図に示す如く半田層10上にヒートシンク11
を介してトランジスタ12が固着され、トランジスタ1
2の電極からはリード細線13を超音波振動によってニ
ッケルメッキ層5上に固着して電気的接続が行なわれる
Further, as shown in FIG. 5, a heat sink 11 is placed on the solder layer 10.
Transistor 12 is fixed via
From the second electrode, a thin lead wire 13 is fixed onto the nickel plating layer 5 by ultrasonic vibration to establish an electrical connection.

以上に詳述した如く本発明に依れば、半田付着工程以前
にクラック内に液状絶縁物を含浸するのでフラックスが
クラック内に全く侵入せず極めて良好な絶縁性を得るこ
とができる。
As described in detail above, according to the present invention, since the crack is impregnated with a liquid insulator before the solder adhesion process, flux does not penetrate into the crack at all and extremely good insulation can be obtained.

また含浸工程を導体層よび抵抗体の焼成の後に行うこと
によりクラック内の水分を除去するとともにクラックを
予じめ発生させるので発生する全クラック内に液状絶縁
物を含浸でき完全な絶縁性が実現できる。
In addition, by performing the impregnation process after firing the conductor layer and resistor, water in the cracks is removed and cracks are generated in advance, allowing the liquid insulator to be impregnated into all cracks that occur, achieving complete insulation. can.

更に真空含浸法によりいかなる微細なりラック内に液状
絶縁物を完全に且つ容易に注入でき更に完全な絶縁性を
得ることができる。
Further, the vacuum impregnation method allows liquid insulation to be completely and easily injected into any microscopic rack, and more perfect insulation can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第5図は本発明を説明するための断面図、第
6図は本発明に用いた含浸方法を説明するための断面図
である。 1は金属板、2は酸化膜、3は混成集積回路基板、4は
銅箔、5はニッケルメッキ層、6は導体、7は抵抗体、
8はクラック、9は液状絶縁物、10は半田層、11は
ヒートシンク、12はトランジスタ、13はリード細線
である。
1 to 5 are cross-sectional views for explaining the present invention, and FIG. 6 is a cross-sectional view for explaining the impregnation method used in the present invention. 1 is a metal plate, 2 is an oxide film, 3 is a hybrid integrated circuit board, 4 is a copper foil, 5 is a nickel plating layer, 6 is a conductor, 7 is a resistor,
8 is a crack, 9 is a liquid insulator, 10 is a solder layer, 11 is a heat sink, 12 is a transistor, and 13 is a thin lead wire.

Claims (1)

【特許請求の範囲】 1 良熱伝導性金属板の表面に陽極酸化により酸化膜を
形成した混成集積回路基板を準備し該基板上に導体抵抗
体層よびトランジスタ等の回路部品を設ける混成集積回
路の製造方法の於いて、半田を付着する工程以前に前記
混成集積回路基板の前記酸化膜に以前の加熱工程で発生
したクラック内に液状絶縁物を含浸させることを特徴と
する混成集積回路の製造方法。 2 良熱伝導性金属板の表面に陽極酸化により酸化膜を
形成した混成集積回路基板を準備し該基板上に導体抵抗
体層よびトランジスタ等の回路部品を設ける混成集積回
路の製造方法に於いて、半田を付着する工程以前に前記
混成集積回路基板を液状絶縁物内に配置して減圧下で前
記酸化膜に以前の加熱工程で発生したクラック内に前記
液状物を含浸させることを特徴とする混成集積回路の製
造方法。 3 良熱伝導性金属板の表面に陽極酸化により酸化膜を
形成した混成集積回路基板を準備し該基板上に導体抵抗
体層よびトランジスタ等の回路部品を設ける混成集積回
路の製造方法に於いて、前記導体釦よび抵抗体の焼成工
程以後で半田を付着する工程以前に前記酸化膜に発生し
たクラック内に液状絶縁物を含浸させることを特徴とす
る混成集積回路の製造方法。 4 良熱伝導性金属板の表面に陽極酸化により酸化膜を
形成した混成集積回路基板を準備し該基板上に導体抵抗
体層よびトランジスタ等の回路部品を設ける混成集積回
路の製造方法に於いて、前記導体および抵抗体の焼成工
程以後で半田を付着する工程以前に前記混成集積回路基
板を液状絶縁物内に配置して減圧下で前記酸化膜に発生
したクラック内に前記液状絶縁物を含浸させることを特
徴とする混成集積回路の製造方法。
[Scope of Claims] 1. A hybrid integrated circuit in which a hybrid integrated circuit board is prepared by forming an oxide film by anodization on the surface of a metal plate with good thermal conductivity, and a conductive resistor layer and circuit components such as transistors are provided on the board. In the method of manufacturing a hybrid integrated circuit, the oxide film of the hybrid integrated circuit board is impregnated with a liquid insulating material into cracks generated in a previous heating step before the step of attaching solder. Method. 2. A method for manufacturing a hybrid integrated circuit in which a hybrid integrated circuit board is prepared by forming an oxide film on the surface of a metal plate with good thermal conductivity by anodization, and circuit components such as a conductive resistor layer and transistors are provided on the board. , the hybrid integrated circuit board is placed in a liquid insulator before the process of attaching solder, and the liquid substance is impregnated into the cracks generated in the oxide film during the previous heating process under reduced pressure. A method for manufacturing hybrid integrated circuits. 3. A method for manufacturing a hybrid integrated circuit, in which a hybrid integrated circuit board is prepared by forming an oxide film on the surface of a metal plate with good thermal conductivity by anodization, and circuit components such as a conductive resistor layer and transistors are provided on the board. A method for manufacturing a hybrid integrated circuit, comprising impregnating a liquid insulator into cracks generated in the oxide film after the step of firing the conductor button and the resistor and before the step of attaching solder. 4. A method for manufacturing a hybrid integrated circuit, in which a hybrid integrated circuit board is prepared by forming an oxide film by anodization on the surface of a metal plate with good thermal conductivity, and circuit components such as a conductive resistor layer and transistors are provided on the board. After the step of firing the conductor and resistor and before the step of attaching solder, the hybrid integrated circuit board is placed in a liquid insulator, and the cracks generated in the oxide film are impregnated with the liquid insulator under reduced pressure. A method for manufacturing a hybrid integrated circuit, characterized in that:
JP52133328A 1977-11-04 1977-11-04 Method for manufacturing hybrid integrated circuits Expired JPS5835374B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52133328A JPS5835374B2 (en) 1977-11-04 1977-11-04 Method for manufacturing hybrid integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52133328A JPS5835374B2 (en) 1977-11-04 1977-11-04 Method for manufacturing hybrid integrated circuits

Publications (2)

Publication Number Publication Date
JPS5466460A JPS5466460A (en) 1979-05-29
JPS5835374B2 true JPS5835374B2 (en) 1983-08-02

Family

ID=15102135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52133328A Expired JPS5835374B2 (en) 1977-11-04 1977-11-04 Method for manufacturing hybrid integrated circuits

Country Status (1)

Country Link
JP (1) JPS5835374B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4124824Y1 (en) * 1964-08-19 1966-12-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4124824Y1 (en) * 1964-08-19 1966-12-19

Also Published As

Publication number Publication date
JPS5466460A (en) 1979-05-29

Similar Documents

Publication Publication Date Title
US4617729A (en) Process for manufacturing miniaturized electronic power circuits
US6820798B1 (en) Method for producing circuit arrangments
JPS632159B2 (en)
JP2003289073A (en) Semiconductor device and method of manufacturing semiconductor device
JPH11345921A (en) Cooling device arranged on printed board and prepared for component of generating heat
US3414775A (en) Heat dissipating module assembly and method
EP0015053A1 (en) A method of manufacturing a semi-conductor power device assembly and an assembly thereby produced
JPS5835374B2 (en) Method for manufacturing hybrid integrated circuits
US3324362A (en) Electrical components formed by thin metallic form on solid substrates
US7417318B2 (en) Thick film circuit board, method of producing the same and integrated circuit device
JPS5835375B2 (en) Method for manufacturing hybrid integrated circuits
JP3243943B2 (en) Manufacturing method of ceramic electronic components
JP2000049056A (en) Solid-state electrolytic capacitor
JPS6153852B2 (en)
JPH03154395A (en) Circuit board and manufacture thereof
JPH08107257A (en) Manufacturing method of printed-wiring board having electromagnetic wave shield
JPH11214591A (en) Semiconductor device
JP2004048013A (en) Electronic unit and its manufacturing method
US3316459A (en) Hermetically sealed thin film module
JP2003163442A (en) Ceramic wiring board
JP3059689B2 (en) Manufacturing method of wiring board
JPH0636601Y2 (en) Circuit board
JPS5835376B2 (en) hybrid integrated circuit board
JPH0365651B2 (en)
JP2632151B2 (en) Manufacturing method of circuit block