JPS5834382A - Microprogram control circuit for timepiece - Google Patents

Abstract

PURPOSE:To reduce a load on hardware logic by speeding a test of operation of timepiece functions through software functions. CONSTITUTION:A beta-up timer 408 is set when a heavy load driving circuit 409 operates to turn on a lamp 410, and during the operation the value beta of an oscillator 401 is increased. The timer 408 uses the reset signal of a decimal counter 403 as a clock and when this clock is inputted twice, the timer 408 is reset. Therefore, during a test, the reset signal from a CPU407 to the decimal counter 403 is generated twice repeatedly to reset the timer 408, thereby executing a test program.

Description

[Detailed description of the invention] The present invention relates to a microprogram control circuit for a watch.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for effectively and efficiently testing a microprogram control circuit for a watch.

Electronic watches, especially digital display watches that use display elements such as liquid crystals, have many added functions. but,
As clock circuits become more multi-functional, the amount of data handled by clock circuits is increasing, and circuits are inevitably becoming more complex.

FIG. 1 is an example of a timepiece circuit with a conventional counter configuration. 101 is an oscillation circuit using a crystal oscillator or the like, 102 is a frequency dividing circuit, 103 is a time counter, 105, 107
．． 109 is a counter related to additional functions. For example 1
05 is a counter for counting alarm time, 104 is a counter control circuit, 107 is a stop watch counter, p, 106 is a counter control circuit, 10
9 is a timer counting counter J), 108 is the same counter 2
- counter control circuit. A multiplexer 110 multiplexes data signals from each counter and transfers the data signals to a display circuit 111.

As can be seen from this diagram, in a counter-configured timepiece circuit, as additional functions are added, the number of counters and their control circuits increases, making the circuit more complex.

For this reason, when electronic watches become multifunctional, cP
U (Central Processing Un)
A microprogram-controlled electronic clock circuit using a microprogram control system (IT) has been proposed. Figure 2 is an example.

Reference numeral 201 denotes a program storage circuit for storing microinstructions and a decoder unit for decoding instructions. The microinstructions 202 decoded by the decoder control data operations, transfers, and the like. 203 is a data storage circuit, which corresponds to the counter group in FIG. A method of configuring the data storage circuit f:xc is RAM (Random k
c, cesa Memory) is common. RAM
is designed for high density and has higher area efficiency compared to counters. 204 is an arithmetic circuit that performs various operations. 20
5 is a display section.

3- In the microprogramming control circuit shown in Figure 2, C
Once the circuit configuration of the PU section is established, adding functionality can be accomplished by simply increasing the capacity of the storage circuit section and changing the program. moreover,
Specifications can be easily changed, and a - number of circuits can be applied to many types of watches.

For the reasons mentioned above, microprogram control clock circuits have been proposed.

Even in this type of microprogram control circuit for tenses, there are -/- code timers. For example, when a heavy load circuit such as a lamp is operated, there are several timers, such as a timer that increases the β value of a MOS or F'ET that constitutes an inverter of a crystal oscillation circuit, and a timer that determines whether a switch input is ON or OFF. All of these timers measure time by modifying the appropriate output signal from the branch unit.

Conventionally, when testing time-opening electronic circuits, performing a function check with the timer in normal operation would greatly increase testing costs, so the circuit configuration was such that the timer function could be ignored during testing. Figure 3 shows that -
Give an example.

4- 301 and 302 are test terminals, and since there are usually many inputs, pull-down resistors 303 and 304 are used to set them at the "0" level.

Therefore, the specific signal from the frequency divider is input to the timer 306 via the composite gate 305.

During testing, 301 is set to the "1" level and 302
A high-speed clock is input from. The timer is
It operates at a higher speed than normal and does not interfere with the test time.In addition, the high-speed clock for fast forwarding is often input from the middle of the branch.

With the above circuit configuration, testing can be performed smoothly, but it is necessary to provide several test pads (depending on the number of fast-forward clock inputs), and the IC tester also
It was necessary to create test terminals and test programs corresponding to the above, and the deviation of η in design cost and inspection cost was also high.

According to the present invention, the test cost can be reduced by increasing the speed of the timer function operation during testing by incorporating it into a software function.

Hereinafter, an explanation will be given based on one embodiment of the present invention. FIG. 4 is a block diagram of one embodiment based on the present invention.

401 is an alarm circuit using a crystal oscillator or the like, 4°2 is a frequency dividing circuit, and 4o3 is an IHz counting counter. 403 is a type of counter that is reset when the counter code detection circuit 405 detects an IHz code. 4
07 is the CPU section (Central Processing).
g Unit). One of the microinstructions issued from the CPU section is sent to 403 through a 4o4 OR gate.
Reset the IHz formation counter of. If this command @
It is named Rs TC (Re5etCo1Lnter). By appropriately using the R8TC command, an IHz signal synchronized with the current time can be obtained.

In this circuit, the output of 404 and the reset signal of 4o3 are
It persists as a Hz signal.

408Jd The β value of the oscillator 401 is
-up timer, which is set to 6 and operates when the 4o9 heavy load drive circuit operates and the 410 lamp is lit. The output of 404 is input as a clock to a timer 408, and after measuring 1 to 2 seconds, the output is set to "0".

Therefore, when the heavy load circuit is in operation, the β-Wp timer operates for 1 to 2 seconds after the heavy load circuit finishes operating.

As can be seen from the figure, since 408 uses the output of 404 as a clock, the timer is canceled even if the Rs'rc command of 406 is issued twice in succession.

A detailed view of 403 to 405 and 408 is shown in FIG. 40
3 has a four-stage configuration of 502 to 505 binary 11 and 2 double flops, and counts 1 second. 4030
The input clock is a one-second signal, and the composite gate 508 detects the codes M (1010) to F (1111), sets the 8R latch consisting of the OR gates 506 and 507, and starts the counter 403. Set lj. That is, 403 operates as a decimal counter.

The 1 second signal is a reset signal of the floating counter 403, that is, the output of the OR gate 404.

The timer 7-408 is set when the heavy load circuit operates and the Load signal goes to the "1" level, and the βqt and p signals go to the "1" level. After 1 to 2 seconds of non-movement of the heavy load circuit, a "0" level is written in the timer 408, and βup is released.

Since the R8TC command signal is also input to the OR gate of 404, if the R8TC command is repeated twice, β will surely be
You can cancel the up state.

FIG. 6 shows a flow chart for transitioning to the test state. The system e-reset specifies the program start address. A transition is made to a test state, but whether a transition to a normal clock state is made is determined, for example, by taking a switch input immediately after a system reset. In the example in Figure 6,
It is identified by the input of K1 (first switch). If K1 manpower is available, perform the test routine. 60
3. Execute R13TC command of 604 and βup (?-
is canceled (the output is set to the "0" level), and the program shown in 605 is executed.

8- According to the present invention, the node timer can be easily canceled by software processing. Moreover, there is almost no burden on hard logic.

Therefore, the present invention is very useful.

[Brief explanation of the drawing]

Figure 1: A conventional clock circuit with a counter configuration Figure 2: A clock circuit using a microprogram control system Figure 3: Conventional circuit for canceling a timer circuit Figure 4:
Based on the present invention (Example of microprogram control circuit for a watch) Figure 5 - Detailed view of a portion of Figure 4 Figure 6 - Transition to test self-routine (D 7 C1-)
Chart example. Applicant Suwa Seikosha Co., Ltd. Attorney Mogami Patent Attorney 9- Procedural amendment (voluntary)] Case microprogram control circuit for display clock 3, person making amendment Relationship with the case Applicant Lost in Tokyo Ward Ginza 4-3, No. 4 (2563 I*i Kosei Kokai Co., Ltd. representative kIMti role Tsuneya Nakamura 4, agent

Claims (1)

[Claims] A reference signal generation source such as a crystal oscillator, and a CPU in which processing is executed according to a preset program. ■The reference signal generated from the reference signal generation source or the signal obtained by dividing the reference signal is counted, and is preset when a preset counter code is detected or by a specific microinstruction. Counter circuit with preset function. (2) A timer circuit that counts the preset signals of the counter circuit and measures time. 1. A microprogram control circuit for a watch, characterized in that the timer circuit is configured to include at least a continuous routine of the specific microinstructions A in a program, and is configured to execute the routine at high speed. 1-