JPS583424A - Resetting circuit - Google Patents

Abstract

PURPOSE:To assure resetting, by delivering a reset signal by making use of the difference between the rise time of the 1st power supply circuit and the rise time of the 2nd power supply circuit to which the output of the 1st power supply circuit is applied. CONSTITUTION:With application of a power supply, the output V1 of the 1st power supply circuit 2 has a rise. Then the output V1 is supplied to the 2nd power supply circuit 4 to be turned into an output V2. The output V2 is lower than the output V1 and has a rise more quickly than the output V1. A transistor TRQ31 is turned off when the base voltage of the TRQ31 does not reach the ON voltage of a Zener diode 2D31. Accordingly, the input of an inverter IC31 is at a low level, and as a result, the output of the inverter is equal to the output V2 which has already a rise. When the output V1 has a sufficient rise with the TRQ31 turned on, a relay T works with a contact (t) switched. Thus the output of the inverter IC31 is set at a low level, and no reset signal is delivered.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset circuit for easily and reliably operating a controlled circuit when a power source is connected or disconnected.

When considering a system that uses a central processing unit (CPU) to control relays, motors, etc., there is a difference between the rated voltage of the relays, motors, etc. and the rated voltage of the CPU, so there is a voltage difference within the system. There are multiple different power supply circuits. A conventional system reset circuit of this type utilizes the rising characteristics of the power supplied to the CPU to reset the CPU when the power is turned on. Here, since the start-up characteristics of the plurality of power supplies are different from those of the CPU power supply, there have been disadvantages such as arbitrary operation before the reset is applied and initial reset is not successful.

Figure 1 is a block diagram of a conventional system of this type.
Figures (a) and (b) are specific examples of a beam throat circuit.

In FIG. 1, 1 is a power input, 2 is a first power supply circuit,
3 is its output, 4 is the second power supply circuit, 5 is its output, 6
is a reset circuit, 7 is its output, 8 is a CPU circuit, 9.
10 is a circuit whose power source is the output 3 of the first power supply circuit 2, and 12 is a circuit whose power source is the output 5 of the second power supply circuit 4.

Circuits 8, 11, and 12 are circuits to be controlled, and the reset signal is used to reset and control these circuits to be controlled. Power is applied to the power supply input 1, the first power supply circuit 2 starts up, and the second power supply circuit 4 is activated by its output 3.
rises and its output 5 is sent to the reset circuit 6 and CPU
It is applied to the turntable 8. The reset circuit 6 outputs a reset signal 7 to the CPU circuit 8 for a certain period of time when the power is turned on.

FIGS. 5(a)' and 5(b) are circuits showing specific examples of the reset circuit 6 in particular detail, and 1 to 7 are the same as 1 to 7 in FIG. 1. Figure 5 (a) uses differential characteristics, and (b) uses integral characteristics. ◇ In (a), the output of the 5V power supply circuit 4 is differentiated by a differentiation circuit composed of C and R1, Two inverters IC1, IC2 and two resistors R
2+ R3 is added to the Nyumi Noto circuit. As a result, a positive reset pulse is output to the cuff when the 5V power supply output 5 rises. (The output of the integrating circuit composed of R11 and C11 is connected to an inverter IC.
, , a positive reset pulse is output to the cuff when the 5V power supply output 5 rises.

Due to this configuration, the following disadvantages have arisen. First, since the second power supply circuit 4 is driven by the first power supply circuit 2, its operation may become unstable when the power supply 1 is momentarily cut off. This is output 3 and output 5
This is because there is a time lag between the It may become unstable later than 3. This is because, although the circuit 12 continues to operate, the circuit 11 may stop operating.

Next, since the reset circuit 6 is driven by the same power source as the CPU circuit 8, the reset operation may be incomplete. Fifth
Figure (ω, (b) is an example of the set circuit used in the jinodane device, and Figures 8 (a) and (b) are explanations of the operation of Figures 5 (a) and (b), respectively. Figure 5.
To explain with reference to FIG. 8(a), the time t is as shown by ■ in FIG. 8(a).

If 5V starts to rise at t4 and becomes complete at t4,
The potential at the connection point of CIRI rises to V2 until tl, as shown by @, and becomes Ov at t3, resulting in a differential output. The fall of the Schmitt circuit changes the slip run-hold voltage on the horse mackerel side to 'T'.
When HL, the reset output cuff rises from to in the same way as in ■, and becomes an output O that drops to zero at t2 when the differential output O becomes equal to vTHL. Here, the voltage of O is 4 at its peak, but it has not reached 5V. For this reason, the resetting of the CPU circuit 8 is often incomplete. Also, 5v
If the time t4 until the voltage rises is longer than the differential constant τ=C1×R1, the differential output vP may not exceed VTHL, and the reset operation may not be possible. In addition, in FIG. 5(b), if 5V starts to rise at time to and becomes complete at t2, as shown in ■ in FIG. 8(b), then C
The charging potential of 1 is like @. At this time, inverter I
C! If the threshold voltage of , is VTR, this cuff rises from to in the same way as
When tl becomes equal to , the output O falls to Ov. Here, the voltage at O reaches VR at its peak, but does not reach 5V, so the reset operation of the KCPU circuit 8 may be incomplete.

In order to solve these drawbacks, the present invention provides a reset circuit configured to take into account the time differences in the rise and fall characteristics of a plurality of power supplies and to monitor voltage fluctuations of each power supply. 〇, The present invention will be explained in detail below with reference to the drawings.

The second tooth, FIGS. 3 and 4 are block diagrams showing embodiments of the present invention, and FIGS. 6, 7 and 9.

FIG. 10 is a waveform diagram for explaining the specific circuit example and operation of FIGS. 2, 3, and 4, respectively. Figures 2 and 3
In the figure, 1 is a power supply, 2 is a first power supply circuit, 3 is its output, 4 is a second power supply circuit, 5 is its output, 6 is a reset circuit, 7 is its output, 8 is a CPU circuit, 9.1
0 is its output, 11 is a circuit whose power source is the output 3 of the first power supply circuit 2, 12 is a circuit whose power source is the output 5 of the second power supply circuit 4, l3 is the reference voltage source, and 14 is its power source. Output, 1
5 is a voltage comparison circuit, 16 is its output, 17 is another power input terminal, and 18 is a delay circuit.

The operation of the embodiment shown in FIG. 2 will be explained. Power is applied to the power supply 1, the first power supply circuit 2 starts up, its output 3 causes the second power supply circuit 4 to start up, and its output 5 powers the CPU.
applied to circuit 8. The voltage comparator circuit 15 is a reference voltage source 1
3 is compared with output 14, and output 1 according to the difference.
Roll a 6. The reset circuit 6 is the output 1 of the voltage comparator circuit 15.
6, a reset signal 7 is output to the CPU circuit 8 in response to the reset signal 7.

FIG. 6 shows a specific example of the block diagram in FIG. 2, and FIG. 9 is a waveform diagram for explaining its operation. First, the power source is human power 1
If the output 3 of the first power supply circuit 2 which outputs 30V is applied to t like @. And stand up? Stable with tx. Here, when comparing the emitter potential η and the base potential VB of the transistor Q31, the emitter potential V0 becomes constant if the output voltage V of the first power supply circuit 2 exceeds the Zener potential v2 of the Zener diode ZD31 ■E=v2 0If we ignore the base current, then,
If the on-voltage between the base and emitter of transistor Q31 is vBE, then vB<vB, 10v.

At this time, transistor Qal is OFF, and relay T is restored. Next, when VB≧vBE−vE, Q31 is turned ON, and therefore relay T operates. Since the contact point t of the relay T is on the solid line side in the figure at the time of recovery, the input of the inverter circuit c31 becomes 'L' and the output becomes 'H'. When the T relay operates and falls to the dotted line side, after a time delay due to the integrating circuit formed by R33 and C31, the inverter circuit ICs+ is inverted and becomes "L". Furthermore, when the T relay is restored from its operating state, the charge in the capacitor C31 is rapidly discharged by the diode D32, so that the output of the inverter circuit IC3 becomes 'H' almost simultaneously with the contact operation.

Therefore, the recent output cuff has an output like O.

Because of this configuration, the reset operation is completely performed when the power is turned on. That is, at the point 1 when the output of the second power supply circuit 4 which outputs 5V is 0. is 30
Since the output ■ of the first power supply circuit 2 that outputs V is earlier than the time t4 when it becomes stable, if the voltage at which the transistor Q31 switches is VREF, the output ■ of 30V is reached.
The time t2 when becomes VREF) is t+ < h < ts
can be set. Therefore, the reset pulse 7 maintains 5■ at least from tl to t2, and R33.
After the charging time of C31 is delayed, the voltage becomes OV at t3, so that the reset can be completed completely. Next, in the case of a momentary power interruption, the output of 30V at ts in Figure 9 is
When Qsl starts to fall and becomes equal to vREF at ts, Qsl turns OFF K, so relay T is restored and, as described above, the reset pulse becomes H#. After that, when 30V begins to recover at tl and becomes equal to VREF at ts, transistor Q31 turns on and the T relay operates, so the reset pulse becomes 'L' at ts (C'2J'J). , Circuit 1 operates on a 30V power supply during a momentary power outage.
1 and the circuit 12 operating at 5V are all reset, so unstable operation will not occur.

FIG. 3 shows the output 5 of the second power supply circuit 4 as the reference voltage source 13 in FIG. 2, and a specific example thereof is shown in FIG. Its operation is similar to that shown in Figure 3, with transistor Q
The emitter potential v0 and base potential VB of 41 are as follows: η=v2. However, this is the forward voltage drop of the v dividing diode D41. Transistor Q41 has VB<V, -V, where the on-voltage between base and emitter is -VBE.
B.

It turns ON when VB'2vE-VBE, and turns OFF when VB'2vE-VBE, so when it is ON, the potential v2 appears at the output of the reset circuit 6, and when it is OFF, the potential ov appears. Therefore, the same effect as in FIG. 1 can be obtained. Furthermore, the configuration as shown in FIG. 3 has the effect of simplifying the circuit because there is no need to separately provide a reference voltage. ' In the above explanation, the second power supply circuit 4 is connected following the first power supply circuit 2, but if another power supply input terminal 17 is added so that both power supplies start up almost at the same time. As shown in FIG. 4 and FIG. 10 showing a specific example, the comparison circuit 1 is
This effect will not be lost if the delay circuit 18 is inserted into one side of the circuit 5. Furthermore, as mentioned in the explanation, there is also the advantage that the set voltage can be set arbitrarily by changing the ratio of the resistances.

FIG. 11 is a block diagram of a button telephone device as an application example of the present invention, where ME is a main device, ME is one of the telephones, L is a speech path, and D is a power and data path. In the main device, CO is the office line input terminal, COC is the office line circuit, IOC is the extension circuit, RC is the incoming signal detection circuit, and TO
NE is a sound source circuit, t is a L IJ relay contact, POW is a power input terminal, AvRl is a first power supply circuit, and CPU is a controller that operates as a central processing unit (control circuit) to be controlled.
PU circuit, T-POW is telephone power supply circuit, TR is data transmission/reception circuit, BU is power failure backup power supply circuit, L
R is the L IJ relay circuit, SD is the self-holding circuit of the relay during power outage, AVR2 is the second power supply circuit, RES is the reset circuit, and SW includes a mono-multivibrator for each input, which is used temporarily after the input arrives. A switch circuit that controls turning off the output to the telephone power supply circuit, L-DRIV
E is the drive circuit that drives the CPU circuit CPU0 output crab yori L relay, D is the diode, p is the contact of the P relay, H8I, H82 are the hook switches, NET is the communication circuit, R is the resistor, AMP is the amplifier circuit, SP is the speaker, AVR-T is the telephone power supply circuit, P-DRIVE is C
PU circuit A drive circuit that drives the P relay based on the output of the CPU, PR is the P relay circuit, and LK is the station line button.
, PK is a call button.

During operation, when power is input to the power input terminal POW, the first power supply circuit AVR1 rises and the second supply circuit T
- Power is supplied to POW. Second power supply circuit AVR2
supplies power to the reset circuit RES and the CPU circuit CPU.
Reset U. After resetting, the switch circuit SW operates the telephone power supply circuit T-POW, and power is supplied to the telephone set. After the reset operation, the CPU circuit CPU detects the operating state of the L relay from the self-holding circuit SD, and
If the L relay is self-holding, output is sent to L-DRIVE to operate the L relay. The standby relay is operating, its contact t is at the dotted line position, and the extension circuit I
Connected to OC. Data transmission and reception between the main device ME and each telephone device is carried out by [CPU circuit CPU-data transmission/reception circuit TR->data transmission/reception circuit TR->CPU
This is done bidirectionally along the path of the circuit (CPU). When power is supplied to the telephone device from the telephone power supply circuit T-POW, the telephone power supply circuit AVR-T operates and resets the CPU circuit CPU by the milli-reset circuit RES. During standby, the P relay is not operating, and the contact p of the P relay is on the hook switch side. If the telephone set goes off-hook, the telephone circuit NET is connected to the telephone line via the p contact and the hook switch H8, and is further connected to the extension circuit IOC via the contact t. By operating the call button PK, [call information of the CPU circuit CPU-data transmitting/receiving circuit TR, etc. is transmitted through the data path,
In the main device ME, the CPU circuit CPU sends a ringing tone to the communication path using the tone generator circuit TONE. Called telephone (In Figure 1, the telephone equipment shown is one of multiple identical ones connected, and to distinguish between the calling telephone and the called telephone, '' is added to the circuit name of the called telephone. ), the CPU circuit CPU' detects the called state, drives the drive circuit P-DRI', and connects the P relay circuit PR'.
At the same time, the amplifier circuit AMP' is brought into operation. As a result, the called telephone is connected to CP' IJ relay contact p' → resistor R' → amplifier circuit AMP' → speaker SP')
A ring tone is sent out. If the called telephone equipment' goes off-hook, the hook switch H8'2 causes the CPU to
Circuit CPU' restores P' relay and calls circuit NET'
is connected to the telephone call circuit NET' via the hook switch H8'1, and based on the information from the hook switch H8'2, the CPU circuit CPU of the main device stops the tone source circuit TONE, so that an extension telephone call state is established.

The other phones will recover and go into standby status.

An extension call goes into a standby state when both phones go off-hook.

When there is an incoming call on the central office line, the incoming call detection circuit RC operates.

As a result, the CPU circuit of the main device ME is connected to the sound source circuit T.
It drives ONE and transmits data on the state of incoming calls to the central office line to the telephone device. Since the CPU circuit CPU of the telephone device operates the P relay and the amplifier circuit AMP, the central office line ring tone is transmitted from each telephone 1 m away. By operating the central office line button LK and off-footer on the telephone device, the CPU circuit of the telephone device restores the P IJ Schiller amplifier circuit AMP, connects the telephone communication circuit NET to the telephone communication path, and transmits the central telephone selection data to the main device ME. Transmit. Main device ME C
The PU circuit CPLJ stops the tone source circuit TONE, restores the L relay, and connects its T contact to the station line circuit coc.
Turn to the side. Also, any telephone device other than the off-hook
Both the relay and amplifier circuit AMP are restored and are in standby mode.

With the above operations, the station-to-station state is established.

, When the call ends, the telephone device goes into a standby state due to the on-hook link, and this on-hook information causes the main unit to operate the L relay, whose T contact is connected to the extension circuit IOC side, and the telephone device goes into a standby state.

To select a central line when making a central line call, press the central line button L on the telephone device.
By operating K and turning OFF 7, the communication circuit NET is connected to the communication path through the hook switch H8l and the p contact. Since the main device ME restores the L relay based on the office line selection information, the contact connects the communication path to the office line circuit COO side, and the state becomes possible for office line transmission.

Button telephone devices include flashing lamp operation, dialing operation,
Although there are various functional operations such as a blocking operation and a transfer operation, they are not necessary for a detailed explanation of the present invention, so their description will be omitted.

As explained in detail above, the present invention operates the reset circuit by comparing multiple power supplies. This has the advantage of ensuring reliable sled reset and preventing unstable operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional device of this type, FIGS. 2, 3, and 4 are block diagrams of an embodiment of the device of the present invention.
5(a) and 5(b) are circuit diagrams showing a specific example of a conventional reset circuit, FIGS. 6 and 7 are circuit diagrams showing a specific embodiment of the device of the present invention, and FIG. a), Fig. 8(b) f
4 are waveform diagrams for explaining the operation of the actual phase example shown in FIGS. 5(a) and 5(b), respectively. FIG. 9 is a waveform diagram for explaining the operation of the embodiment of FIG. 6, and FIG. FIG. 11 is a block diagram showing an example of application of the present invention. Special Applicant: Iwasaki Tsushinki Co., Ltd., Telegraph and Telephone Public Corporation

Claims (3)

[Claims] (1) A first power supply circuit, a second power supply circuit, and the first power supply circuit.
a controlled target circuit that receives power supply current from the power supply circuit and the second power supply circuit, and the output voltage of the first power supply circuit as one input, and the other input as a reference voltage, and the voltage of the one input is and a voltage comparison circuit that outputs a positive signal to the controlled circuit when the reference voltage is exceeded. (2) Claim 1, characterized in that the reference voltage is extracted by 9 from the output voltage of the second power supply circuit.
Reset circuit described in section. (3) The reset circuit according to claim 1, further comprising a circuit having a linkage characteristic in a path of the one input of the voltage comparison circuit.