JPS5833861A - Lead frame for semiconductor - Google Patents

Lead frame for semiconductor

Info

Publication number
JPS5833861A
JPS5833861A JP13146681A JP13146681A JPS5833861A JP S5833861 A JPS5833861 A JP S5833861A JP 13146681 A JP13146681 A JP 13146681A JP 13146681 A JP13146681 A JP 13146681A JP S5833861 A JPS5833861 A JP S5833861A
Authority
JP
Japan
Prior art keywords
lead
leads
lead frame
patterns
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13146681A
Other languages
Japanese (ja)
Inventor
Ryuichi Kyomasu
隆一 京増
Yoshikazu Suzumura
鈴村 芳和
Isamu Yamazaki
勇 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP13146681A priority Critical patent/JPS5833861A/en
Publication of JPS5833861A publication Critical patent/JPS5833861A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To align the positions of a chip and leads by inserting the right and left external leads of a lead pattern between the external leads of adjacent lead patterns and inclining the lead patterns with respect to the profile line of the lead frame, thereby saving the material. CONSTITUTION:A plurality of lead patterns, each of which has a plurality of leads 2 and a profile unit 3 at a semiconductor element placing part 2 as a center, are continuously formed at a lead frame. The right and left external leads 5 of the lead patterns are inserted between the external leads 5' of the adjacent lead patterns. Further, the lead patterns are inclined at the prescribed angle theta with respect to the profile line 6 of the lead frame. As a result, the element placing parts 1, 1' of the respective lead patterns are disposed on linear lines parallel to the profile line 6 of the lead frame.

Description

【発明の詳細な説明】 本考案は複数個の反復パターンを有する半導体集積−路
装置(IC,LSI)用リード7レー^に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead 7 array for semiconductor integrated circuit devices (IC, LSI) having a plurality of repeating patterns.

従来、上記構造の半導体リードフレームは m品となる
部分の整数倍以上の長さが必要であった。
Conventionally, the length of a semiconductor lead frame having the above structure was required to be an integral multiple or more of the length of the part to be made into an m-product.

第1111に従電源リードフレームの11pl&−示す
。同図においてlは素子(チップ)載量部、2はこれを
堆り踊むリード、3は外郭部(7レーム)、4は境界部
である。このようなリードフレームは一枚の金属平II
Lを打抜い工連続したり一部フレームパターンを形成す
るものであるが、リードの外端部(外部リード)の近傍
で抜きしろが大きく、それだけ材料的にもむだが多い。
11pl&- of the 1111th slave power lead frame is shown. In the figure, 1 is an element (chip) mounting part, 2 is a lead extending over this part, 3 is an outer part (7 frames), and 4 is a boundary part. Such a lead frame is made of a single metal flat II
L is punched out continuously or a part of the frame pattern is formed, but the punching margin is large near the outer end of the lead (external lead), and there is a lot of wasted material.

そこで従来よりリードフレームパターンをずらせて隣り
合うリードフレームのリードな上下に重ねるよ5にする
ことでリードの閏の空白を少なくし、材料的に節減を図
る試みがなさrL″Cいる。
Therefore, conventionally, there has been no attempt to shift the lead frame patterns so that the leads of adjacent lead frames are stacked above and below each other, thereby reducing the gap between the leads and saving on materials.

例えば第xHに示すようにとなり合うリードフレームを
1/2ピツチづつずらして、リードの先瑠部分S、イを
互い罠入り込ませるリードフレーム構造、さらK、その
構造で113gに示すようにとなり合5チップ(IIP
導体素子)の位置が同じになるよう、となり会うリード
ブンニ五のパターンを変えてチップ及びリードフレーム
の位置を整え、ペレットポンディンダウワイヤポンディ
ング等の便宜なはかった構造がある。しかし、前述の改
良11によれば、第2図のものについては、隣接する亨
−ド7レー五のパターンが異なり、チップの堆り付は位
置も異なろため1組立工程の複雑化と。
For example, as shown in No. 5 chips (IIP
There are convenient structures, such as pellet bonding and dow wire bonding, in which the positions of the chip and lead frame are adjusted by changing the pattern of adjacent leads so that the positions of the conductive elements (conductor elements) are the same. However, according to the above-mentioned improvement 11, in the case of the one shown in FIG. 2, the patterns of adjacent wires 7 and 5 are different, and the positions of the chips are also different, which complicates the assembly process.

モールドm<レジンパッケージの場合)の形状波線化に
よる品質、IR備のメインテナンスの問題がある。又第
3閣のも〇につい【は、リードフレーム設針上のw約か
ら最嵐のリードパターンがとれない事、同一品lIK対
し2@のり−ドパターンが温布するため、品質を保つ事
が難しい岬の欠点がち番。
There are problems with the quality and maintenance of the IR equipment due to the wavy shape of the mold m<resin package. In addition, regarding the third cabinet, the most stormy lead pattern cannot be obtained from the w diameter on the lead frame setting needle, and the quality cannot be maintained because the 2@glued pattern is warm compared to the same product lIK. The disadvantage of the cape is that it is difficult to do so.

本尭−は上記した従来技術の欠点な取り除くためになさ
れたものであり、その目的はリードフレームの材料節減
tmるとと″もに在米の組立工@をそのまま適用でき、
均一で信頼性ある完成品が得られるリード7レー五t−
提供することに&る。
The present invention was made to eliminate the drawbacks of the above-mentioned conventional technology, and its purpose was to save materials for lead frames, and to make it possible for assembly workers in the United States to be applied as is.
Lead 7-ray 5-t- that produces uniform and reliable finished products
To provide &.

本発明の一実施例′に第4閣に示す。この実施例で示さ
nたリードフレームはII隣れる素子に対応するリード
パターンの左右の外部リード5は互いに隣りのリードパ
ターンの外部リード5の間に入りこむと同時に、各リー
ドパターンがリードフレームの外郭線6に対してそれぞ
れ所定角度(#)傾くように形成されているものであり
、これにより各素子に対応するリードパターンの素子載
量S1.1がリードフレームの外郭線に平行な直線上に
配置されるようになっている。なお互いに入りこんだ外
部リードはリードパターンでは第51!11に示すよう
にその先端部が相手のリードの基部に接続された形状と
し、素子ごとにリードフレームを分割する際に同図の一
点鎖線で示す位置から切り離すようにしてもよい。
An embodiment of the present invention is shown in the fourth panel. In the lead frame shown in this embodiment, the left and right external leads 5 of the lead patterns corresponding to adjacent elements are inserted between the external leads 5 of the adjacent lead patterns, and at the same time, each lead pattern is connected to the outer part of the lead frame. They are formed so as to be inclined by a predetermined angle (#) with respect to the line 6, so that the element loading S1.1 of the lead pattern corresponding to each element is on a straight line parallel to the outline of the lead frame. It is set to be placed. In the lead pattern, the external leads that have entered each other should have their tips connected to the base of the other lead as shown in No. 51!11. It may be separated from the position shown in .

以上実施例で述べた本考案によれば、側々のパターンは
まったく同一のものを用いながらリードフレームの長さ
方向の寸法を短縮する事ができるとともに下記の種由で
前記発−の目的が達成できる。
According to the present invention described in the embodiments above, the longitudinal dimension of the lead frame can be shortened while using exactly the same side patterns, and the purpose of the above-mentioned generation can be achieved for the following reasons. It can be achieved.

■全てのリードフレームが同一の形状であり、完成品は
従来の製品とまりたく変らぬ−のがでする。
■All lead frames have the same shape, and the finished product is virtually unchanged from conventional products.

■リードの長さ方向は1例えば、14.16Pimlの
汎用ICタイプで2s−握短くなるが、それに対し纒は
従来とIIIm度におさえる事かでき ai造俟装の従
来タイプとの共用化が容易である。
■The length direction of the lead is 1. For example, with a general-purpose IC type of 14.16 Piml, the grip will be 2s shorter, but the lead length can be kept to 1/2m compared to the conventional type. It's easy.

■チップ及びリードの位置がそろっているので自動組立
機の適用が容易である。
■Since the chip and leads are aligned, it is easy to use an automatic assembly machine.

等である。etc.

本考案によるリードフレームな自動組立ラインにかける
場合に考慮丁ぺぎこととして、第**に示すようにボン
ディングヘッド8や認識ヘッドを7レーJ71イーダ9
の方向に対しり−ド7レームの頷1と合わせれば、従来
工程でペレットポンデインダやワイヤボンディング、i
1動認識を行なってきたのと全く同様の考え方で自動化
かでき◆。又。
When putting the lead frame on the automatic assembly line according to the present invention, it is necessary to take into consideration the bonding head 8 and recognition head 8 as shown in section **.
If combined with the nod 1 of the -7 frame in the direction of
Automation can be done using exactly the same way of thinking that has been used for single motion recognition◆. or.

認識装置がチップ10の傾tt−許せば第7図のように
傾いたままwmt*ンディングをする事もできる。又、
第8園のようにリード7レー五のフラグ(素子載量部)
五のみ傾#をなくしチップ10なつけても良いし、ブラ
ダの大きさが、チップ10に対し充分大診ければ、第9
図のようにチップのみ傾et一つけずにグイ(ベレット
)ボンディングしても良いであろう。
If the recognition device allows the chip 10 to tilt tt-, it is also possible to perform wmt* ending while the chip 10 is tilted as shown in FIG. or,
Lead 7 Ray 5 flag (element loading part) like the 8th garden
You can remove the tip #5 and add a tip #10, or if the bladder size is sufficiently large for the tip #10, the #9 tip can be added.
As shown in the figure, it may be possible to perform bullet bonding on only the chip without attaching any tilt.

さらK1110図に示すよ5にリードフレームの7ラダ
lと内リードは従来のパターンのままで外部リード5の
みを傾tt一つけるととによって同様の目的を達成する
ことがでする。
Furthermore, as shown in Figure K1110, the same purpose can be achieved by adding only the outer lead 5 at an angle tt while leaving the 7 ladder l of the lead frame and the inner lead in the conventional pattern.

wJwiの簡単な説明 g1ml〜第3図は従来のリード7レームパターンな示
す平面図である。第4図は本発明によるリード7レーム
パターンの一実施例な示ス平WiIE1%第5図は第4
図の一部を変形した一部拡大平面図である。第6図は本
発明によるリードフレームに牛導体素子を組立てる形1
IN−説明するための平面図、第7wJは同拡大平面図
である。第8図〜亀10図は本発明によるリードフレー
ムパターンの他の実施例な示す一部平面図である。
Brief description of wJwi g1ml~ Figure 3 is a plan view showing a conventional lead 7-lame pattern. FIG. 4 shows an example of the lead 7 frame pattern according to the present invention.
FIG. 3 is a partially enlarged plan view in which a part of the figure is modified. FIG. 6 shows a configuration 1 in which a conductor element is assembled to a lead frame according to the present invention.
IN- A plan view for explanation, No. 7 wJ is an enlarged plan view of the same. 8 to 10 are partial plan views showing other embodiments of lead frame patterns according to the present invention.

l・・・素子載置部(フラッグ)、2・−リード、3・
−7レーム、4・・・境界部、ト・・外部リード、6・
・・外郭線、7・−中心線、8・・・ボンディングヘッ
ド。
l...Element placement part (flag), 2.-lead, 3.
-7 frame, 4... border, g... external lead, 6...
... Outer line, 7 - Center line, 8... Bonding head.

9・・・フレームフィーダ、lo・・・中導体素子(チ
ップ)。
9... Frame feeder, lo... Medium conductor element (chip).

第  1  図 第  2  図 第  3  図 第  4  図 第  5  図 第  6  図Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims] 1、半導体素子載置部な中心に複数のリード及び外郭部
を有するリードパターンが長尺の導体平板に複数個連続
して形成さnた半導体リードフレームにおいて、1つの
素子に対応するリードパターンにおける複数のリードの
外部リード部は所定間隔で左右に並列して形成され、相
隣れる素子に対応するリードパターンの左右のリードは
互いに隣りのリードパターンのリードの関に入りこむと
同時に各リードパターンの少なくとも外部リード部がリ
ードフレームの外郭−忙対してそれぞれ所定角WL傾く
ことにより各素子に対応するリードパターンの素子載置
部がリードフレームの外郭−に平行に配置さnているこ
とを41黴とする半導体用リードフレーム。
1. In a semiconductor lead frame in which a plurality of lead patterns having a plurality of leads and an outer part at the center of the semiconductor element mounting part are successively formed on a long conductor flat plate, in the lead pattern corresponding to one element. The external lead portions of the plurality of leads are formed in parallel on the left and right at predetermined intervals, and the left and right leads of the lead patterns corresponding to adjacent elements enter into the gap between the leads of the adjacent lead patterns, and at the same time, the leads of each lead pattern 41 that at least the external lead portions are tilted at a predetermined angle WL relative to the outer contour of the lead frame, so that the element mounting portion of the lead pattern corresponding to each element is arranged parallel to the outer contour of the lead frame. Lead frame for semiconductors.
JP13146681A 1981-08-24 1981-08-24 Lead frame for semiconductor Pending JPS5833861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13146681A JPS5833861A (en) 1981-08-24 1981-08-24 Lead frame for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13146681A JPS5833861A (en) 1981-08-24 1981-08-24 Lead frame for semiconductor

Publications (1)

Publication Number Publication Date
JPS5833861A true JPS5833861A (en) 1983-02-28

Family

ID=15058613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13146681A Pending JPS5833861A (en) 1981-08-24 1981-08-24 Lead frame for semiconductor

Country Status (1)

Country Link
JP (1) JPS5833861A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075252A (en) * 1990-05-14 1991-12-24 Richard Schendelman Interdigitated trans-die lead method of construction for maximizing population density of chip-on-board construction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075252A (en) * 1990-05-14 1991-12-24 Richard Schendelman Interdigitated trans-die lead method of construction for maximizing population density of chip-on-board construction

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