JPS5833558B2 - image display device - Google Patents

Description

[Detailed description of the invention] The present invention relates to an image display device.

Conventionally, in display devices with full-surface pattern memory, when displaying characters, the memory between the lines of characters is used without storing information, resulting in poor memory usage efficiency and when the density of the pattern is coarse. The jagged edges of the displayed characters were an eyesore.

The present invention has been made in view of these points. For example, when displaying figures such as pictures, a pattern is displayed on the entire surface, and when displaying characters, etc., the pattern is displayed more densely than on the entire surface, and moreover, the memory is effectively used. An object of the present invention is to provide an image display device that increases the line spacing and displays images for easy viewing.

An embodiment of the present invention will be described below based on the drawings.

Now, assume that the entire pattern display is in A mode and the partial high-density display is in B mode.

In FIG. 1, Ml 7M22M32M4 is an image memory that stores patterns such as characters and figures, CH is a horizontal clock input terminal, C is a vertical clock input terminal, and EI
and El are operation enable input terminals to which a signal for permitting memory operation within one horizontal period and one vertical period is input;
RH is a horizontal address register reset input terminal, RV is a vertical address register reset input terminal, and 0 is an output terminal that outputs the memory contents specified by the horizontal and vertical address registers.

The address registers of the memos IJM1 to M4 are incremented with "l" by horizontal and vertical clock signals, but
It is assumed that if both operation permission input terminals E 1 and E 2 are active, no addition is performed and no output appears at output terminal O.

21 is a clock control circuit, which sends a horizontal clock signal to the terminals CH, CV and El, El of each memory M1 to M4;
The vertical clock signal and operation permission signal are switched by mode A/B.

Reference numeral 31 denotes a clock generation circuit which outputs a check signal, a horizontal position designation signal, a vertical position designation signal, and a reset signal necessary for memory reading to terminals CVA and CVB, respectively.

CHA, CHB and EIL, EIR, EIA and E21,
E22. E23. E24. E2X.

A horizontal synchronizing signal and a vertical synchronizing signal necessary for the raster scan/display device 51 are generated at terminals H and (2).

Next, the rask scan display device 51 uses the clock generation circuit 3.
It is driven by horizontal and vertical synchronizing signals of 1, and displays by the output from the memory output circuit 41.

Further, the memory output circuit 41 performs an OR operation on each of the memories M1 to M4 and outputs the result to the rask scan display device 51.

FIG. 2 is a time chart showing the output of the clock generation circuit 31 shown in FIG. .

CVA is the mode B horizontal and vertical clock signals CHB, C
It has a period twice that of VB.

In mode A, the signals sent to each memory M1 to M4 are controlled by the clock control circuit 21 as follows.

CV-CVA, CH=CHA MLM2. EI of M3 and M4=E2 of EIAM1=
E21. E2 of M2=E22E2 of M3=E23,
E2 of M4=E24 Therefore, referring to FIG. 2, the display screen P at this time is divided into four sections in the vertical direction as shown in FIG. 3, corresponding to each memory M1 to M4, and a pattern is displayed on the entire surface. The output of each memo IJ M 1 to M 4 is sent to a rask scan display device 51 through a memory output circuit 41 .

In mode B, the signals sent to each memory M1 to M4 are controlled by the clock control circuit 21 as follows.

CV = CVB, CH = CHB E1 of Ml and M3 = EIL E 1 of M2 and M4 = E I R E2 of Ml and M2 = E2X E2 of M3 and M4 = E2Y Therefore, referring to Figure 2, at this time Display screen P is Ml
and M2, and M3 and M4 are inserted horizontally adjacent to each other in a strip shape at appropriate positions in the vertical direction, and a partial pattern is displayed with increased line spacing, and each memory M1 to M2 is horizontal compared to mode A. , the vertical and vertical reading speeds are twice as high, and the display density is four times as high.

Such partial high-density display is considered to be particularly effective in character display; for example, a full-page pattern is displayed with 128 dots in the horizontal direction, and partial high-density is displayed with 2 horizontal dots.
Considering that it is displayed with 56 dots, the horizontal line will display about 16 alphanumeric characters and 8 kanji characters in the full pattern, but in partial high density mode, it will display 32 alphanumeric characters and 166 kanji characters. It is possible to display character length, detailed sentences, and easy-to-understand display.

Another advantage is that the same number of characters can be displayed using a finer font.

Also, the position of the belt at this time, that is, E2X. E2Y can be set at an appropriately visible position in the clock generation circuit 31.

Furthermore, by moving this position over time, the screen can be scrolled.

Note that in the case of mode A, E21, E22. E23゜E2
4 can be similarly scrolled and displayed.

This E21, E22. E23. E24 and the above E2X,
E2Y is a screen vertical position designation signal.

EII and EIR can also be used in the horizontal direction. The EIA can be operated as a horizontal position designation signal.

Further, the number of image memories is not limited to four and can be applied.

'As described above, the present invention can display an easy-to-read display by switching between full-scale pattern display and line-by-row partial high-density pattern display while effectively utilizing memory, while maintaining the same number of characters as before. Now, it is possible to display in a finer font, and it is also possible to display a larger number of characters than before.

Furthermore, we have achieved an excellent and low-cost image display device that allows users to enjoy varying images through the vertical and horizontal scrolling functions.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a block diagram thereof, FIG. 2 is a time chart showing the output of the clock generation circuit, and FIG. 3 is the correspondence between the display screen and image memory in the case of full-surface pattern display. FIG. 4 is an explanatory diagram showing the correspondence between the display screen and the image memory in the case of partial high-density pattern display. M1 to M4... Image memory, 21...
Clock control circuit, 31--Clock generation circuit, 41--Memory output circuit, 51--Rask scan display device.

Claims (1)

[Claims] 1. A plurality of image memories that can control memory read addresses, fine and coarse clock signals supplied from a clock generation circuit to each memory, and vertical and horizontal position designation signals that designate memory locations on the screen. a clock control circuit that switches between the full pattern display mode and the partial pattern display mode; a memory output circuit that ORs each memory output and outputs the output; and a memory output circuit that is driven at the same horizontal and vertical frequency in each mode. An image display device comprising a rusk scan display device that displays an entire pattern on a screen and a partial pattern at high density on a part of the screen by outputting. 2. The image display device according to claim 1, wherein the clock generation circuit is configured such that the vertical position designation signal or the horizontal position designation signal moves with time, so that scroll display is performed. .