JPS5833378A - Static picture recorder - Google Patents

Abstract

PURPOSE:To prevent assuredly the shift of a static picture to be recorded on a disket of a floppy disk device, by coinciding the horizontal positions of the joints on a screen comprising the FM signal information recorded on plural tracks of the disket. CONSTITUTION:A header signal adding circuit 22 is set to add the header signal to a slow read clock in order to detect a reference position for initiation of an FM signal recorded on a disket. An output of the circuit 22 is fed to a recording amplifier 31, and a read clock signal added with the header signal by the amplifier 31 is recorded on the disket simultaneously with the FM signal. While a header signal detecting circuit 23 detects the header signal from the difference of pulse duration between the header signal and the clock signal to detect the initiation position of the FM signal. As a result, the horizontal positions can be arranged regularly for the joints on a screen comprising an FM information recorded on plural tracks of the disket.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a still image recording device that records a video signal as still image information on a diskette of a floppy disk device. The present invention relates to a still image recording device that records on multiple tracks of a diskette of a floppy disk device.

Generally, the original purpose of a floppy disk device is to record and reproduce digital data, and digital data and a clock signal are written simultaneously.

Transfer data to diskette of floppy disk device -Y
When data is written, it is written according to a predetermined format, and in addition to data, track addresses, sector numbers, etc. are written. Further, a diskette of a floppy disk device is provided with a hole called an index hole, and this hole is detected by a light emitting diode and a phototransistor to generate an index signal indicating the start of a track.

The prescribed format of the above-mentioned monitor is that there are 26 sectors on the mini track, and these sectors consist of an ID field 101, a gap 102, as shown in FIG.
, 'f-L: Tuffield 103 and Gap 104
It consists of

It is determined that data address mark 105, data 106, and cyclic check (CRC) 107, which are a predetermined pattern, are written in the data field 103 in this order.

The data address mark 105 described above is a 1-byte specific bit pattern, and is provided to identify the beginning of the data field 103.

Therefore, in order to retrieve desired data from a diskette, first detect the start of the track using the index signal, select the sector to be retrieved, and then select the sector written further ahead of data field 1.03. By detecting the data address mark 105, which is a bit pattern, the start of the data is identified, and subsequent information is identified as data and is imported.゛By the way, if you try to record and play back the video signal that continues from the field memory in the form of an FM signal using a conventional floppy disk device like the one mentioned above, you will encounter a different system than when recording digital data. , since it is not possible to record the clock signal over the FM signal at the same time,
It is necessary to separate the FM signal and the clock signal and record them on both sides of the diskette.

As mentioned above, if the FM signal and the clock signal are separated and recorded on both sides of the diskette, it is determined whether the data written in the form of the FM signal is data that should be stored in the field memory. In other words, it is very important to accurately detect the beginning of FM fi, No. 7 written on the track. For example, as shown in Figure 2(a), -1-1 address and n
If one screen is constructed from the information of three tracks at address +a, and the detection position of the start of the FM signal at address n11 shifts, the image will shift as shown in Figure 2 (1)). I end up.

Therefore, it is necessary to detect the beginning of the FM signal of each track. In order to detect the FM signal of each track, the index bridge number indicating the beginning of the track of the diskette output from the floppy disk device is required. It is possible to use .

However, the above index signal is generated by the index hole (diameter 2.54 mm) in the diskette.
), it is inevitable that the output timing will fluctuate, and the position accuracy of the index hole is allowed to fluctuate by ±500 μs in time conversion. ±5 to detect the beginning of
During the fluctuation of 00 Ps, the index signal is large and cannot be used.

Also, in order to detect the beginning of the FM signal of each track,
Similar to when recording digital data, it is also possible to set a specific bit pattern such as the data address mark 105 at the beginning of the data and use this bit pattern to detect the beginning of the FM signal of each track. However, even if a specific bit pattern is added to the FM signal or a single frequency clock, it is difficult to distinguish the clock or FM signal from the bit pattern and identify the leading position during reproduction.

The present invention has been made in view of the above-mentioned circumstances when a still image is obtained by recording one field of video signal in the form of an F'M signal on a floppy disk device. A header having a parnu width larger than a clock signal recorded in synchronization with the FM signal on the surface opposite to the recording surface of the diskette on which the signal is recorded in the form of an FM signal, and representing the starting position of the FM signal. A header signal addition circuit is provided for adding a signal to the clock signal, and by detecting the header signal from the difference in pulse width between the header signal and the clock signal and detecting the starting position of the FM signal, each trunk of the diskette is It is an object of the present invention to provide a new still image recording device that detects the reference position of the start of an FM signal recorded in the image and prevents image shift.

Another object of the present invention is to delay the header signal from the index signal indicating the start of the track, and write a pseudo clock signal in the meantime, thereby erasing the previously written header signal and allowing only the regular header signal to remain. It is an object of the present invention to provide a still image recording device which detects image shift and prevents image shift.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 shows a block diagram of a still image recording device using a floppy disk device.

The still image recording device has two operation modes, one for recording and one for reproduction.

That is, during recording, there is a fast write mode in which the video signal of one field is written to the field memory in real time, and a fast write mode in which the contents of the written field memory are written in one field memory.
There is a slow read mode in which the data is read out at a speed of /33, converted into an analog signal, and then FM modulated and recorded on three tracks of a diskette of a floppy disk device along with the clock used to read out the field memory.

On the other hand, during playback, the FM signal played by the floppy disk device is demodulated, and the playback clock
There is a slow write mode in which the data is sampled again and written to the field memory, and a fast read mode in which the contents of the field memory are read out at the scan rate of the television scan line and converted to an analog signal to obtain a reproduced video signal.

The configuration of the still image recording apparatus shown in FIG. 3 will be explained below according to the above four operation modes.

[Fast write mode operation part]

The video signal input to the video signal input terminal 11 is passed through a low-pass filter (L,
P, F, ) is input to the pre-filter 1, then input to the pedestal clamp circuit 2 for processing, and a movable contact C1 is connected from 1 to the contact point of the switch S1 of the selection circuit 3 that selects recording and playback. A/D with 6-bit quantization
The signal is input to converter 4 and converted into a 6-bit digital signal.

On the other hand, the video signal is also input to the synchronization separation circuit 7, and based on the horizontal synchronization signal separated by the synchronization separation circuit 7, a fast write clock generation circuit 8 generates a fast write clock that serves as a reference for the write operation. ing.

The clock for writing to the field memory 5 in which the output of the A/D converter 4 is written is the fast write clock described above or the slow write clock to be described later. Select Fastlight Clock.

The fast write clock is input to the A/D converter 4 as a sampling pulse for sampling the video signal, and is also input to the write address control circuit 10 as a write clock pulse.

The write address control circuit 10 creates a write address for writing the digital signal sampled by the A/D converter 4 and quantized to 6 bits into the field memory 5 constituted by a semiconductor memory.

The field memory 5 has a configuration as shown in FIG.

In the field memory 5 shown in FIG. 4, an input digital signal is converted into parallel data by a 10-bit serial-to-parallel conversion circuit 35, temporarily stored by an input latch 36, and 60 memories are converted at a cycle of 1710 of the sampling frequency. The data is written into a semiconductor memory section 37 consisting of the following.

The field memory 5 has the above configuration because A.
When writing a 6-bit digital signal from the /D converter 4 to the semiconductor memory section 37, the sampling frequency is about 12 MHz (period: about 82 μs), so the cycle time of the semiconductor memory section 37 and This is because a signal sampled at a frequency of 12 MHz cannot be directly written into the semiconductor memory section 37 for this reason.

On the other hand, when reading a signal, the field memory 5 temporarily stores the signal from the semiconductor memory section 37 in the output latch 38, and converts the signal from the semiconductor memory section 37 into serial data using the parallel-to-serial conversion circuit 39. ing.

The RAM controller 40 creates control signals such as an address signal, a write signal, an input latch signal, an output latch signal, a serial-to-parallel conversion clock, and a parallel-to-serial conversion clock from the write address signal and the read address signal. This is a circuit that does this.

Next, the fast write block generating circuit 8 generates a well-known PLL (Phase Locked) signal as shown in FIG.
Loop) circuit, which includes a phase comparator 41 that detects the phase difference between the reference signal and the comparison signal, a phase comparator 41 that detects the phase difference between the comparison signal, and a phase comparator 41 that removes the high frequency components. The low-pass filter 42 and the input voltage
A voltage controlled oscillator 43 that generates a signal with a frequency of 2fs, and a frequency fs of the signal output from the voltage controlled oscillator 43.
1/N frequency divider circuit 44.

The reference signal input to the phase comparator 41 is a horizontal synchronizing signal, and the frequency division ratio N of the frequency divider circuit 44 is determined based on the capacity of the field memory 5 and how much of one horizontal opening period is sampled. In this example, N=
772 to Fukagawa.

Therefore, the fast write clock frequency fs (output signal frequency of the voltage controlled oscillator 43) by the fast write clock generation circuit 8 is fs = 772 x 15.784 = 12.147 MHz, and this 12.147 MH2 clock is used to sample the video signal. and into the field memory 5.

I am doing a lot of research.

In this embodiment, the video signal is a monochrome signal, and the sampling frequency is 12.147 MHz as described above. However, in the case of a color signal, if the frequency of the color subcarrier is fsc, then 3×[sc = IQ,
A sampling frequency of 7 MHz or 4 x fsc = 14.3 Mtlz is used.

In addition, in this embodiment, when writing the video (No. 4) of one field period into the field memory 5, the semiconductor memory section 37
In order to keep the capacity as small as possible and store as much information as possible within the range of customer traffic, only the period during which video information exists is stored.

Therefore, for the horizontal component of the video signal Q, the horizontal blanking period is not sampled, and for the vertical component, the vertical synchronization period is not sampled. of clock minutes (85 percent of one horizontal opening period), and
In the vertical write processing circuit 26, write gates for 249H are respectively created, these write gates are input to the write clock selection circuit 9, and the output J+ of the write gate is inputted to the write clock selection circuit 9.
, Jj, the video signal is sampled and written into the field memory 5.

[Slow read mode operation part]

When the fast write mode ends and writing of the digitized video signal to the field memory 5 is completed,
A slow mode signal is input to the slow clock generating circuit 15 in FIG. 3 from the slow mode signal input terminal 2.

The slow clock generation circuit 15 is a circuit that generates a slow read clock, and when the slow mode signal is input as described above, the slow clock generation circuit 15 outputs the slow read clock to the read clock selection circuit 12.

The read clock selection circuit 12 is a circuit that selects between a slow read clock and a fast read clock output from a fast read clock generation circuit 13, which will be described later. is selected and output as a read clock pulse and a D/A pulse to the read address control circuit 11 and the 6-bit D/A converter 6, respectively.

The read address control circuit 11 creates a read address for reading the field memory 5 using a slow read clock input as a read clock pulse.

Further, the D/A converter 6 takes in the digital signal from the field memory 5 according to the slow read clock inputted as the D/A pulse, and converts it into an analog signal at the cycle of the D/A pulse.

The output of the D/A converter 6 is input to a low-pass interpolation filter 18 for smoothing.

The interpolation filter 18 outputs a video signal that is time-base converted with respect to the video signal input to the video signal input terminal II.

The frequency fck of the slow read clock described above is determined by the number of tracks on the diskette used for one feed and read clock, and the maximum frequency of the time-axis converted video signal. , the frequency fck of the slow read clock is set to 1738, which is the sampling frequency at the time of fast write, and f ck ” 1..2447H/3B = 36.
It becomes 8 KHz.

On the other hand, the highest frequency f, max of the video signal input from the video signal input terminal 11 is fmax = 4.57 MH
z, the highest frequency fsmax of the time-axis converted (low frequency) video signal is fsmax=4.6
7/3 B = 141.5 KHz.

The time-base converted video signal output from the interpolation filter 18 is input to the FM modulation circuit 19 .

The FM modulation circuit 19 is a circuit that modulates the time-base converted video signal into an FM signal of 1 KHz to 220 KHz, and its output is input to the recording amplifier 30 in the floppy disk device 20. The recording amplifier 30 records the FM signal of the time-base converted video signal on a track on one side of the diskette.

As described above, the FM signal of the time-axis converted video signal is recorded on one side of the diskette of the floppy disk device 20, but in order to reproduce this FM signal and store it again in the field memory 5, it is necessary to A clock is required to obtain the programming pulse and write address, and this clock, like the FM signal, is used for the floppy disk drive 2.
It must be a signal that receives fluctuations due to rotational unevenness that occur within 0.

Therefore, in order to correct fluctuations in the FM reproduction signal due to rotational irregularities occurring within the floppy disk device 20, it is necessary to write a clock on the other side of the diskette.

Therefore, in this embodiment, the recorded FM
Header signal addition circuit 2 for adding a header signal for detecting the reference position of the signal start to the slow read clock
2 are provided.

The header signal has a pulse width sufficiently larger than that of the slow read clock, and the output of the header signal adding circuit 22 is input to the recording amplifier 31.
1, the read clock signal to which the header signal is added is recorded on the diskette at the same time as the FM signal.

Note that when recording an FM signal on a diskette, the horizontal write processing circuit 25 generates 650 clock pulses of read clock pulses, while the vertical write processing circuit 26 generates 650 clock pulses.
To create a read gate for 83H, first read 83H from field memory 5, and read out 83H from field memory 5.
Record on the second track.

When the recording of the first track is completed, the mode control circuit 28 detects the index signal from the floppy disk device main body 32 and outputs a head access signal, and the track control circuit 29 moves the head to record the second track. 88H worth of information is recorded on the track.

Similarly to the above, information for 8aH is recorded on the third track, and in three tracks, recording for the ■ field, that is, for 249H, is completed.

[Slow light mode operation part]

The reproduction amplifier 33 of the floppy disk device 20 reproduces the FM signal written on the diskette, outputs its output to the FM demodulation circuit 21, and restores it to a time-base converted (low-frequency converted) video signal.

The output of the FM demodulation circuit 21 is input to the A/D converter 4 from the contact P1 of the switch S1 of the selection circuit 3 through the movable contact C1.

On the other hand, the reproduction amplifier 34 of the floppy disk device 20 reproduces the clock signal written on the side opposite to the recording side of the FM signal at the same time as the FM signal, and outputs a write clock signal.

The header signal detection circuit 23 detects a header signal included in the write clock signal.

Since the timing immediately after the detection of the header signal is the reference for the start of the FM signal, the game subcircuit 24 extracts the write clock signal of the header signal and performs a null write clock.

The slow write clock is input to the write clock selection circuit 9 together with the fast write clock.

The locking clock selection circuit 9 selects the slow write clock in the slow write mode.1. - The slow write clock is input to the A/D converter 4 as a sampling pulse, and is output to the write address control circuit 10 as a write clock pulse.

The A/D converter 4 samples the low frequency conversion video signal output from the FM demodulation circuit 21 using the slow write clock as a sampling pulse, converts it into a digital signal, and generates a write address output from the write address control circuit 10. The data is written to the address of the field memory 5 specified by.

As already mentioned, the video signal of one field is
The data is recorded on three tracks of the diskette, and the horizontal write processing circuit 25 operates similarly to the slow read mode.
creates a gate for 650 clocks of write clock pulses, and the vertical write processing circuit 26 creates a write gate for 8aH, respectively 9, and transfers 83H worth of video information obtained from the first track of the diskette to the field memory 5. Write - When this write operation is completed, the head of the diskette moves and the video information recorded on the second and third tracks of the diskette is transferred to the field memory 5.
I try to write to .

[Fastly lower mode operation part]

When the slow write mode ends and writing of the low frequency converted video signal to the field memory 5 is completed, the mode control circuit 28 outputs a fast read mode signal.

The synchronization signal generation circuit 14 includes a 4×fsc crystal oscillator 14.
', creates a horizontal synchronization signal that serves as a reference for the reproduced signal, and transmits the horizontal synchronization signal to the fast read clock generation circuit 1.
Output to 8.

The fast read clock generation circuit 13 is constituted by a PLL circuit shown in FIG.
A fast read clock, which serves as a reference for the read operation, is created using the above-mentioned horizontal synchronization signal inputted from the controller as a reference signal.

The frequency of the fast read clock mentioned above is the same as the frequency of the fast write clock, fs=12°147 M
It is Hz.

The fast read clock is input from the read clock selection circuit 12 to the read address control circuit 11 as a read clock pulse, and is also input to the D/A converter 6 as a D/A pulse.

The read address control circuit 11 creates a read address signal for reading information written in the field memory 5 from the read clock pulse.

The D/A converter 6 converts the digital signal read from the field memory 5 according to the read address signal into an analog signal using a D/A pulse, and the output of the D/A converter 6 is passed through an interpolation filter. 16 to restore the video signal to the same scan rate as the television.

On the other hand, the horizontal write processing circuit 25 creates read gates for 650 clock pulses, and the vertical write processing circuit 26 creates read gates for 249H. No signal is read out during the non-open period, ie, the horizontal blanking period and the vertical synchronization period.

A video signal without a horizontal blanking signal and a vertical synchronizing signal outputted from the interpolation filter 16 is inputted to a mixing circuit 17 together with a composite synchronizing signal and a composite blanking signal outputted from the synchronizing signal generating circuit 14, and the mixing circuit 16 performs the above-mentioned processing. A composite video signal is created by adding a composite synchronization signal and a composite blanking signal to the video signal, and the composite video signal is passed from the playback side contact P2 of the switch S2 of the selection circuit 3 to the common contact C2. I am trying to output it.

In the fast read mode described above, by continuously and repeatedly reading out the field memory 5, a continuous composite video signal is output from the common contact C2 of the switch S2 of the selection circuit 8, and the composite video signal is If you input it to a television receiver, you will get a still image.

Note that the mode control circuit 28 in FIG. 3 controls the operating portions of the four modes described above based on input signals from the operation keys 27, and supplies necessary mode signals for each mode.

Next, the operation of the still image recording apparatus shown in FIG. 8 will be explained, focusing on the operations of the header signal addition circuit 22 and the header signal detection circuit 23.

In the present invention, as already explained, at the time of recording,
A header signal is inserted into the clock signal (addition of header signal) with a pulse width larger than the pulse width of the Chloran signal and matched with the beginning of the FM signal, and is recorded on a diskette.

On the other hand, during reproduction, the pulse width of the clock signal is determined, a header signal having a pulse width within a predetermined range is detected (detection of a header signal), and the starting position of the FM signal is determined.

[Additional operation of header signal]

In the slow read mode, as shown in FIG. 6, the starting position of the track is identified by the index signal output from the floppy disk device 20, and the slow mode signal is output by the mode control circuit 28. Created.

The null clock generation circuit 15 generates a clock pulse and a header signal using the slow mode signal.

The pulse width of the above header signal is approximately twice the pulse width of one cycle of the clock pulse (fck = 868 KHz, period 2.7 μs) to distinguish it from the clock pulse (5
μs).

Note that in FIG. 6, the clock prohibition signal adds a header signal to the clock pulse, so this period (10μ
Let it be s. ) is a signal that inhibits clock pulses, and output of the slow read clock is inhibited only during the above period.

The slow read clock and the header signal are added by the header signal adding circuit 22 to create a read clock, which is recorded on the diskette.

On the other hand, due to the slow read clock, field memory 5
During the period TO before the slow read clock is output, the FM signal read out from the diskette and recorded on one side of the diskette opposite to the recording side of the read clock is a simple signal with no input signal to the FM modulation circuit 19. Although it is one frequency, the period T after the timing when the slow read clock is output
1, it becomes an FM modulated wave that is FM modulated by the interpolation filter 18.

[Header signal detection operation]

To detect the header signal from the write clock signal reproduced by the floppy disk device 20, the difference in i4t response width between the header signal and the clock signal is utilized.

That is, since the header signal period is 10 .mu.s and the clock signal period is 2.71 LS, a signal with a width greater than 2.7 .mu.s and 10 .mu.s or less is extracted as a header signal.

As shown in FIG. 7, the floppy disk device main body 32
When the index signal is input from the mode control circuit 2
A slow mode signal is output from 8, and this slow mode signal gates the reproduced clocks 6 and 6 regenerated by the floppy digital device main body 32 to create a write clock.

The write clock is input to a header signal detection circuit 23 consisting of a retriggerable monostable circuit or the like. .

The above-mentioned retriggerable monostable circuit is a circuit in which if the next trigger signal is input before the monostable circuit finishes its operation, the trigger signal starts the monostable circuit operation again.
．． The time constant T of the retriggerable monostable circuit is 2.7 μs<
If it is selected so that T< 10 Ps, the pulse width identification signal output from the retriggerable monostable circuit will go from the %HI level to the 'L level at the rising edge 9 of the header signal portion of the write clock. , T<10Ps<
710 (=period of the header signal portion of the reproduced clock pulse), the above pulse width identification signal always ends the monostable circuit operation between the header signal and the following clock signal, and the pulse width identification signal changes from 'L level' to 'L level'. Become IH Rubel.

On the other hand, when the clock signal exists continuously, the period 711 of the clock signal is T11=2.7 μs, which is 11 (=2.7 Ps) (T, so the above monostable circuit operates at the rising edge 9 of the clock signal, but the next clock signal is input before the operation is completed.

Therefore, the pulse width identification signal changes from the %HI level to $L' at the rising edge of the clock signal next to the header signal.
Once the level is reached, the level will be maintained at 1L level as long as the clock signal continues with a period of 2.7 μs.

That is, at the first timing after the operation by the header signal of the monostable circuit ends, the pulse width identification signal becomes 1H.
The timing of falling from the level to the 1L level 0 is the end of the header signal period and the timing of the start of the clock signal.

A header identification signal is created at the above timing to, and the FM demodulated video signal is sampled by the slow write clock obtained by gating the reproduced clock pulse using the header identification signal and written into the field memory 5. .

As described above, the start timing of the FM signal is determined by detecting the header signal from the reproduced clock pulse. However, since the floppy digital device 20 has the following characteristics , the following problems arise.

■When erasing, floppy disk devices use a method of erasing only the signals on both sides of the signal written on the track in order to obtain a guard band. This is done by writing a new signal over the previously written signal without performing an erase operation.

(2) The index signal obtained from the floppy disk device 20 has a large fluctuation of ±500 μs.

Assume that a clock pulse and an index signal have been written in a certain track of a diskette as shown in FIG. 8, and when a read clock shown in FIG. If the signal is at a position later in time than the previous index signal, as shown by the delayed index signal in FIG. 8, a new read clock will be written from this position.

However, due to the above-mentioned characteristic (■), writing is not performed on the diskette track during the period in which the index signal is delayed, and neither is erasing. Since the written header signal exists, the reproduced read clock may include a pseudo header signal in which there are two header signals, or may be a one-dot clock.

When the read clock as described above is regenerated and a header signal is detected, the pseudo header signal hd shown in FIG.
Since there is no difference from the header signal hi, the header signal detection circuit 23 identifies the pseudo header signal hd as the regular header signal hi, and from the timing of the end of the pseudo header signal period, the header signal detection circuit 23 identifies the pseudo header signal hd as the regular header signal hi. When the writing operation begins, the reproduced image will be shifted in the horizontal direction, as shown in FIG.

In order to eliminate the deviation of the reproduced image due to the pseudo header signal as described above, as shown in Figure 9:
The header signal may be inserted with a greater time delay than the above, and a pseudo (dummy) clock pulse may be written between the index signal and the header signal.

As mentioned above, if you delay the header signal and write a pseudo clock pulse between the index signal and the header signal, the pseudo clock pulse will always be written on top of the previously written pseudo header signal. Therefore, the pseudo header signal is always erased, and it is possible to eliminate deviations in reproduced images due to the pseudo header signal.

Although the basic embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various configurations can be made within the scope of the gist of the present invention.

As is clear from the above detailed explanation, the present invention provides a clock signal recorded on the other side of the diskette in synchronization with the FM signal of the video signal recorded on one side of the diskette, and a clock signal added to the clock signal. Since the header signal is detected based on the difference in pulse width from the header signal and the starting position of the FM signal is detected, the reference position of the starting position of the FM signal recorded on each track of the diskette can be detected. Using a floppy disk device, you can obtain still images without any deviation.

Furthermore, if the header signal is delayed from the index signal and a pseudo clock signal is written in between, the previously written header signal will always be erased, and it is possible to reliably prevent the playback image from shifting due to the pseudo header signal. can.

4. Brief explanation of the drawings Figure 1 is an explanatory diagram of the format of data recorded on the diskette of a conventional floppy disk device, Figure 2
Figure ←) and the mountain are explanatory diagrams of reproduced images when the start of the FM signal of the video signal recorded on the diskette is detected accurately and when it is not detected, respectively. Figure 3 is an illustration of the reproduced image according to the present invention. A block diagram of an embodiment of a still image recording device, FIG. 4 is a block diagram showing the configuration of a field memory,
Fig. 5 is a block diagram of the PLL circuit, Fig. 6 is a time chart for adding a header signal, Fig. 7 is a time chart for detecting a header signal, and Fig. 8 is a diagram explaining the shift of half a page due to a pseudo header signal. The time chart in FIG. 9 is an explanatory diagram of the insertion timing of the header signal and the pseudo clock pulse.

4... A/D converter, 5... Field memory, 6... D/A converter, 8... Fast write clock generation circuit, 9... Write clock selection circuit,
10... 1 bottle 1 address control circuit, 11... Read address control circuit, 12... Read clock selection circuit, 18... Fast read clock generation circuit, 1
5... Slow clock generation circuit, 19... FM modulation circuit, 20... Floppy disk device, 21...
FM demodulation circuit, 22... Header signal addition circuit, 23.
...Header signal addition times i-each.

Patent applicant: Sanyo Electric Co., Ltd. Representative: Lawyer: Aobai Ao and two others Figure 1 (a) (b)

Claims (1)

[Claims] (1) A device that records one field of video signal stored in a field memory in the form of an FM signal on multiple tracks of a diskette of a floppy disk device, the FM signal being recorded on the opposite side to the recording surface of the FM signal. The clock signal recorded in synchronization with the FM signal also has a large pulse width, and includes a header signal adding circuit that adds a header signal representing the starting position of the FM signal to the clock signal. It is equipped with a header signal detection circuit that detects the start position of the FM signal by detecting the header signal based on the difference in the pulse width of the diskette. A still image recording device characterized in that the directional positions are matched. (2. In the still image recording device according to claim 1, the header signal addition circuit is configured to perform a fixed time period determined by variations in the output timing of the index signal from the index signal indicating the start of a track on the diskette. 9. A still image recording device characterized in that a header signal is added to the clock signal with a delay of 9, and a pseudo clock pulse is written between the index signal and the header signal.