JPS5833363A - Producing circuit of synchronizing signal - Google Patents

Abstract

PURPOSE:To always supply a subcarrier in correct phase relation with a solid- state-image pickup element, by always securing phase locking between the working of a frequency dividing circuit which generates the subcarrier to the same phase mode and preventing the change of the orthogonal phase relation of the subcarrier when the application of the power supply is repeated. CONSTITUTION:The reference clock signal (a) of the TV signal given from a reference clock generator 1 is supplied to the input of a T-FF2. The signal (a) is divided into two parts by the T-FF2, and the divided signals (b) and signal (c) are delivered. These signals (b) and (c) delivered from the T-FF2 are turned into input signals (j) and (k) of a waveform shaping circuit 9. The circuit 9 produces horizontal scanning clock pulses (l) and (m) of a solid-state image pickup element. While signals (a), (b) and (c) are applied to NAND gates 4 and 5 plus T-FF3 respectively, and the timing to actuate T-FF6 and 7 is obtained through the gates 4 and 5 plus the T-FF3. Then subcarriers (f) and (i) which have the same phase mode at all times are delivered from the T-FF6 and 7 and supplied to the solid-state image pickup element.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses a solid-state image pickup device to produce a synchronization signal generation circuit K1141 for a color television image pickup device.

The point K that operates the television imaging device is horizontal,
Various driving signals such as vertical synchronization signals and blanking pulses are required, but in addition, in a color chi-revision imaging device using a solid-state image sensor, 8111 carrier, wave transmission, and solid-state imaging are required to transmit color information. A narrow p-scan pulse is required to horizontally scan the imaging pixel of the device.

By the way, in an NTSC color television device, the subcarrier is specified to have a frequency that is 455/2 times the horizontal frequency of the television signal.
Generally, a reference clock with a frequency of 910 times the horizontal frequency is divided into four to obtain two-phase subcarrier pulses with a phase difference of 90 degrees, and various color signals are generated using this as a reference. It's like K. Hue information among the color signals is transmitted as various phases synthesized from the two-phase subcarriers whose phases are orthogonal (90 degree phase difference) -f.

On the other hand, for the 10 pulses for scanning the solid-state image sensor described above, - general pf is set to a frequency that is an integral multiple of the horizontal frequency of the television signal, and a frequency that is an integral multiple (mainly twice) of the above-mentioned subcarrier. It has been decided that the distance will be 5km.

Therefore, these subcarriers and clock pulses are generally generated from the same reference clock signal, and a synchronization signal generation circuit for this purpose, for example, as shown in Figure 1, has traditionally been used. .

In this wJ1 diagram, 1 is a reference clock generator, 2.
3.8 is T-free lag prop (hereinafter referred to as T-FF)
, 4 and 5 are Nant gates, 6.7 is a D-arbit 70 tube (hereinafter referred to as D-FF), and 9 is a waveform shaping circuit.

Next, the operation of this circuit will be explained using the timing chart shown in FIG.

The reference clock generator 1 generates a reference clock signal a having a frequency 910 times the horizontal frequency of the television signal as shown in FIG. 2 (1) K, and T of T - FF2.
supplied to the input. Therefore, from the output of T-FF2, if the signal a'Y2 is frequency-divided and a good signal is obtained, an inverted signal C is obtained. This signal bt'g2 (2) k shows 0 This 2 frequency divided signal is supplied to the input of the next T-FF3 n,
A 4-frequency divided signal d of the reference clock signal a as shown in FIG. 2(5)K is obtained as the Q output.

Friend, the frequency-divided signal S is also supplied to the other input of the Nantes gate 4, which has the reference clock signal 1 inputted to one input, and the signal e shown in FIG. 2 (4) is output. taken or taken out.

Therefore, this signal is supplied to the D input of dvD-FF6, the signal C is supplied to its clock input φ, and the reference clock signal a as shown in FIG. The subcarrier f obtained by dividing the frequency by 4 is obtained by n, which is K.

Similarly, the Q output of T-FF3 is obtained in Figure 2 (6
) A signal g'kD as shown in K is supplied to the D input of FF7, and its clock input φKaJRZ is supplied to the output signal h of the Nantes gate 5 which is used as an input. As a result, the next carrier wave l is obtained by dividing the reference clock signal a by 4 from the Q output of this D-FF7 as shown in FIG. f, i can be obtained. Note that the above is the same as a known synchronizing signal generating circuit, but as described above, a clock pulse generating circuit for horizontal scanning must be added for a color television image pickup apparatus using a solid-state image pickup element.

Therefore, the reference clock signal a from the reference clock generator 1 is supplied to the T input of T-FF@, and the 2-frequency divided signal j of the signal a as shown in FIG. 2 (16) is obtained at its Q output. This is supplied to the waveform shaping circuit 9 and its output is
As shown, get lick pulse JY and T-FF8
The inverted output signal k of the signal j obtained at the Q output of is supplied to the waveform shaping circuit 8, and the output signal #! A p-suck pulse mf is obtained as shown in Fig. 2 θ8). Then, these n clock pulses 1 and m may be supplied to the solid-state image sensor as two-phase clock pulses. Note that the clock pulse for driving the solid-state image sensor is not limited to two-phase clock pulses, but here -
As an example, two-phase clock pulses l and mK are shown.

By the way, in the above explanation, T-FF for subcarrier generation
2 and the frequency division phase of T-F'Fl for clock pulse generation coincide with each other, and their output signals and j have the same polarity. In reality, the initial state of T-FF2.8 when the power is turned on, etc.
C, these branching phases become opposite to each other, and the signal becomes j
It may operate with the polarity reversed. At this time, Fig. 2 Q) to (8) K indicates t signals b, i
The operation timings are as shown in (9) to (15) K signals b' to i' in the figure. That is, in the circuit S of FIG. 1, due to the difference in the initial state such as when the power is turned on, the subcarriers f and i are set as (5) in FIG. 2 with respect to the horizontal scanning clock pulses l and m of the solid-state image sensor.

(8) Signals f and i indicating K and (12) and 05 in Fig. 2)
Two phase modes of the signals f' and i' shown by K are obtained as follows.

Therefore, the duty of the reference clock signal is exactly 1.
If the pair is 1, the subcarriers f and I or f't!, regardless of the phase mode. The phase difference with ' is maintained at a positive 1K90 degree in all cases, and there is no problem in operation.

However, in general, the human power impedance at the horizontal scanning clock pulse input terminal of a solid-state image sensor exhibits a fairly large capacitance, and this results in a large capacitive load (several tens to hundreds of pF) for the clock pulse human power. Therefore, the ripple component of the clock pulse frequency for horizontal scanning is likely to be mixed into the operating tmt ratio of the synchronization signal generation circuit, and it is extremely difficult and almost impossible to completely prevent this.

Moreover, the capacitive impedance of the horizontal scanning clock input of this solid-state image sensor has slight variations for each input, and as described above, the horizontal scanning clock pulse is applied to the power supply voltage of the synchronization signal generation circuit. If a frequency ripple is mixed in, the reference P clock signal a is isometrically modulated in pulse width by the horizontal scanning clock pulse frequency, resulting in a rectangular shape, as shown by the broken line in Fig. 2 (1), for example. Therefore, the operation timings of other signals also change as shown by broken lines in (2) to (16) in FIG. 2.

As a result, the phase differences θ and θ' between subcarriers f and i, and between Fif' and i' are (s), (s) e (j2
) and 5), the waveforms are deviated from 90 degrees, as is clear from the broken line waveforms.

As already explained, in a color television device, two-phase subcarriers whose hue information of color signals are orthogonal! Since K is set to be transmitted based on the reference, as mentioned above, the phase difference θ of the subcarrier, and θ' in the subcarrier wave, deviates from 90 degrees,
If the orthogonal relationship breaks down, it will be difficult to transmit color information that is accurate to 17ia.
K is coming. However, if this phase shift is always kept constant, it can be easily corrected using a phase correction circuit, etc., and the correct color information can be transmitted. When m'tt is received, K is determined in special cases (for example, in the conventional example above, θ in Figure 2)
The phase difference θ and θ' is It is always different and elaborate.

When the phase difference differs in this way, the above phase correction becomes difficult and almost impossible.

Therefore, in the conventional 1FIK as described above, each time the nine-phase mode changes due to repeated turning on of the IL source, the orthogonal relationship of the K11l carrier wave changes, and the orthogonal relationship of the K11l carrier changes, which is necessary to obtain a color television signal with the correct hue. accurate phase relationship l
It has the disadvantage of not being able to supply subcarriers with

SUMMARY OF THE INVENTION It is an object of the present invention to provide a synchronization signal generation circuit which avoids the drawbacks of the prior art as described above and which prevents the orthogonal phase relationship of subcarriers from changing even after repeated power-on operations.

To achieve this objective, the invention is characterized in that the operation of the frequency divider circuit for subcarrier generation always assumes the same phase mode K1g1 at point t.

Hereinafter, an explanation will be given of a drawing showing an example of a synchronization signal generation circuit using a misfiring F93.

Figure 3 on the side shows an embodiment of the present invention, in which the same or equivalent parts as in the conventional example shown in Figure 1 are given the same reference numerals. The difference between the embodiment shown in FIG. 3 and the conventional example shown in FIG. 1 is that T-FF8 in the conventional example shown in FIG. 1 is omitted, and the Q output signal of T-FF2 is Signal C becomes waveform shaping circuit 90 input signal J and kK, respectively.
The only difference is that K is set so that two-phase clock pulse signals J and m for horizontal scanning of the solid-state image pickup device are generated from K, and the rest is the same as the conventional device shown in FIG.

Therefore, the operation is similar to the signal (2) in the tying chart of Diagram 2, and the signal j of 96) is the same signal, and for the signal j shown in Figure 2 06). Of course Shinji! The signals jb have the same phase as shown in (2) K in the same figure, and never become the signals b' of opposite polarity as shown in (9) in the same figure.

According to this embodiment, T-FF3 and Nantes Gate 4, 5. In addition, the operation timing of D-FF8.7 is only such that the signal d-i shown in FIG. 2 (3) to (8)K is obtained, and therefore the Q
The phase difference between the signals f and i (i.e., 11J transmission waves) obtained at the output is also the same as when the power is turned on, i#p return, etc. θ', and it is possible to obtain subcarriers that always maintain the same phase difference.

Next, FIG. 4 shows another embodiment of the present invention. In this embodiment, the same reference numerals are given to the same or the same parts as in the conventional example shown in FIG. 1, and only the different points will be explained. .

In Figure 4, 10 is Nando Game), 11 is D-FF
, 12 is an inverter, 13 is a T-FF, 14 is a 2-circuit 2
This is a contact changeover switch circuit.

In the embodiment shown in FIG. 4, the output of T-FF2 and T-
The output of FF8 is detected by OK, and the switch circuit 14 is switched and controlled so that these output conditions are in a predetermined state.
and clock pulse for horizontal scanning! .

The phase mode with m is convergently fixed to -'1Mh, and its operation will be explained below with reference to the timing chart (K) in FIG. Note that the PTS signal 1 according to the original text shown in (1) of FIG. 5 has been subjected to pulse width modulation as shown by the broken line K in FIG. 2 (1).

T-FF13 is set to the set state, and its Q output signal p is 1 pJs as shown in Figure (7) VC, and it is switched to the upper contact at switch turn w114 as shown in Figure 4. Suppose there were n. And at this time, T-FF
The output coefficient j of 8 and the output signal of T-F' F2.

The phase relationship with C is (2), (3), (
4) When they are in the state shown, they become friends.

Then, the signal that appears at the output of Nando Game) 10, n
When the signal n and the reference clock signal a are both Kr1JK as shown in Fig. 5 (5), the Q of D-FF11 is
The output signal O becomes [j)c. Immediately after that, the reference PTS signal stage rises to "1" again, that is, time t. )C, the T-FF13 is reset, and as shown in FIG.
7) As shown by K, the output of K is Q' (if U p is 0)
The contact Vi of the switch circuit 14 is switched from the state shown in FIG. 4 to the lower contact.

As a result, the output signal of the switch circuit 14 (b4-
c) and (c+b) are reversed from the previous state at ill's, and in the subsequent period, the signal becomes K so that C is input and supplied to T-FF3 and NAND game)4.5. .・When the operation starts from K, such as when the power is turned on, the state from the beginning is the same as that after time t in Fig. 5. When K is in the same state as the state after time t in Fig. 5, the output signal n of the Nant gate 1o becomes "1" IC. Because jOJK will not become like this, D-FF11 (7)
The signal o of the Q output does not change from "1" to rOJ, so the output signal p of T-FF-13 is kept at either "1" or "0" and the switch circuit 14 is also switched. I can't do it. - Therefore, according to this embodiment, when the signals of the Q outputs of T-FF'2 and 8 and the phase of j are opposite to each other, that is, the second'
When a super relationship is reached as shown in (9) and 06) in the figure, the switch circuit 14 automatically changes K by 9J. ) The phase difference between the subcarriers f and 5 is fixed at θ, and the operation will not continue until t when n and θ′ are reached, so the correct phase relationship can be maintained. subcarrier! Can be easily supplied.

FIG. 6 shows an embodiment of the switch circuit 14 in the embodiment of FIG. With this configuration, it is possible to easily obtain a switch circuit that operates reliably.

In the embodiment shown in FIG. 4, the output signal of the T-FF 2 is switched by the switch circuit 14, but the output signal of the T-FF 8 may be switched.

-17'j, In the above embodiments, the horizontal scanning clock pulse of the solid-state image sensor is shown as having two phases, but the present invention is not limited to this. It goes without saying that a clock pulse K having four or more phases is also applicable as long as it is double the number of phases.

As explained above, according to the present invention, the phase relationship of the subcarrier with respect to the horizontal scanning and scanning p-sku pulses of the solid-state image sensor is maintained in one mode, and the orthogonal phase relationship of one carrier wave is maintained from K. Since it eliminates the risk of changes due to repeated power-on, etc., it eliminates the drawbacks of conventional technology and always supplies subcarriers with the correct orthogonal phase relationship to a color television imaging device using a gated image element. Accordingly, it is possible to provide a synchronizing signal generating circuit that can obtain a color television signal with correct hue.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional example of a synchronization signal generation circuit;
Figures (1) to (18) are timing charts for explaining its operation, Figure 3 is a circuit diagram showing one embodiment of the synchronizing signal generation circuit according to the present invention, and Figure 4 is a circuit diagram showing another embodiment Z of the same. 5(1) to 5(7) are timing charts for explaining the operation thereof, and FIG. 6 is a circuit diagram showing one embodiment of the switch circuit. 1...Reference clock generator, 2.3, 8.13
...T7 lip 70 tube (T-FF), 6,7
．． 11...D7 lip 70 knob (D-FF), 4,5
．． 10°16~21... Nantes Gate, 12.
15... Inverter, 14... Switch circuit, a... Reference clock signal, f, l...
...Subcarrier, l, m...Clock pulse for horizontal scanning of the solid-state image sensor Fig. 1 Fig. 2 a8) Figure 5 y. Figure 6

Claims (1)

[Claims] (1) A subcarrier of a television signal and a 7t two-phase clock having a repetition frequency twice that of the subcarrier are generated by frequency division processing from the same reference signal. In the synchronization signal generation device for a solid-state imaging device, a phase synchronization means is provided for matching the division phase of the reference signal with respect to the subcarrier and the division phase of the reference signal with respect to the clock pulse, and Phase change of i11* transmission due to difference! A synchronization signal generation circuit characterized in that it is configured to prevent such occurrence. (2. In claim 1, the output of the 7-lip 70-tube that manually converts the reference signal is used as the input of the frequency divider circuit for generating the subcarrier and the input of the frequency divider circuit for generating the clock pulse. A synchronizing signal generating circuit characterized in that the synchronizing signal generating circuit is provided with a means for supplying the reference signal in common to the phase synchronizing means, and the means is configured to supply the reference signal in common to the phase synchronizing means. Compare the output phase of the 7 rigs and 70 tubes for subcarrier generation with the output phase of the 7 rigs and 70 tubes for clock pulse generation which input the reference signal,
A synchronizing signal generating circuit characterized in that means is provided for switching the output phase of one of these 7 liters and 2.70 tsubu depending on the comparison result, and the above-mentioned phase synchronization means is configured in the means.