JPS5832933Y2 - Half dot print control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a half-dot print control device that can form bar-dot timing signals in a dot-type printer with a simple configuration.

For example, as shown in FIG.
Example: This head has a head PH in which seven wire dots are aligned, and as shown in FIG. Wire dot WD is a drive unit PHO such as a magnet.

Driven by PHI, PH2, etc., the wire dot WD will impact the platen PN side.
Ink from the ink ribbon IR creates a form, car 1-'
It cannot be printed on CDs, etc.

The head also moves the platen PN according to the information indicating the printing position.
For documents, cards, CDs, etc., each line is moved by one line each time one line is printed.

The number of dots in one character is generally 7 x 5, but in order to improve character quality, it has been adopted to print half dots HD between full dots, as shown in Figure 1. There is.

The timing signal is required to print these half dots.

Therefore, conventionally, as shown in FIG. 2a, for example, a full dot timing signal
DTM is formed, a half dot timing signal HDTV is inserted in the middle, and these timing signals FD
Based on TM, H, and DTM, the magnet excitation signal FD for printing full dots is created as shown in Figure 2C.
It is known to drive wire dots by generating MG and a magnet excitation signal HDMG for printing half dots.

In this case, the period of the mechanical clock signal is, for example, 1 m.
Since it is about s, there is a half dot exactly in the middle.
Inserting the timing signal HDTV is difficult.

Further, FIGS. 3a" to 3e show time charts of other conventional examples, in which a counter or one-shot multivibrator is operated by the full dot timing signal FDTM shown in FIG. The signal CTR shown in the figure is generated, and its falling timing is set as a half-dot timing signal HDTM as shown in FIG. 3C.
Based on these timing signals FDTM and HDTM, magnet excitation signals FDMG and HDMG for printing full dots shown in FIGS. 3d and 3e are generated.

However, it requires a one-shot multivibrator or the like, which has the disadvantage of making the configuration complicated.

FIG. 4 is a block diagram of the main part of the conventional example, and the mechanical clock signal MCL is an OR gate OR, a one shot clock signal, and a one shot clock signal MCL.
The output signal of the gate OR becomes a data set signal of the register REG, a count start signal of the counter CNT, and a set signal applied to the set terminal S of the flip-flop FF.

The mechanical clock signal MCL has a period of, for example, 1 mS, and the clock signal CLK has a period of, for example, 80 nS.

The output signal of the one-shot multivibrator MSI is, for example, the signal shown in Figure 3, and the falling edge of this signal triggers the one-shot multivibrator MS2 to output a pulse signal. Added to OR game t-OR.

The output signal of this OR gate is half dot
The clock signal HDTM is generated, a half-dot date is set in the register REG, the counter CNT starts counting the clock signal CLK, and the flip-flop FF is set.

When the counter CNT counts the clock signal CLK during 1/2 of the bright period of the full dot timing signal, the output signal is set to "1" and is added to the reset terminal R of the flip-flop FF and the reset terminal of the counter CNT.
The flip-flop FF is reset, and the counter CNT is also reset.

Therefore, when the output signal of the flip-flop FF is set with full dot timing 1 word, the output signal of the flip-flop FF is as shown in FIG.
The magnet excitation signal FDMG is as shown in Figure 3e when set as a half dot timing signal.
The magnet excitation signal HDMG is shown in FIG.

This magnet excitation signal is applied to the AND gates G1 to G7, and the data set in the register REG is passed through the AND gates G1 to G7 to the driver circuits D1 to DV.
Added to 7.

Magnets MG1 to MG7 that drive the wire dots are excited by the power source 1E by the outputs of the driver circuits DV1 to DV7.

For example, when printing the character rAJ shown in Fig. 1 1)j,
The output terminals 4 to 7 of the register REG become 1" due to the first data from the character generator set in the register RBG by the full dot timing signal FDTM, and the output signal strength of the flip-flop FF is <8191 times,
That is, when the magnet excitation signal FDMG is l'', the driver circuits DV4 to DV7 are activated via the AND gates G4 to G7.
is operated, magnets 1-MG4 to MG7 are simultaneously excited by .delta., and the first row of four dots is printed.

The next half-dot timing signal sets the half-dot data from the character generator in the register REG, and only the output terminal 3 of the register REG becomes 1'', during which time the head is sent to the half-dot position. Therefore, one half dot is printed between the first column and the second column by the excitation of magnet MG3.

In the same manner, characters having a dot configuration similar to the 7×IO dots shown in FIG. 1 are printed.

However, it requires a one-shot multivibrator MSI, M82 with a different configuration, and it is not easy to set the output time.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to generate full-dot timing signals and half-dot timing signals with a simple configuration.

Examples will be described in detail below.

FIG. 5 is a block diagram of main parts of an embodiment of the present invention, and the fourth
The same reference numerals as in the figure indicate the same parts, and HD is a timing circuit for forming a half-dot timing signal by detecting the falling edge of the output signal of the flip-flop FF.

Further, the counter CNT uses the output signal of the timing circuit HD as a set signal, and also uses a signal inputted through the OR gate OR and delayed by the delay caused by the OR gate OR as a count start signal, and also as a data set signal for the register REG. It is.

FIG. 6 shows a time chart for explaining the operation of FIG. 5, and FIG. 6a shows the mechanical clock signal MCL.
is converted into a full dot timing signal FDTM via the OR game 1-OR. This full dot timing signal FDTM sets the full dot data from the character generator in the register REG, and also sets the full dot data from the character generator in the counter CNT. starts counting the clock signal CLK, and the flip-flop FF is set and its output signal becomes I''.

And when the counter CNT reaches the predetermined count content,
The output signal is added as a reset signal to the flip-flop FF, and the full dot timing signal F
I) The output signal of the flip-flop FF by TM becomes the magnet excitation signal FDMG for full dot printing shown in FIG.

The timing circuit HD indicates that the flip-flop FF has been reset and its output signal has fallen from "1" to on.
detects and outputs a pulse signal.

This pulse signal is applied to the reset terminal of the counter CNT and becomes the half-dot timing signal HDTM via the OR gate, and FIG. 6C shows this half-dot timing signal HDTM. It is.

And this half dot timing signal HI)T
Half dot data from the character generator is set in the register REG by M, the counter CNT starts counting the clock signal CLK, and the flip-flop FF is set.

When the counter CNT reaches a predetermined counter content, the flip-flop FF is reset by its output signal.

At this time, the timing circuit hD outputs a pulse signal for detecting a falling edge, which resets the counter CNT and also adds it to the OR gate OR.Since the timing matches the mechanical clock signal MCL,
The output signal of the OR gate OR becomes the full dot timing signal FDTM.

This can be done by setting the count time of the clock signal CLK to be very slightly shorter than 1/2 of the period of the mechanical clock signal MCL, so that the falling timing of the magnet excitation signal HDMG for printing half dots can be adjusted. This means that the timing of the mechanical clock signal MCL coincides with the timing of the mechanical clock signal MCL.

Therefore, the flip-flop FF set by the half-dot timing signal HDTM
The output signal of the magnet excitation signal HDMG is as shown in FIG. 6d, and the output signal of the flip-flop FF is, as shown in FIG. 6e, a full-dot timing signal FDTM and a half-dot timing signal HDTM.
The data set timing of the register REG is 0'', resulting in a magnet excitation signal with a width of time T.

As explained above, the present invention stores data in the register RE.
Full dot timing signal FD for setting to G
TM and half dot timing signal HDTM,
It can be formed by a counter CNT, a flip-flop FF, a timing circuit HD, and an OR gate OR, and does not require a one-shot multivibrator as in the conventional example, which has the advantage of simplifying the configuration.

The timing circuit HD can be configured with a differential circuit that detects the falling edge of the output signal of the flip-flop FF. Such a configuration is well known and is extremely simple compared to a one-shot multivibrator. All it takes is the configuration.

[Brief explanation of the drawing]

Figure 1 a ``C is an explanatory diagram of the head, characters printed by half dots, and the printing mechanism, Figure 2 a = d and Figure 3
Figure a ``'-e is a time chart for explaining conventional operation,
FIG. 4 is a block diagram of the main parts of the conventional example, FIG. 5 is a block diagram of the main parts of the embodiment of the present invention, and FIG. 6 is a time chart for explaining the operation of the embodiment of the present invention. REG is a register, OR is an OR gate, CNT is a counter, FF is a flip-flop, HD is a timing circuit,
MCL is a mechanical clock signal, CLK is a clock signal, 01 to G7 are AND gates, DVI to DV7Ili
The driver circuits M()1 to MG7 are magnets.

Claims (1)

[Scope of utility model registration request] A flip-flop that outputs a magnet excitation signal for controlling the excitation time of the magnet that drives the wire dot; a timing circuit that detects the fall of the output signal of the flip-flop and outputs a pulse signal; An OR gate which adds an output pulse signal and a mechanical clock signal, sets the pulse signal as a half-dot timing signal, and sets the mechanical clock signal as a full-dot timing signal, and controls the flip-flop with the output signal of the OR gate. Along with setting
a register for setting full dot data using the full dot timing signal of the output signal and setting half dot data using the half dot timing signal; and an output pulse signal of the timing circuit. is used as a reset signal, the output signal of the OR gate is used as a count start signal of a clock signal, and a counter outputs a reset signal of the flip-flop according to a predetermined count content of the clock signal. half·
Dot print control device.