JPS583267A - Manufacture of logic circuit - Google Patents

Abstract

PURPOSE:To shorten a delivery term of the finished product by forming a plurality of MOSFETs on a substrate and a region not affected by a client pattern and deciding the pattern of a logic circuit by the specification from a user at the rear period of the steps. CONSTITUTION:The first insulating film 9 is formed ona substrate 8, and the active regions of MOSFETQ1-QL are opened. Then, an ion implanted layer 11 which is not affected by the influence of a client pattern is formed. Gate regions 14-17, source and drain regions 18 and wiring N<+> type diffused layer 18 are formed on the second film, and the third insulating film 19 is covered thereon via a polysilicon layer 13 on the second film. Shortcircuit layer 24 and aluminum electrode 22 are formed via holes 20, 23 by using the client pattern from here to complete the logic circuit. In this manner, the delivery term can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a nine-arbitrary circuit that enables shortening of delivery time.

Logic circuits as shown in FIGS. 1 to 4 are generally known.

Such a logic circuit is also shown in Japanese Patent Publication No. 56-3688. FIG. 1 is a partial plan pattern diagram of this logic circuit. In addition, Figure 2 is an equivalent circuit diagram corresponding to Figure 1, Figure #E3 is a cross-sectional view of Rattan 1 diagram taken along the line I-I', and Figure 4 is a logic diagram of the pattern diagram in Figure 1. There are nine things.

According to FIGS. 1 to 4, in the -m circuit, a gate insulating film (2) and a gate electrode (3) are formed on a Ps substrate (1), and a KN+ region (4) between the gate electrodes is formed by diffusion. It consists of According to the circuit shown in FIG. 1, MO8 (Metal Oxide) shown in FIG.
8emiconductor)) Rungis' Qll
"Q21 ' Qll eQll・Qo・qsx
Since nine N are connected in series (the load transistors are not shown), a multi-input N as shown in Figure 4 is possible.
It is made up of two AND circuits connected in series.

Here, the required number of gate inputs for these logic circuits is set according to specifications from the user for various purposes.

For example, in order to eliminate the function of the MOS transistor Qzz and make it appear as if the number of manpower is reduced by one, the source (4□) and drain (4□) of the MOS transistor Q22 are short-circuited by the t ion-implanted layer (7).

Logic circuits of these configurations have conventionally been formed by the manufacturing process shown in Figures S to (G)K.

However, following these manufacturing processes has the drawback that the above-mentioned ion implantation process is performed at an early stage of the Quafer process, resulting in a delay in delivery.

That is, the logic circuits shown in FIG. 5(4) to n are as follows.

Enhancement type MO8) transistor Q8,・Q,□
To form these, first, a field insulating film (9) is provided by opening a predetermined active region on a P-type semiconductor substrate (8) as shown in the fifth part, and the dks customer pattern is Accordingly, the process starts by simultaneously forming the ion implantation layer α for short-circuiting the transistor and the depletion region qυ, but after receiving the customer pattern, the following steps (1) to (B) are performed. The process has to be advanced, which significantly delays delivery to the user.

That is, the above logic circuit has an ion implantation layer (It)Ql)
(1) A thin first layer covering the exposed surface of the substrate as shown in the fifth step.
(1) A polysilicon layer Ql of Isl is formed on the upper surface of the insulating film I.
& formed, (...) the first polysilicon layer formed in the 5th step (
11 to PgP (photo &sgraving Pro
cess: Photo-etching process, hereinafter abbreviated as P11P. ) and the dirt area α◆■■ as shown in 111115WA@
η must be formed.

- Jiu, the first polysilicon layer after this PgP (1!I'
) is used as a mask to remove the first insulating film by etching to form a gate insulating film (12'). A territory must be formed.

At this time, the first polysilicon layer (13'
) is made into an N-type conductor.

(B) Then, as shown in Figure S (c) K, the entire base steel must be covered with the second insulating film part, and *I t, as shown in Figure 5 OJK. Aluminum electric f
! A contact hole (to be described later) must be formed in the portion from which the material (described later) is taken out.

Furthermore, as shown in Figure 5 (G), BP8G
(Bron phospho-8i1icate G
lass ) film (2I) must be formed.

(Incorporated) Then, the BP8GIE (2) is heated to cause it to sag and form a surface smoothing layer.
After performing step-spinning measures (described later), and forming a new 7'tK electrode contact hole (2)
form.

A Then, as shown in Figure 5 (g), five aluminum F electrodes (2) must be formed.

The present invention relates to a method of manufacturing a logic circuit devised in view of the above-mentioned drawbacks, and its purpose is to shorten the delivery time of the circuit.

First, its feature is that the pattern of the logic circuit is determined in the latter half of the process, and its structure will be clear from the following explanation.

Figures 6 to VIK show an embodiment of the present invention.

IIG Figures 4-(g)r1 This is a schematic process diagram of the logic circuit drawn corresponding to Figure 5(4)-(g).
) to (g) are all given the same reference numerals.

A logic circuit according to the present invention is manufactured as follows. First, as shown in the sixth column, a film thickness of 8,000 mm is applied to a semiconductor substrate (8) of a -field type (containing Pal impurities).
A thick insulating film (9) of -15,000 angstroms is formed.

Next, MOS transistors Q11'Q21 and Q3
The active region constituting 1.QL is opened. Then, an area aυ is formed in the depression 171 that acts as a load by ion implantation. Note that the N region formed by ion implantation at this time is only the region 1, for example, the load area 1 peripheral circuit, which is not affected by the customer pattern. The following explanation will be given while assigning process numbers according to the conventional example.

That is, the above logic circuit is formed after forming the ion implantation layer +11).

(1) The film thickness as shown in Prisoner 61 is SOO ~ 100
A thin second insulating film a having a thickness of 0 angstroms is provided.

(■) Then, layer it on top to make the film thickness 3000~4.
A polysilicon layer AS having a thickness of 1,000 oz. is formed.

(-) Then, after that, P is applied to the polysilicon layer I.
By performing 13P, the l'-t11 region [4) (19 (lIclf) t' * is formed as shown in Figure 6.

(iv) Next, using the above-mentioned polysilicon pattern as a mask, the 12-density film in the non-41 portion is removed.

Next, by performing vapor-solid phase diffusion using POCI, regions of other conductivity types, that is, source/drain regions (II ill) and N diffusion layers tIII for wiring, are created. , the polysilicon layer (13') which has been subjected to PNP is made into a four-electrode N8.

M) Then, as shown in FIG. 6 (Q), CVD-840, (ChemIc
alVaper Deposition -8i0.
;Chemical vapor deposition K Yo also 5I02 film. ] 200 membranes
It is provided with a thickness of 0 to 6000 angstroms.

(Vl' Then use the customer pattern from here.

This customer pattern is a mask for forming the ion implantation layer (7) shown in Figures I11 to 113FIA, and the ion implantation layer (7) shown in Figures 5 and 6. Contact hole cf shown in FIG.
11 (to) is provided. and the exposed surface of the base (20')
(23') is formed.

n' Next, from the contact hole m@, for example, P
Gas phase solid phase diffusion is performed using OCI, and a short-circuit layer @ made of other mold engravings as shown in Fig. 6 (g) is provided. The conditions for providing this shorting layer (to) are the elongation of the impurity layer (generally
It is expressed as i. ) K Therefore, it is assumed that punch-through of the source and drain is extended to a minimum value Xj at the normally used voltage.

(IX) Next, as shown in FIG. 6, a fourth insulating film, that is, a BP8G film is formed.

(x) Then, it is heated and sagged to form a surface smoothing layer.

- Then, perform pgr to form aluminum contact holes.

-Then, the logic circuit is completed in this way by forming five electrodes (to) as shown in Figure FC6 (0).

Note that the method for manufacturing the logic circuit shown here uses cross-sectional views, so it is difficult to understand the planar configuration.

Therefore, the planar configuration will be explained using Figure 7-0.

Figure 11I7 shows a wafer in which the thick first insulating film (9) is selectively etched to expose the base surface (to) of a part of the column (active region). Laminated on this upper surface is a thin second absolute rut ii1 [(not shown),
A polysilicon layer (not shown) is also formed. Then, as shown in FIG. 7(6), by applying PEP to the polysilicon layer, polysilicon 4 (13') is left in the row and row portions arranged orthogonally to the column line portions.
Then, using this polysilicon layer (13') as a mask, the insulating film of the irises 2 is etched. And column 4Is
The substrate surface (to) is exposed.

The exposed surface VC of the substrate forms, as shown in FIG. 7 (q), an N-type region (to) which is oppositely conductive and conductive to the substrate. At this time, poly7 recon m (13') is activated.

The gate arrangement becomes @(13"), and MOS゛) transistor Q, 1゜Q31 is formed. This polysilicon layer (13") is formed.
3") The substrate is then covered with a second insulating film Al as shown in FIG.
□ is set, and a contact hole (c) for shorting the north drain is formed as shown in Fig. 7 (see Fig. 7).

Next, as shown in FIG. 7, phosphorus is diffused from the contact hole (toward) using POCI to form an impurity region of another conductivity type. Note that the impurity diffusion conditions at this time are such that the impurity diffusion area (to) extends in the lateral direction (XD causes minimum source/drain punch-through at the normally used voltage, and requires elongation at -it). At this time, the lateral extension (XI) is connected to the contact hole (to) to prevent the influence on other transistors.
The pattern is set when forming the pattern. Next, in a later step, a contact hole (to) is provided at a portion Vζ where an aluminum contact is to be made, and its immersion is performed.
A BPSG II (not shown) is provided. And J#! There is a contact hole (
To) The logic circuit is completed by providing t-&ke and Alha-umden 4ii-.

As is clear from the table above, the present invention and the conventional example are based on the delivery time (blank below). In the case of the conventional method, it takes at least (1 )
~ (b) process, that is, 11 processes are required, whereas according to the process of the present invention, ← 1 ~ rest process, that is, 7 processes are required. Therefore,
According to the present invention, it is possible to provide a method for manufacturing a logic circuit that can reduce the number of processes by 4 times and shorten the delivery time by 5 to 7 days compared to the conventional method.

Incidentally, FIG. 8 shows a logic circuit according to the present invention, and FIG. 9 shows its equivalent circuit diagram, but these are specifically a mask ROM and a decoder, and they are ordinary It is a logic gate.

As described above, according to the present invention, it is possible to provide a method for manufacturing a logic circuit that can shorten the delivery time, but the present invention is not limited to the embodiments presented herein, but also includes modifications within the scope of the "claims". It is clear that adding scales. For example, 96
The short-circuiting layers shown in Figure 7 or η in Figure 7 may be short-circuiting materials, and the impurity source for forming these short-circuiting layers is a doped substrate containing phosphorus. It's good to be there.

[Brief explanation of the drawing]

Figure m1 is a plan pattern diagram of a conventional logic circuit, Figure 2 is its equivalent circuit diagram, Figure 3 is a cross-sectional view of Figure 1 taken along line I-I', and Figure 4 is a ts1 diagram. Logic diagrams, Figures 5--n are conventional process diagrams for manufacturing the logic circuit shown in Figure 1, and Figures 6-4-(g) are for manufacturing a logic circuit with the same functions as in Figure J1. A manufacturing process diagram of the present invention according to the present invention, Figures 7-(q is a manufacturing process diagram explaining the present invention from a two-dimensional perspective, Figure 8 is a cross-sectional view showing a logic circuit according to the present invention, and Figure 9 is an equivalent circuit diagram for Fig. 8. 8... Semiconductor substrate (P type) 9...
......Insulating film 12' of i41...
...Second insulating film 13'...
・Polysilicon layer 18 ......N+ impurity region 24 ...... Short circuit layer (impurity region) 19 ......Third insulating film 21・
......Fourth insulating film 20, 23...
...Contact hole 22 ......Aluminum 1 to 11 (7317) Representative patent attorney Norichika Denshin (and 1 other person) ゛,. Fig. 1 Fig. 2 Fig. 3 ￥4 Fig. VJ6 Fig. fI 8 Draft procedure amendment (voluntary) Drunkenness 5m, 9.778 Commissioner of the Japan Patent Office 1, Indication of Case Patent Application No. 100656/1983 2, Title of Invention Logic m circuit manufacturing method 3, relationship with the amended case Patent Applicant (307) Tokyo Shibaura Electric Co., Ltd. 4, Agent 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo 100 Tokyo Shibaura Electric Co., Ltd. In the office (7317) Patent attorney's aide telegraph +1) "It will be made by other mold engravings" in the 9th true line 3 of the specification
is corrected to "becomes of another conductivity type." 12) Ming + Il Book 111, line 18 (7) rW
J t r121) Correct as J. (3) Drawings, Figures 4 and 7 (q, Figure 9 are corrected as shown in the attached sheet).

Claims (1)

[Claims] Step 1 of forming a thick ill insulating film on a semiconductor substrate having a conductivity type of 1111, selectively etching the first insulating film to expose the substrate surface of the column line portion, and etching an insulator on the substrate. Thereafter, a process of laminating a thin second insulating film/polysilicon layer, and leaving the second insulating film/polysilicon layer on the row line portions disposed perpendicularly to the column lines and removing the rest. a step of forming an impurity region of a second conductivity type on the exposed surface of the substrate using the first insulating film and the second insulating film as masks; a step of forming a third insulating film, a step of setting a short-circuiting transistor part according to the required program and exposing the above-mentioned impurity region constituting this transistor, and a step of forming a third insulating film in order to short-circuit the exposed impurity region. A step of diffusing an impurity having a more striped 2 conductivity type, a step of forming a fourth insulating film on the substrate after this diffusion, and forming a contact hole for forming an external S extraction electrode from the impurity region. and a step of forming an external filling electrode.