JPS5832446A - Formation of silicide - Google Patents
Formation of silicideInfo
- Publication number
- JPS5832446A JPS5832446A JP13096481A JP13096481A JPS5832446A JP S5832446 A JPS5832446 A JP S5832446A JP 13096481 A JP13096481 A JP 13096481A JP 13096481 A JP13096481 A JP 13096481A JP S5832446 A JPS5832446 A JP S5832446A
- Authority
- JP
- Japan
- Prior art keywords
- silicide
- melting point
- layer
- point metal
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Abstract
Description
【発明の詳細な説明】
本発明は高融点金属と多結晶シリコンとを反応させてシ
リサイドを形成するシリサイドの形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming silicide by reacting a high melting point metal with polycrystalline silicon to form silicide.
近年集積回路の集積度同上のため、抵抗素子として比較
的高抵抗であるシリサイドが用いらｎるようになって米
ている。そこでシリサイド層の基板上への形成方法が問
題になるが、現状とじてに。In recent years, as the degree of integration of integrated circuits has increased, silicide, which has a relatively high resistance, has come to be used as a resistive element. Therefore, the method of forming the silicide layer on the substrate becomes an issue, but as it stands now.
スバタリング法でシリサイドを基板上へ蒸着する方法が
とられており、との方法では装置の保守やスバタリング
時間が力為雇りかかると云う問題点があっπ・
本発明に斯る点ｒｃ鑑みて為さ庇たものであって短時間
でシリサイド層を形成する方法を提供するものである。A method has been adopted in which silicide is deposited on a substrate by a sputtering method, but this method has the problem that maintenance of the equipment and time required for sputtering are labor intensive. The present invention provides a method for forming a silicide layer in a short time.
以下図！ｉｉＫ基づｈて本発明を詳述するのまずシリコ
ン基板（１）上に不純物１例えば燐を約１０’ｉｆｉ／
ａｘ！ドープした多結晶シリコン１２）の層１ｓｏｏ。Figure below! The present invention will be described in detail based on K. First, impurity 1, for example phosphorus, is added to a silicon substrate (1) at a rate of about 10'ifi/.
ax! A layer 1soo of doped polycrystalline silicon 12).
ｋの厚みで減圧ＯＶＤ法を用いてつくる・この多結晶シ
リコン（２；表面ｒｃ宅リすデン１３）等の高融点金属
１ｉ０ＶＤ法で２６０ＯＡ厚に形成する・この図を第１
図に示す・絖いてモリブデン表面から不純１５
物である燐イオンｔ Ｉ Ｘ １０ ｅＬｏｅｅ／ｌ
ｓの割合でイオン注入法を用いて１００ ｘ＊ｖ のエ
ネルギーでモリブデン（３）及び多結晶シリコン（２１
へ注入する。次［９００’Ｃのｉ１票雰囲気中で３０分
間熱処Ｉｌ１行うと、シリサイド（４１がｉ［２図のよ
うにモリブデン（３）と多結晶シリコン１２）との界面
からモリブデン（３）側へ５００ム乃至１０００ Ａ形
成される・さらに上記方法で注入する燐イオンの量ｔ５
×Ｓ
１Ｑ Ｌｏｓｓ／ｌ＊ に増加ぜしめると形成される
シリサイド（４）の厚さは第３図に示すように：１６０
０ンを注入しない状態で前記方法と同一条件の熱処理ｔ
−施した時に形成さｔｔ７ｙシリサイドの厚さば１０Ｏ
Ａ乃至２００ムの厚さしかなかった。このように燐イオ
ンの注入量を増やすと、シリすイドの形成量が増大する
・換言するとシリサイドの形成遮電が速くなる。従って
上記方法を利用する事に依って形成されるシリサイド讐
の厚みげ不純物である燐の注入量を制御する手に依って
賜コントロールする事が出来る。This figure is made using the low pressure OVD method to a thickness of
As shown in the figure, phosphorus ions which are impurities from the surface of molybdenum t I X 10 eLoee/l
Molybdenum (3) and polycrystalline silicon (21
Inject into. Next, when heat treatment Il1 is performed for 30 minutes in an atmosphere of 900'C, silicide (41) moves from the interface between molybdenum (3) and polycrystalline silicon 12 to the molybdenum (3) side as shown in Figure 2. The amount t5 of phosphorus ions to be formed and further implanted by the above method is 500 μm to 1000 A.
×S 1Q Loss/l* The thickness of the silicide (4) formed is 160 as shown in Figure 3.
Heat treatment under the same conditions as the above method without injecting 0.
- Thickness of tt7y silicide formed when applied: 100
It was only A to 200mm thick. Increasing the amount of phosphorus ions implanted in this manner increases the amount of silicide formed, or in other words, speeds up the formation of silicide. Therefore, by using the above method, it is possible to control the injection amount of phosphorus, which is a thickening impurity of the silicide formed.
次に本発明シリサイド形成方法を用いて多結晶シリコン
とモリブデンの２層構造の配線にシリサイドの抵抗を選
択的に形成する方法を配す。壕ずシリコン基板ｆ５１
［ｉｌ化膜（６）を形成し、酸化膜（６）上に減圧ＯＶ
Ｄ法で多結晶シリコンｔ７１ｔ−成長させ。Next, a method of selectively forming a silicide resistor in a wiring having a two-layer structure of polycrystalline silicon and molybdenum using the silicide forming method of the present invention will be described. trenchless silicon substrate f51
[An oxide film (6) is formed and a reduced pressure OV is applied on the oxide film (6).]
Polycrystalline silicon t71t- was grown using method D.
さらにモリブデンＴ８１ｉＣＶＤ法で形成し、燐イオン
注入のマスク（９）ｔ−酸化膜でつ（Ｄ、モリブデン（
８）の表面から燐イオンを注入する・この状ｍｔ−第４
図に示す、この状態でマスク（９）ヲエッチングし熱処
理會行うと第５図のよりに燐を注入した一所゛にシリサ
イドｈａか形成されるので、モリブデン（８）工りなる
導電Ｗ＆にシリサイド（１（ＩＫよって分断さｆｔ。Furthermore, a molybdenum T81i CVD method is used to form a mask (9) for phosphorus ion implantation.
8) Inject phosphorus ions from the surface of the mt-4th
When the mask (9) is etched and heat treated in this state as shown in the figure, a silicide ha is formed in the place where phosphorus is injected as shown in Figure 5, so it becomes a conductive W& made of molybdenum (8). Silicide (1 (divided by IK ft.
シリサイドＱ（ｌが抵抗体として働く工うｒｃなる。最
後に絶縁膜１１１１及び了ルミ＊＊ａａａ；ａｔ設ける
と、この両アルミＩＥ極ｕ３１２関ｒｃ形成されたシリ
サイド四の童に係る大きさの抵抗値の抵抗が得られる。The silicide Q (l) acts as a resistor.Finally, when an insulating film 1111 and an aluminum **aaa;at are provided, the size of the formed silicide 4 The resistance value of resistance is obtained.
このように任意の一所に適当な童の燐イオンを注入する
事に依って該箇所に任意の抵抗値の抵抗体を得る手が出
来る・
以上のＷＪ＜本発明シリサイド形成方法は多結晶シリコ
ンと高融点金属と、Ａ２層構造にした後高融点金属表面
から高融点金属及び多結晶シリコンへ不純物を注入し、
熱処理をする事に依って多結晶シリコンと８；融点金属
とから成るシリ、サイド層を形成しているのでシリサイ
ド形成時間の短縮が計れ。In this way, by implanting appropriate phosphorus ions into an arbitrary location, it is possible to obtain a resistor with an arbitrary resistance value at that location. and high melting point metal, and after forming A2 layer structure, impurities are injected into the high melting point metal and polycrystalline silicon from the high melting point metal surface,
By performing heat treatment, a silicide side layer consisting of polycrystalline silicon and a metal with a melting point of 8°C is formed, so that the silicide formation time can be shortened.
抵抗体上使用する集積回路の量産に効果が上げられる。This is effective for mass production of integrated circuits used on resistors.
さらに、注入する不純物を選択的に注入する亭に依って
任意の箇所に抵抗を形成する事が可能となり、配線上の
任意の箇所に任意の抵抗値の抵抗体を得る平が出来る。Furthermore, by selectively implanting impurities, it is possible to form a resistor at any location, making it possible to obtain a resistor with any resistance value at any location on the wiring.
蕗１図乃至第３図に本発明方法を工程順に示した要部断
面図、１１Ｉ！４図乃至ｊｉＩ６図は、本発明方法を用
いて配線に選択的にシリサイドの抵抗を形成する工程を
示す要部断ｌｆｉ図である・１１）１５１・・・シリコ
ン基板、 １２１１７１・・・多結晶シリコン。
４３）ｔ８１・・・モリブデン、（４１賎・・・シリサ
イド。
第１図
第２図
第３図
第４図
１１
第５図
２０９−Fushimi Figures 1 to 3 are cross-sectional views of main parts showing the method of the present invention in the order of steps, 11I! Figures 4 to 6 are cross-sectional views of main parts showing the process of selectively forming silicide resistors on wiring using the method of the present invention. 11) 151...Silicon substrate, 121171...Polycrystal silicon. 43) t81... Molybdenum, (41 賎... Silicide. Figure 1 Figure 2 Figure 3 Figure 4 Figure 11 Figure 5 209-
Claims (1)
、高融点金属表面から高融点金属及び多結晶シリコンへ
不純物を注入し１次（熱処理する亭に依って、多結晶シ
リコンと高融点金属とから成るシリすイド層を多結晶シ
リコンと高融点金属との界面から成長言ゼる亭を特徴と
したシリサイドの形成方法。 ２、特許請求の範ｌ！Ｉ第１頂に於いて注入する不純物
の量ｔ−変化させる亭に依って形にされるシリサイド層
の厚みを制御する亭ｔ４１黴としたシリサイドの形成方
法。 ３）特許請求の範ｉ！Ｉ第１項、又は第２項に於いて、
不純物を選択的に注入する事に依ってシリサイド層を選
択的に形成する事ｔｑ！＃黴としたシリサイドの形成方
法。[Claims] 1) After forming two layers of polycrystalline silicon and high-melting point metal, impurities are injected into the high-melting point metal and polycrystalline silicon from the surface of the high-melting point metal, and primary (depending on the heat treatment) A method for forming a silicide characterized by growing a silicide layer consisting of polycrystalline silicon and a high melting point metal from an interface between the polycrystalline silicon and the high melting point metal. 2. Claims l!I A method for forming silicide using a method of controlling the thickness of a silicide layer formed by varying the amount of impurity implanted in the first layer. 3) Claims i! In paragraph 1 or paragraph 2,
Selectively forming a silicide layer by selectively implanting impurities tq! #How to form moldy silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13096481A JPS5832446A (en) | 1981-08-20 | 1981-08-20 | Formation of silicide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13096481A JPS5832446A (en) | 1981-08-20 | 1981-08-20 | Formation of silicide |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5832446A true JPS5832446A (en) | 1983-02-25 |
| JPH025298B2 JPH025298B2 (en) | 1990-02-01 |
Family
ID=15046735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13096481A Granted JPS5832446A (en) | 1981-08-20 | 1981-08-20 | Formation of silicide |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5832446A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5013686A (en) * | 1987-09-30 | 1991-05-07 | Samsung Electronics Co., Ltd. | Method of making semiconductor devices having ohmic contact |
| US6323528B1 (en) | 1991-03-06 | 2001-11-27 | Semiconductor Energy Laboratory Co,. Ltd. | Semiconductor device |
-
1981
- 1981-08-20 JP JP13096481A patent/JPS5832446A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5013686A (en) * | 1987-09-30 | 1991-05-07 | Samsung Electronics Co., Ltd. | Method of making semiconductor devices having ohmic contact |
| US6323528B1 (en) | 1991-03-06 | 2001-11-27 | Semiconductor Energy Laboratory Co,. Ltd. | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH025298B2 (en) | 1990-02-01 |
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