JPS5832431B2 - Data aggregation method for online system using electronic cash register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data aggregation method for an online system using an electronic cash register.

An online system using electronic cash registers has multiple child cash registers 1-L as shown in Figure 1.
1-2. ... 1-n and the parent capper/yu register 2 are electrically coupled via the transmission line 3, the data is aggregated from each child register to the parent register, and the aggregated data is externally outputted by an output device 4 such as a printer. I am trying to output it.

Conventionally, in such an online system, as shown in the figure, cumulative data A1. B1. Four summators M11 with C, , Dl
．． M, 2. M13. M, 4 are provided, and cumulative data A2 1 B2 1C to be aggregated in child register 1-2
Four totalizers M2□2M2□ storing 2, D2.

M23 t M24 are provided, ... - child register i
-4 totalizers Mn1 storing cumulative data AnyBn, Cn, Dn to be totaled in n) Mn2, Mn3
When 1Mn42 is provided, each child register 1-1, 1-2 . . . . When the parent register 2 aggregates accumulated data from 1-n, the parent register has a number of buffer memories BF1 corresponding to each child register.

BF2,...BFn, four cumulative totalizers S1 corresponding to the four totalizers provided in each child register
, B2, B3, B4, and a totalizer T, first, a transmission command is output from the parent register 2 to the child register 1-1, and the accumulated data A1 is output from the child register 1-1 and stored in the buffer memory IJBF. , followed by child register 1
-2, outputs the cumulative data A2 from its child register 1-2, and outputs the buffer memory IJBF, Jζ.
. . . Finally, a transmission command is output to the child register 1-n to cause the child register 1-n to output the accumulated data An and store it in the buffer memory BFn.

In this state, parent register 2 is used for each buffer memory IJB.
Data A stored in F1, BF2,...BFn
1. A2. . . . An is subjected to arithmetic processing of ΣAn and is stored in the cumulative totalizer S1.

When this process is completed, the parent register 2 sequentially outputs the transmission command again to each child register 11, 1-2, . . . 1-n, and the cumulative data B1, B2, B2,
...Bn sequentially to each buffer memory BF1゜BF2
, . . . BFn and then performs arithmetic processing on □Bn and stores it in the cumulative totalizer S2. Hereinafter, such processing is performed on the cumulative data C1, C2, . . . Cn, and so on.

Also do this for B2 and D n, and finally ΣAn+ΣB
n+ΣCn+ΣDn is calculated and the result is stored in the totalizer T, and each cumulative totalizer S1. S
2, B3, B4 and the contents of the totalizer T are output to the device 4.
I was trying to output it with .

However, in this data aggregation method, the parent register must output a transmission command to each child register individually, and the output must be repeated as many times as the cumulative data totalizers provided in the child registers. There is a drawback that the number of command outputs associated with data aggregation increases, which increases the data aggregation time.Also, the transmission line and buffer memory of the parent register are occupied for a long time, so the effective usage efficiency of the transmission line and buffer memory is reduced. There was a drawback that the value decreased.

This invention was devised to eliminate these drawbacks, and provides an electronic cash register that can shorten data aggregation time and improve the effective use efficiency of the transmission line and the buffer memory of the parent cash register. The purpose is to provide a data aggregation method for online systems.

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 2, 1l-Lll-2,...11-n are child cache registers, 12 is a parent cache register, and transmission lines 13-C13-2,...1 are connected between each child register.
3-(n-1), and the child registers 111 and 11-n at both ends thereof are connected to the parent register 12 by transmission lines 14-1 and 14-2 to form a closed transmission loop. is forming.

The child register 11-1 contains cumulative data AI to be accumulated.
,B1.

Four totalizers M112M1□ storing C1 and Dl.

M13. M14. is provided, and the child register 112 has cumulative data to be aggregated A2 > B2 t C2
>Four summators M21 j M222 storing B2
M232M24 are provided, -- the child register 11
-n has 4 totalizers M n12Mn95M
n37Mn4 is provided.

The parent register 12 includes the child registers 11-1 and 11.
-2. . . . The number of buffer memos IJBF1.corresponds to the number of 11-n. BF2゜BFn totalizer T and output device 1
5 is provided.

Each of the child registers 1l-LIL-2, . A keyboard 22 for externally inputting data, signals, etc.
2. Programs for the CPU 21 to perform various control operations based on human input signals are set in the glROM (
read-only memory) 23, and the aforementioned four summators M(1 to n).

Various memories for storing variable data such as M (1 to n) 22 M (1 to n) 32 M (1 to n) 4 are formed, and the above CP
A RAM 24 is provided which is controlled by U21.

Further, each of the child registers 1l-L11-2, 11-n includes a display 25 that displays processing data controlled by the CPU 21, a printer 26 that is also controlled by the CPU 21 and prints the processing data, and the CPU 2.
1 and the aforementioned parent register 12 and data,
A transmission control device 27 for communicating signals is provided.

As shown in FIG. 4, the parent register 12 includes a CPU (Central Processing Unit) 28 and a ROM (Read Only Memory) 2 which have the same functions as the circuits of the child registers described above.
9, a keyboard 30, a display 31, and a printer 32 are provided.

Note that the display 31 and printer 32 form the output device 15.

The parent register 12 also includes the buffer memory BF mentioned above.
1, BF2...BFn are formed, and the CPU 2B
B-RAM (Buffer Random) controlled by
access memory) 33, the above-mentioned interface unit T, etc. are formed, and the S-RAM (
random access memory) 34 and the above CP
All the child registers 1l mentioned above controlled by U28
-L11-2. ... 11-n, and a transmission control device 35 for transmitting data and signals.

The parent register 12 is connected to each of the child registers 11-1゜11.
-2, ・11-H each totalizer M(1 to n) 1゜M(1
~n) 22M (1~n) 32M (1~n) 4, first the CPU 28 calculates the data from the transmission control device 3.
5, transmission lines 14-1 to 13-1 to 13-2
～...13-(n-1), start address data, word length data, m-step data specifying an address m steps from the start address, code data indicating that the word length is the same even when m steps are taken. , number data indicating the number of data and addition instruction code data are all stored in child registers 11-1, 11-2 .・・・
- I am trying to send it to 11-n.

Therefore, for example, in the RAM 24 of the child register, four totalizers M(1~n)1°M(1~n
)22M(1~n)32M(1~n)4 is formed. In the operation instruction from the parent register 12, the start address data specifies address 8000, the word length data specifies 16 digits, and m The step data specifies the fourth step, and the number data specifies four steps.

Each child register that receives this operation command via the transmission control device 27 controls the RAM 24 with the CPU 21 to execute the operation (addition) of data A + data B + data C + data D, and the result is formed in the RAM 24. The data is stored in a buffer memory (not shown).

Next, the parent register 12 is connected to each of the child registers 1l-L1.
1-2. ...Sends a data transmission command to 11-n.

As a result, first the child register 11-1 becomes Σ1=A1+B1
+C1+D1 data is output to the transmission line 13-1.

Subsequently, the child register 11-2 is connected to the data Σ1 of the child register 111 in the previous stage, and outputs the data Σ2=A2+B2+C2+D2 to the transmission line 13-2.

Therefore, data of Σ1°Σ2 is transmitted to the transmission line 13-2.

Thereafter, by performing data processing in this manner, the transmission line 13-(n-1) receives Σ1. Σ2. ...Σ(n
The concatenated data of l) is transmitted, and further the child register 11-
The data of Σn are connected by n and sent to the parent register 12 via the transmission line 14-2. . . . Σn concatenated data will be transmitted.

Note that each child register 11-1, 11-2 . ...11-
Data transmission in n is performed by controlling the RAM 24 and the transmission control device 27 by the CPU 21.

The parent register 12 receives the concatenated data Σ1. transmitted via the transmission line 14-2. Σ2. ...Σn transmission control device 3
5, and separates the concatenated data to each buffer memory BF1, BF2.

...Stored in BFn.

When this import is completed, each child register 1l-L1
1-2. ...11-n, and sends a reception end signal to each buffer memory BP,, BF2, ...'B
Fn data Σ1゜Σ2. . . . Σn is subjected to arithmetic processing of Σ1+Σ2 . . . +Σn by the CPU 28, and the total sum data is stored in the total summator T.

Finally, the parent register 12 prints the total data of the totalizer T on a receipt or the like using the printer 32 and displays it on the display 31.

This series of parent registers 12 and each child register 1l-L11
-2. . . . The process of transmitting data and signals to and from 11-n is shown in a flowchart as shown in FIG.

In this way, from the parent register 12 to all the child registers 11-1,
11-2. ...For 11-n, start address data, word length data, m step data, code data,
A common operation instruction consisting of 6 pieces of data including count data and addition instruction code data is transmitted once and all child registers 11-
1, 11-2° . . . 11-n is subjected to addition processing of a plurality of accumulated data to be accumulated in advance, and then all child registers 11-1, 11-2. ... Since the transmission command is sent to 11-n and the added data from all child registers is totaled, the parent register sends the command to all child registers individually and repeatedly. There is no need to transmit data, and data aggregation time can be shortened.

Furthermore, since commands and data in data aggregation use the transmission line for a short time, the transmission line can be used for a long time for data transmission to other areas, so the effective use efficiency of the transmission line can be improved.

Also, each buffer memory of the parent register IJBF1, BF2
, . . . BFn is used to connect the connected data Σ1 . . . through the transmission line 14-2. Σ2. ...Since the time from when Σn is taken in until the data in each buffer memory is added is relatively short, each buffer memory can be used for other purposes for a longer period of time, making effective use of the buffer memory. Efficiency can be improved.

Note that in the above embodiment, the data processed in each child register is concatenated and transmitted to the parent register all at once, but the invention is not necessarily limited to this. For example, the data processed by each child register is transmitted individually to the parent register. It is also possible to transmit data that has been subjected to arithmetic processing.

As described in detail above, according to the present invention, a plurality of totalizers for storing accumulated data to be totaled are provided, and a plurality of child cash registers are provided with a transmission control device, and a transmission control device is provided for each of the child cash registers. The data of each totalizer of each of the child cash registers is electrically connected through the transmission controller, and the data of each totalizer of each child cash register is once taken into the buffer memory, and then totaled by the internal totalizer, and the totalized data is outputted to the output device. In an online system consisting of a parent cash register that outputs data to the outside using Since the calculation is executed and then put on standby, a transmission command is output and only the data resulting from the calculation is sequentially collected from each of the child cache registers, it is possible to shorten the data collection time and also to transmit the data. It is possible to provide a data aggregation method for an online system using an electronic cash register, which can effectively use the line and parent cash register buffer memories and improve usage efficiency.

[Brief explanation of drawings]

Fig. 1 is a schematic block diagram showing a conventional example, Figs. 2 to 6 show embodiments of the present invention, Fig. 2 is a schematic block diagram, and Fig. 3 shows the circuit configuration of a child cash register. 4 is a block diagram showing the circuit configuration of the parent cache register, FIG. 5 is a diagram showing an example of the memory configuration of the RAM totalizer section in the child cache register, and FIG. 6 is a block diagram showing the circuit configuration of the parent cache register and each It is a flowchart which shows the data transmission processing process with a child cash register. 1l-LIL-2, . . . 11-n . . . Child cache register, 12 . . . Parent cache register, Ml, ~M142M21-M24. ...Mn1~
Mn4...summer, RFl, BF2 t
・-・BFn・・・・・・Buffer memory, T・・・・
...Totalizer, 13-L13-2゜...13-(n-
1), 14-1, 14-2...transmission line, 15...output device.

Claims (1)

[Claims] 1 A plurality of child cash registers each having a plurality of totalizers for storing cumulative data to be aggregated and a transmission control device, and a recorder electrically connected to each child cash register via a transmission line. The data of each totalizer of each child cash register is once taken into multiple buffer memories via the built-in transmission control device, and then totaled in the internal totalizer, and the totaled data is output to the outside by the output device. When data is totaled by an online system consisting of a parent cash register configured to perform data processing, the parent cash register first outputs a common operation instruction to the Kaneko cash register, and then outputs a common operation instruction to each of the child cash registers to calculate its own totalizer. The electronic cash register is characterized in that the electronic cash register is configured to perform the calculation and wait, then output a transmission command, and sequentially aggregate only the data of the calculation results from each of the child cash registers via the transmission line. Data aggregation method for online system.