JPS5832416A - Inspection for pattern defect - Google Patents

Inspection for pattern defect

Info

Publication number
JPS5832416A
JPS5832416A JP56111392A JP11139281A JPS5832416A JP S5832416 A JPS5832416 A JP S5832416A JP 56111392 A JP56111392 A JP 56111392A JP 11139281 A JP11139281 A JP 11139281A JP S5832416 A JPS5832416 A JP S5832416A
Authority
JP
Japan
Prior art keywords
chips
reticle
defect
foreign substances
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56111392A
Other languages
Japanese (ja)
Inventor
Tsunehiro Taguchi
田口 恒弘
Toshio Wada
和田 俊男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56111392A priority Critical patent/JPS5832416A/en
Publication of JPS5832416A publication Critical patent/JPS5832416A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)

Abstract

PURPOSE:To detect foreign substances with a high reliability, by a method wherein a plurality of chips are transferred onto a substrate, and one of them is compared with another. CONSTITUTION:Foreign substances 104, 105 and circuit patterns 106 are on a reticle 103. The probability is substantially zero that the positions of the foreign substances on the respective chips and the configurations thereof are completely the same. When transferred images are formed on a photoresist on a transparent glass, transferred images 116 of the circuit patterns appear on the whole chips, but trasferred images 114, 115 of the foreign substances appear every two chips. Objective lenses 118, 119 are disposed above chips 112, 113 respectively, and a glass plate 107 is irradiated 120. The light is photoelectrically converted 121, 122 and amplified 123, 124 and then differentially amplified 125 before being delivered 126. A holder 117 is moved in the X and Y directions to detect the existence of a defect in the whole chip aea, i.e., the existence of a foreign substance on the reticle. By this constitution, the defect due to the transfer of a foreign substance on the reticle will not be a mutual defect, and a highly reliable detection can be performed.

Description

【発明の詳細な説明】 本発明はパターン欠陥検査方法に関する。[Detailed description of the invention] The present invention relates to a pattern defect inspection method.

近年、牛導体集積回路装置の高密度化が進むにつれて、
微細パターンの形成方法が重要なものとなってきている
。この微細パターンを形成するための手段として最近開
発された縮小投影露光装置は従来の装置に比べ、解像度
、アライメント精度に優れた性能を持っている。
In recent years, as the density of conductor integrated circuit devices has increased,
The method of forming fine patterns is becoming increasingly important. A recently developed reduction projection exposure apparatus as a means for forming this fine pattern has superior performance in terms of resolution and alignment accuracy compared to conventional apparatus.

しかしながら、霧光方法が従来と異なり、1チツプごと
に繰り返し露光する断簡、ステ、プ・アンド・リピート
方式である為に、レチクル上に塵などの異物がある場合
には、すべてのチップにこの異物が転写されて共通欠陥
となり、欠陥の大きさ、チップ内の位置によってはすべ
てのウ一/Sが不良品となってしまう。
However, since the fog light method is different from the conventional method and uses a fragment, step, pull and repeat method that repeatedly exposes each chip, if there is foreign matter such as dust on the reticle, all chips will be exposed using this method. The foreign matter is transferred and becomes a common defect, and depending on the size of the defect and its position within the chip, all Uni/S become defective.

従って、このマスク上の異物を高い信頼性をもって検出
する上とが、縮小投影露光装置を使用する上では、最も
重要な問題となってくる。
Therefore, the most important issue when using a reduction projection exposure apparatus is to detect foreign substances on the mask with high reliability.

これを検出する従来の方法としては、縮小投影露光装置
にて、転写したウェハを、数百倍程度の光学顕微鏡を使
用して、肉眼で(比□較)検査する方法が用いられてき
た。
As a conventional method for detecting this, a method has been used in which a transferred wafer is inspected with the naked eye (comparison) using an optical microscope with a magnification of approximately several hundred times using a reduction projection exposure apparatus.

しかしながら、この方法は肉眼に頼る検査である几めに
、作業者の不注意等による検査ミスを避けることは困難
であり、信頼性は甚だ低い。又、検査に長時間を要し、
検査工数が多くなる欠点を持つ、II数の作業者がこの
検査を繰り返し行なうならば1信頼性を高めることは出
来るが、充分とは言えず、検査工数が膨大なものとなり
てしまう。
However, since this method relies on the naked eye for inspection, it is difficult to avoid inspection errors due to operator carelessness, and the reliability is extremely low. In addition, the inspection takes a long time,
Although it is possible to increase the reliability by repeating this inspection by a large number of workers, which has the drawback of requiring a large number of inspection man-hours, it is not sufficient and the number of inspection man-hours becomes enormous.

%に微細パターンでしかも大きなチップの場合には、低
い信頼性、膨大な検査工数という2つの欠点は更に顕著
となってくる。
%, and in the case of large chips with very fine patterns, the two drawbacks of low reliability and an enormous number of inspection steps become even more pronounced.

そこで、本発明の目的は、レチクル上の異物を信頼性よ
く検出し、工数の軽減化された検査方法を提供すること
にある。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an inspection method that can reliably detect foreign substances on a reticle and reduce the number of man-hours.

本実gi4は縮小投影露光装置において、同一の複数個
のチップ1有するレチクルを使用し、透過性を有する基
板上に形成された非透過性を有する被膜に、該複数個の
チップを繰プ返し転写する工程と、転写された該複数個
の中の第1のチップと、他の第2のチップとを比較検査
する工程とを含むことt−特徴とするものである。
In this actual GI4, a reticle having the same plurality of chips 1 is used in a reduction projection exposure apparatus, and the plurality of chips are repeatedly applied to a non-transparent film formed on a transparent substrate. The present invention is characterized in that it includes a step of transferring, and a step of comparing and inspecting the first chip among the plurality of transferred chips and another second chip.

本発明は同一の複数個のチップを有するレチクル上に塵
等の異物が複数個存在する場合、第1のチップの異物と
全く同一形状の異物が他の任意の第2のチップ内の全く
同一位置に存在する確率はゼロに等しいという原理に基
づいている。
In the present invention, when a plurality of foreign objects such as dust are present on a reticle having the same plurality of chips, the foreign object having the same shape as the foreign object on the first chip is completely identical to the foreign object in any other second chip. It is based on the principle that the probability of existing at a location is equal to zero.

本発明によれば、この原理により、異物が存在しても、
ステ、プ・アンド・リピート方式で転写されたチップに
は、異物が転写され、たために生ずる同一形状、同一位
置の欠陥が、レチクル内のチ、プ数に応じて、数チップ
ごとに規則正しく繰り返されるだけで、全チップの同一
位置に繰り返される同一形状の欠陥、所謂、共通欠陥は
生じないことになる。
According to the present invention, based on this principle, even if foreign matter is present,
When chips are transferred using the step-pull-and-repeat method, defects in the same shape and position caused by the transfer of foreign matter are regularly repeated every few chips, depending on the number of chips in the reticle. This means that defects of the same shape that are repeated at the same location on all chips, so-called common defects, will not occur.

従って、レチクル上に異物が存在しても、任意の位置に
任意の形状の欠陥がある第1のチップと、同一位置に同
一形状の欠陥がない第2のチップとに分離することが出
来、この第1及び第2のチ。
Therefore, even if there is a foreign object on the reticle, it is possible to separate the first chip, which has a defect of any shape at any position, and the second chip, which does not have a defect of the same shape at the same position. These first and second h.

プを比較検査することにより、両者の間に差異が生じて
欠陥の存在を検出することができる。
By comparatively inspecting the two samples, it is possible to detect a difference between the two and detect the presence of a defect.

更にこの発明の比較検査方法は透過性のある基板上に非
透過性の欠陥パターンを形成して、光を照射するために
、充分なコントラストが得られ、又、人為によらず、こ
の光の増減を電気信号に変換し、自動的に比較検査する
ために、高い信頼性と工数の軽減化が実現できる。
Furthermore, since the comparative inspection method of the present invention forms a non-transparent defect pattern on a transparent substrate and irradiates it with light, sufficient contrast can be obtained, and this light cannot be irradiated without human intervention. Since the increase/decrease is converted into an electrical signal and automatically compared and inspected, high reliability and reduced man-hours can be achieved.

次に本発明の特徴をより良く理解するために、この発明
の実施例について図WJを用いて説明する。
Next, in order to better understand the characteristics of the present invention, an embodiment of the present invention will be described using FIG. WJ.

第1図ないし第6図はこの発明の一実施例における主要
工程図である。
1 to 6 are main process diagrams in one embodiment of the present invention.

初めに、第1図に示すように、同一の複数チップの例と
して2つのチップ101.102を有するレチクル10
3を用意する。このレチクル103上には異物104,
105及び回路パターン106があるものとする。この
異物104,105のそれぞれのチップ101,102
に対する位置及び形状は、同時に全く同一となる解重は
ゼロに等しいことは明らかである0次に第2図の断面図
に示すように透過性のあるガラス板107を用意し、上
面に非透過性の被[1108t−形成する。ガラス板1
07としては、光に対する透過性を示すもので、例えば
サファイヤ、ソーダ・ライム、石英ガラスがある。非透
過性の被膜108は、後述するように転写されたパター
ンのコントラストラ大キくするためのもので、例えばア
ルミニウム等の金属を用い、膜厚は約1μm程度にする
。さらに、非透過性の被膜108の上面に約1μm程度
のフォトレジスト109を塗布する。このフォトレジス
ト109は、市販のいずれのものでも良いが、ピンホー
ルが少なく、解像力に優れているものが望ましい。次に
第1図のレチクル103を縮小投影露光装置の所定の場
所にセットし、第2図のガラス板107上のフォトレジ
スト109に、ステ、プ・アンド・リピート方式で露光
後、現儂すると、レチクル103上の異物104,10
5及び回路パターン106が転写されて、フォトレジス
ト像110が形成される(第3図)。このフォトレジス
ト1lllOtエツチングのマスクとして非透過性の被
膜108をエツチング除去後、上面のフォトレジスト@
110を除去すると、非透過性の被膜倫111が第4図
のように形成される。
First, as shown in FIG. 1, a reticle 10 having two chips 101 and 102 as an example of multiple identical chips is shown.
Prepare 3. On this reticle 103 there is a foreign object 104,
105 and a circuit pattern 106. Chips 101 and 102 of these foreign substances 104 and 105, respectively.
It is clear that the deweighting is equal to zero when the position and shape are exactly the same at the same time. [1108t- to form] glass plate 1
07 indicates transparency to light, such as sapphire, soda lime, and quartz glass. The non-transparent film 108 is used to increase the contrast of the transferred pattern as will be described later, and is made of metal such as aluminum, and has a thickness of approximately 1 μm. Further, a photoresist 109 having a thickness of about 1 μm is applied to the upper surface of the non-transparent film 108. This photoresist 109 may be any commercially available photoresist, but it is desirable that it has few pinholes and has excellent resolution. Next, the reticle 103 shown in FIG. 1 is set at a predetermined location in the reduction projection exposure apparatus, and after exposing the photoresist 109 on the glass plate 107 shown in FIG. , foreign matter 104, 10 on the reticle 103
5 and circuit pattern 106 are transferred to form a photoresist image 110 (FIG. 3). After removing the non-transparent film 108 as a mask for etching the photoresist, the upper photoresist@
When 110 is removed, an impermeable capsular layer 111 is formed as shown in FIG.

第5図は、非透過性の被膜@111の平面図の一部であ
る。112,113はそれぞれチップl0L102の%
 114,115,116はそれぞれ異物104,10
5及び回路パターン106の転写像であるが、上述の方
法で転写*1−形成すると、回路パターンの転写111
16Fi全チツプに現われるが、異物の転写像114,
115はそれぞれ2チツプごとにしか現われないことに
なる0次に第4図のガラス板104を第6図のようにホ
ルダー111にセ、トシて、チップ112の上部に対物
レンズ118’t、チップ113の上部に対智レンズ1
19を配置する。
FIG. 5 is a partial plan view of the non-permeable coating @111. 112 and 113 are respectively % of chip l0L102
114, 115, 116 are foreign substances 104, 10, respectively
5 and the transfer image of the circuit pattern 106, when the transfer *1- is formed by the method described above, the transfer image of the circuit pattern 111
Although it appears on all 16Fi chips, foreign matter transfer image 114,
The glass plate 104 shown in FIG. 4, which will appear only every two chips, is placed on the holder 111 as shown in FIG. Anti-chip lens 1 on the top of 113
Place 19.

その後、対物レンズ118,119t″通して光120
をガラス板107に照射して、転写像114゜115.
116(第5図)以外の領域を通過してくる光を7オト
マル121,122で受信すること(よって、2つの電
気信号に変換する。ここで透過性のあるガラス板107
に比して転写像114゜115.116は非透過性であ
るために、電気信号には充分なコントラストが得られる
。この2つの信号は増幅器123,124をそれぞれ経
由して差動増幅器125にはいり、信号の比較が行なわ
れて出力126に至る。
After that, the light 120 through the objective lenses 118, 119t''
is irradiated onto the glass plate 107 to form transferred images 114°, 115.
The light passing through the area other than 116 (FIG. 5) is received by the 7-meters 121 and 122 (thus, converted into two electrical signals. Here, the transparent glass plate 107
In contrast, the transferred images 114°, 115, and 116 are non-transparent, so that sufficient contrast can be obtained for electrical signals. These two signals enter a differential amplifier 125 via amplifiers 123 and 124, respectively, where the signals are compared and delivered to an output 126.

出力126にはチップ112とチップ113との間にパ
ターンの差異がない場合、即ち欠陥が存在しない場合に
は、差動増幅器125から信号は発生しないが、差異が
ある場合、即ち欠陥が存在する場合に:は、2つの信号
間に差異が生じ、これが差動増幅器125にて比較され
た後、信号が発生して欠陥の存在を検出することができ
る。
If there is no pattern difference between the chips 112 and 113, that is, there is no defect, no signal is generated from the differential amplifier 125 at the output 126, but if there is a difference, that is, there is a defect. In the case: a difference occurs between the two signals, and after this is compared in the differential amplifier 125, a signal can be generated to detect the presence of a defect.

次にこの比較検査を、ホルダー1171−紙面内の横方
向及び紙面に対して垂直方向に動かしながら行なうこと
によりチップ内全械の欠陥の存在、即ち、レチクル上の
異物の存在を検知することができる。
Next, by performing this comparative inspection while moving the holder 1171 in the lateral direction within the plane of the paper and in the direction perpendicular to the plane of the paper, it is possible to detect the presence of defects in the entire structure within the chip, that is, the presence of foreign objects on the reticle. can.

上述したように、この発明によれば、縮小投影露光装置
においてまず同一の複数個のチップを有するレチクルを
用いることにより、レチクル上の異物が転写され次ため
に生ずる欠陥は共通欠陥とならず、比較検査が可能とな
る。
As described above, according to the present invention, by first using a reticle having a plurality of identical chips in a reduction projection exposure apparatus, defects that occur as a result of foreign matter on the reticle being transferred do not become common defects; Comparative inspection becomes possible.

次にこのレチクルを透過性を有する基板上の非透過性を
有する被膜に転写して、光を照射するために充分なコン
トラストが得られ、この光の増減を電気信号に一変換し
て比較検査する九めに、従来の内眼による検査にしばし
ば見られる検査ミスが防止され、信頼性の高い検出を行
なうことができる。更に検査工程の自動化により工数の
軽減化を実現できる。
Next, this reticle is transferred to a non-transparent coating on a transparent substrate to obtain sufficient contrast for irradiation with light, and the increase and decrease of this light is converted into electrical signals for comparative inspection. Ninth, test errors often seen in conventional intraocular tests can be prevented and highly reliable detection can be performed. Furthermore, by automating the inspection process, it is possible to reduce the number of man-hours.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第6図は本発明の一実施例における主要工
程図である。 尚、図において、 101・・・・・・チップ、102・・・・・・チップ
、103・・・・・・レチクル、104・・・・・・レ
チクル上の異物、105・・・・・・レチクル上の異物
、106・・・・・・レチクル上の回路パターン、10
7・・・・・・透過性を有するガラス板、108・・・
・・・非透過性の被膜、109・・・・・・フォトレジ
スト、110・・・・・・フォトレジスト像、111・
・・・・・非透過性の被膜偉、112・・・・・・チッ
プ101の転写像、113・・・・・・チップ102の
転写像、114・・・・・・レチクル上の異物1040
転写像、115・・・・・・レチクル上の異物1050
転写像、116・・・・・・レチクル上の回路パターン
の転写像、117・・・・・−ホルダー、118・・・
・・・対物レンズ、119・・・・・・対物レンズ、1
20・・印・光、121・・・・・・フォトマル、i2
2・・・・・・フォトマル%123・・・・・・増幅器
、124・・・・・・増幅器、125・・・・・・差動
増幅器、126・・・・・・出力、である。 107 悴す区 手続補正書(自発) 57,9.2B 昭和  年  月  日 r′、。 特許庁長官 殿 1、事件の表示   昭和56年特 許 願第1113
92号2、発明の名称   パターン欠陥検査方法3、
補正をする者 事件との関係       出 願 人東京都港区芝五
丁目33番1号 (423)   日本電気株式会社 代表者 関本忠弘 4、代理人 6、補正の内容(特願昭56−111392)(1)明
細書の特許請求の範囲の記載を別紙のとおりに訂正いた
します。 7 添付書類 別  紙     1通 訂正後の特許請求の範囲 「縮小投影無光装置において、同一の複数個のチップを
有するレチクルを使用し、該複数個のチッる工程とを含
むことを特徴とするパターン欠陥検査方法。」
1 to 6 are main process diagrams in one embodiment of the present invention. In the figure, 101... Chip, 102... Chip, 103... Reticle, 104... Foreign matter on reticle, 105... - Foreign matter on reticle, 106...Circuit pattern on reticle, 10
7...Transparent glass plate, 108...
... Non-transparent film, 109 ... Photoresist, 110 ... Photoresist image, 111.
. . . Non-transparent coating, 112 . . . Transfer image of chip 101, 113 . . . Transfer image of chip 102, 114 . . . Foreign matter on reticle 1040
Transferred image, 115... Foreign matter on reticle 1050
Transfer image, 116...Transfer image of circuit pattern on reticle, 117...-Holder, 118...
...Objective lens, 119...Objective lens, 1
20...mark/light, 121...photomaru, i2
2... Photomal% 123... Amplifier, 124... Amplifier, 125... Differential amplifier, 126... Output. . 107 Written amendment to Kazusu Ward procedure (voluntary) 57, 9.2B Showa year, month, day, r'. Commissioner of the Japan Patent Office 1, Indication of the case 1981 Patent Application No. 1113
No. 92 No. 2, Title of invention: Pattern defect inspection method 3,
Person making the amendment Relationship to the case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent 6 Contents of amendment (Patent application 111392-1982) (1) The scope of claims in the specification will be corrected as shown in the attached sheet. 7 Attachment: Attachment: 1 copy of the amended claims: “A reduction projection achromatic device characterized by using a reticle having a plurality of identical chips and including a step of ticking the plurality of chips.” Pattern defect inspection method.”

Claims (1)

【特許請求の範囲】[Claims] 縮小投影露光装置において、同一の複数個のチップを有
するレチクルを使用し、透過性を有する基板上に形成さ
れた非透過性を有する被膜に、該複数個のチップを繰夛
返し転写する工程と、転写された該複数個の中の第1の
チップと、他の第2のチップとを比較検査する工程とt
含むことを特徴とするパターン欠陥検査方法。
A step of repeatedly transferring the plurality of chips onto a non-transparent coating formed on a transparent substrate using a reticle having the same plurality of chips in a reduction projection exposure apparatus; , a step of comparing and inspecting the first chip among the plurality of transferred chips and another second chip;
A pattern defect inspection method characterized by comprising:
JP56111392A 1981-07-16 1981-07-16 Inspection for pattern defect Pending JPS5832416A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56111392A JPS5832416A (en) 1981-07-16 1981-07-16 Inspection for pattern defect

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56111392A JPS5832416A (en) 1981-07-16 1981-07-16 Inspection for pattern defect

Publications (1)

Publication Number Publication Date
JPS5832416A true JPS5832416A (en) 1983-02-25

Family

ID=14559994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56111392A Pending JPS5832416A (en) 1981-07-16 1981-07-16 Inspection for pattern defect

Country Status (1)

Country Link
JP (1) JPS5832416A (en)

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