JPS5831678B2 - Read-only memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read-only memory circuit, and more particularly to a read-only memory circuit in an integrated circuit device (hereinafter referred to as MO8IC) configured with an insulated gate field effect transistor.

In MO8ICs, generally, aluminum or silicon is used as the material for the gate electrode, and an enhancement mode load MO8 is used as the load for the enhancement mode drive MO8FET in the impark stage that constitutes one circuit of the IC. (hereinafter E
(hereinafter referred to as an E/D type IC) and one using a depletion mode load MO8 (hereinafter referred to as an E/D type IC) are known.

Of these, silicon gate MO8ICs using depletion loads have recently been widely adopted as devices with higher performance and higher integration density for various uses than aluminum gate MO8ICs.

According to the inventor's experiments, self-alignment (self-alignment)
The area occupied by a Si-gate MOS transistor having a gate structure is reduced by about 20 to 30% compared to an AA age-MOS transistor.

However, as a result of investigating MO8ICs from various manufacturers on the market, we found that for read-only memory (hereinafter referred to as ROM), which occupies a considerable portion of MO8IC chips, the size of a single bit of ROM is shown in Table 1 below. As shown, it was found that the normal Si gate ROM structure is not necessarily significantly smaller than the Al gate one.
Therefore, one object of the present invention is to provide a new ROM that can occupy a significantly smaller area than conventional Al gate or Si gate ROMs.

Another object of the present invention is to provide a ROM that operates well.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The ROM (MOS matrix) according to the present invention will be described in detail below with reference to the drawings, while comparing it with a conventional Si gate ROM.

FIG. 1 shows a basic circuit used in a conventional Si gate ROM, FIG. 2a is an enlarged plan view of a part of the conventional Si gate ROM, and FIG. 2b is a plan view showing a part of the conventional Si gate ROM. FIG. 2 is a partially enlarged cross-sectional view of a conventional Si Age-MO8ROM taken along the line xx' of FIG.

As shown in FIG. 1, a conventional Si gate MO8ROM consists of MOSFETs arranged in parallel, and the state of each memory cell is identified by the thickness of the gate oxide film.

The operation of the illustrated ROM is as follows.

That is, a low level signal close to the power supply voltage is applied to the selected address line.

On the other hand, a high level signal close to 0 volts is applied to unselected address lines.

Accordingly, the level of the output OUT is determined by the MOSFET coupled to the selected address line.

For example, if we consider the case where ■N2 line is selected,
Since the MOSFET lying below this line has a thick gate oxide film, it is normally turned off.

Therefore, the output level becomes a low level.

Such a conventional ROM, as shown in FIGS. 2a and b,
It is composed of ten diffusion layers 2, 3, 4; polysilicon layers 7, 8; silicon dioxide films 5, 6; phosphorus silicate glass 9; through holes 11; and aluminum layer 10.

The poly-Si layer is used for address input lines, and the A1 layer is used for output lines.

A through hole between the A1 layer and the P1 diffusion layer is necessary to commonly connect the drain electrodes of the MOSFETs arranged in each row.

As is clear from these figures, the state of each memory cell at the intersection of each input line and each output line is determined by the thickness of the gate oxide film.

That is, if a MOSFET that operates 0N-OFF depending on the signal voltage applied to the input line at a certain intersection is required, the gate oxide film under the poly-Si layer at that point is thinned, and the above operation is applied there. M to do
If an OSFET is not required, use a polyS at that location.
A ROM having a predetermined bit pattern is constructed by increasing the thickness of the oxide film under the i-layer.

The minimum size per unit bit of a Si gate ROM having such a configuration is approximately 410 .mu.-, which is approximately the same as that of a ROM.

This ROM is characterized by the following configuration.

(1) The state of each memory cell is identified by the thickness of the gate oxide film.

(2) Since it uses a self-line gate structure,
The poly-Si layer cannot cross over the P+ diffusion layer.

Accordingly, an Al wiring layer is required, a P diffusion layer and an A
A through hole is required between the first layer and the first layer.

Therefore, the area occupied per bit of the conventional Si gate ROM cannot be reduced despite the self-line structure.

Next, according to FIGS. 3, 4a, b, c and 5,
The Si Age-MO8ROM according to the present invention will be explained.

FIG. 3 shows the basic circuit used in the ROM.

This basic port 1 bath has multiple enhancement modes and depletion modes connected in series as driving elements.
It consists of a mode MOSFET.

The depletion mode MO8FE'l also works as a resistance element.

This depletion mode MOSFET also substantially constitutes a cross-wire.

Reading one piece of data is stably performed by applying a high level signal close to O volts to the address line to be selected.

At this time, a low level signal is applied to the unselected address line so as to turn on the enhancement mode MOSFET depletion MO8FET whose gate is coupled to the unselected address line.

For example, if the illustrated address line N2 is selected, an MO whose gate is coupled to this address line N2
The SFET remains on because it is in depletion mode.

At this time, among the unselected address lines, address lines IN, , IN3 . MOS with gate coupled to IN
The FETs are in enhancement mode but are turned on by applying a low level signal to their respective gates.

Since the MOSFET whose gate is coupled to an unselected address line, for example (1)Nn-1, is in depletion mode, it remains on regardless of its gate potential.

Therefore. In this case, all drive elements are substantially turned on, so
A high level output signal close to O volts is obtained at the output terminal.

On the other hand, if the address line N3 is selected, the MOS FET whose gate is coupled to this line
Since it is in the enhancement mode, it becomes non-conductive (off) due to the high level input signal applied to this line N3.

Therefore, a low level output signal is applied to the output terminal OUT.

Thus, in the ROM shown in FIG. 3, the precharged output data line either remains at a low level or goes to a high level, depending on whether the enhancement or depletion mode MO8FET is selected. It will be shifted.

FIG. 5 is a circuit diagram of a ROM circuit according to an embodiment of the present invention.

The ROM circuit in the figure is composed of a first address decoder MOS matrix 23 and a second MOS matrix 24 whose output is input.

Matrices 23 and 24 are constructed from the basic circuit shown in FIG.

The output of each stage of a cascade-connected plurality of stages (72 stages, for example) of flip-flop circuits 21 is input directly or via an inverter circuit 22 to a first MOS matrix 23, and the output is fed to a second MOS matrix 23. The signal is input to the IJ box 24, and outputs 0UTI to 0UTn are obtained from the second MOS matrix.

In the figure, the matrices 23 and 24 have one MOSFET that operates in depletion or enhancement mode at the intersection of the input line and the output line, and these FETs are connected to the power supply VDD and the reference potential source (earth) for each row. are connected in series between.

Also connected to each matrix are enhancement mode MO8FETs 27 and 28, to whose gates a clock signal is applied, as loads for the drive MO8FETs.

In addition, as shown by 25 in the figure, the drive MO3FET marked with a circle is a MOS that operates in depletion mode.
This indicates that the drive MO8FET is a FET, and that the other drive MO8FETs operate in enhancement mode.

The plurality of inverters 22 in the figure each consist of a drive MO8FET operating in an enhancement mode and a load MO8FET connected in series thereto and operating in a depletion mode, although their specific circuits are not shown.

The MOSFETs in the figure, regardless of whether they are in depletion mode or enhancement mode, all have gate insulating films (for example, SiO2 films) with substantially the same thickness (approximately 500 to 1500 angstroms).

The depletion MO8FET in the MOS matrix and the depletion MO8FET in the inverter 22 are simultaneously formed by the same process.

The input lines in each of the first and second matrices 23 and 24 are formed of wiring layers made of poly-Si.
The output line of the matrix 23 and the input line of the second matrix 24 are connected via aluminum wiring that connects the P+ diffusion layer and the P'JSi layer.

Next, the device structure constituting the MO8ROM will be explained using FIGS. 4a, 4b, and 4c.

Figure 4a is an enlarged plan view of a part of the MO8ROM, and Figures 4b and C are x-x' and Y-Y of Figure 4a, respectively.
'Shows a cross section.

In the figure, 31 is an N-type single crystal Si substrate; 32 to 34 and 47
49 are P+ type diffusion layers formed by self-alignment with Si gate electrodes; 35, 36 and 43 are gate insulating films made of silicon dioxide having substantially the same thickness (approximately 1,000 layers); 37 and 38 are polygonal insulating layers; Input line made of Si; 39 is an insulating film made of phosphor silicate glass; 41 and 42 are depletion MO8FETs
A P-type channel layer is formed by selectively implanting P-type impurity ions into the substrate surface to form a P-type channel layer; 44 to 46 indicate field insulating films made of relatively thick (approximately 1 to 2 μm) silicon dioxide; There is.

As is clear from the figure, one memory cell is always formed at the intersection of the poly-Si wiring layers 37, 38 as address input lines and the P+ diffusion layer as self-connected data output lines.

Each memory cell all has a thin gate oxide to operate as an enhancement or depletion MO8FET.

The state of each memory cell is determined by whether there is a P-type channel formed by ion implantation.

Figures 6 to 6E show operational waveform diagrams of the ROM circuit of Figure 5.

Load M in the first and second matrices 23 and 24 of FIG.
Clock pulses ψ1 and ψ2 having mutually different phases as shown in FIGS. 6B and 6C are applied to the gate of O8FET 27>28, respectively.

At time 10, the clock pulse ψ1 is changed from a high level, such as VO volts, to a low level, and the load MO8FET 27 in the first matrix 23 is turned on in response.

As a result, each output line A to Am of the first matrix 23 is connected to the
It is precharged to a value close to the power supply voltage VDD in volts, that is, to a low level.

When the clock pulse ψ1 is set to high level again at time t1, each M in the first matrix 23 responds to this.
O8FET 27 is turned off.

The levels of the address signals output from the plurality of flip-flop circuits 21 are updated in synchronization with the clock pulse ψ1.

Accordingly, the first matrix 230) input, e.g.
1 is changed as shown in FIG.

For example, when the combination of address signals output from the plurality of flip-flop circuits 21 indicates a state in which the output line A1 should be selected, the output line A1 is connected in series between the output line A1 and the ground point of the circuit. A plurality of MOS FETs in the 171st IJ box 23 are simultaneously turned on.

As a result, the output line A1 is brought to a high level of 0 volts as shown in the sixth diagram.

In other words, the output line A1 is set to the selection level.

The remaining unselected output lines A2 through Am have at least one enhancement mode MO8FET connected in series between each of them and the circuit ground point.

Since it is turned off by either of the following, it is maintained at a low level, that is, a non-selection level.

When the clock pulse ψ2 is set to a low level at time t2 as shown in FIG.

is precharged to the main power supply voltage level (low level).

In addition, in FIG. 5, the 271-IJ box is connected to the pit line B1. B2 and output line OUT.

depletion mode MO8FET and enhancement mode MO8FET connected in series between
Contains.

The gates of these MOSFETs are supplied with signals CI and C2, which can essentially be regarded as address signals.

Correspondingly, for example, if signal C1 is high and signal C2 is low, only B1 of pit lines B1 and B2 will be coupled to output line 0UT1 via MO8FETs 30 and 31. .

In other words, pit line B is selected by signals C1 and C2.

Therefore, in precharging the output lines 0UT1 to OUTn, bit compensation is performed.

The bit line selected by the signals C1 and C2 among the bit lines B1 to B1 is also precharged.

When the clock pulse ψ2 is returned to a high level at time t3, each load MO8FET 28 is turned off, and the precharge operation is completed.

The level of each output line OUT to 0UTn in the second matrix 24 is determined by the on/off state of the MOSFET connected in series between each output line and the ground point of the circuit.

For example, as described above, the output line A of the first matrix 23
1 is selected, the MOSFET 29 belonging to the bit line B1 and to which the signal of the output line A1 is supplied is in depletion mode as shown, so that the MOSFET 29 is connected between the bit line B1 and the ground point of the circuit. A current path is formed.

At this time, if the signals C1 and C2 are at high level and low level, respectively, as described above, the output line 0UT
1 is connected to bit line B via MOSFETs 30 and 31.
1 will be combined.

As a result, the output line OUT is brought to a high level as shown in FIG. 6E.

At time t4, the clock pulse ψ1 is set to a low level again, and in response, each output line A1 to Am of the first matrix 23 is precharged again.

When the clock pulse ψ2 is brought to a low level at time t5, each output line 0UT1 to 0UTn of the second matrix 24 is precharged again.

Since the MOS matrix according to the present invention has a self-aligned gate structure and does not require a through hole, it is understood that the area occupied per single bit is significantly smaller than that of the conventional one.

Figures 7a and 7b are MO8s that are distantly related to the same circuit function.
The semiconductor chip size and the area occupied by each circuit block are shown in comparison when an IC is formed using the technology of the present invention and when an IC is formed using the conventional 81 gate MO8 manufacturing technology.

That is, by adopting the MOS matrix according to the present invention, a simple self-line type 81 gate MO8R
Compared to the case where OM is adopted, the ROM portion, which occupies a relatively large area in the LSi, is reduced by about 50%, and as a result, the total chip size can be reduced by about 20%.

Next, the operating speed of the ROM according to the present invention will be explained with reference to FIGS. 8a and 8b.

Since a ratioless circuit as shown in FIG. 8b is used, the RO
The output level of M has two states, and as described above, the precharge data line either remains low or shifts to high.

In this case, the operating speed of the ROM mainly depends on the discharge time td during which the precharged data line transitions to a high level.

FIG. 8a has 48 address lines shown in FIG. 8b, and 48 enhancement or deregion MO8s.
The FETs are connected in series f, and the discharge time (lltd) of the knee MO8ROM and the amplitude of the clock pulse supplied to the gate of the enhancement mode load MO8 (horizontal axis ■).

p).

However, the output capacitance of the ROM is approximately 1.5 pF.

This figure shows that the discharge time is less than 1.5 μs, and since it is possible to operate on the order of 100 KHz especially as a calculator IC, there is no problem in practical use.

In summary, the ROM according to the present invention has the following features.

(1) The ROM of the present invention is composed of enhancement type and depletion type MO8FETs as driving elements.

(2) The ROM of the present invention is extremely small in size, about 50 times smaller than that of a conventional Si gate structure.

(3) The ROM of the present invention can be manufactured using a process compatible with the Si age MO8LSI using a depletion load, which is currently being widely used.

(4) A cascade ratioless circuit can be applied to the ROM of the present invention, and by paying sufficient attention to estimating the operating speed, an LSI with extremely excellent characteristics can be realized.

The circuit of the embodiment shown in FIG. 5 can be constructed with fewer circuit elements and performs reliable circuit operation.

This will be better understood from the following explanation.

For example, the address decoder can be configured using a plurality of unit circuits as shown in FIG. 1 instead of the configuration shown in FIG. The output selection level is the low level of the power supply voltage.
Also, the non-selection level is a high level of 0 volts, whereas the selection level of the input of the second matrix 24 is, as is clear from the above, a high level of 0 volts, and the non-selection level is a high level of 0 volts. Since the power supply voltage is required to be at a low level such as the main power supply voltage, signal inversion by an inverter circuit is required.

Therefore, it becomes necessary to provide inverter circuits corresponding to the number of inputs of the second matrix 24.

In the case of the configuration shown in FIG. 5, the selection level of the address decoder 23 is the high level of VQ volts, and the non-selection level is the low level of the power supply voltage, so there is no need to provide an inverter circuit as described above. .

As a result, the circuit of FIG. 5 can be constructed with a small number of circuit elements.

Address decoder 23 in FIG. 5 supplies a signal at an appropriate level to second matrix 24 as a ROM matrix.

Instead of the configuration shown in FIG. 5, for example, if a constant voltage such as the power supply voltage is applied to the gate of the load MO3FET 27 of the address decoder 23 shown in the same figure, instead of one pulse ψ1, the high level of the output line will be , load MO8F
It is determined by the ratio between the conductance of the ET and the overall conductance of the MOSFETs connected in series between its output line and the ground point of the circuit.

In this case, it is difficult to sufficiently increase the conductance of each of the plurality of MOSFETs connected in series between the output line and the ground point of the circuit due to restrictions such as the dimensions of the MOSFETs, so the high level of the output line It becomes difficult to change the value to a sufficient value.

As a result, it becomes impossible to drive the second matrix 24 well.

The address decoder having the configuration shown in FIG. 5 outputs a good level high level signal because it substantially constitutes a so-called ratioless circuit.

Therefore, the circuit of FIG. 5 operates reliably.

Note that the idea of the present invention described above can also be applied to other complex logic circuits such as a programmable logic array and a four-phase phaseless dynamic circuit.

Therefore, it is clear that the scope of rights in this application is not limited to the specific embodiments described above.

[Brief explanation of drawings]

Figure 1 is a basic circuit diagram of a conventional MO8ROM, Figures 2a and 2b are a partially enlarged plan view and cross-sectional view of a conventional MO8ROM, respectively, and Figure 3 is a basic circuit diagram of a MO8ROM configured by MOSFETs connected in series. , FIGS. 4a to 4C are partially enlarged plan and cross-sectional views of the integrated circuit constituting the MOS ROM of FIG. 3, and FIG. 5 is a MOS ROM according to the present invention.
The circuit diagram of FIG. 6 is the operating waveform diagram of the circuit of FIG. 5, and the circuit diagram of FIG.
a and b are LSIs for comparing MO8LSI adopting the present invention and MOSLSI according to the prior art, respectively.
The chip top pattern diagram, Figure 8b, is actually the MO of the present invention.
FIG. 8a is a diagram showing an example of a circuit when using an 8ROM, and FIG. 8a is a diagram showing the results of measuring the operating speed of the circuit No. 8b.

Claims (1)

[Scope of Claims] 1. A first insulated gate field effect transistor group arranged in a matrix, selected ones of which are defined as depletion type and the remaining transistors defined as enhancement type. , in each row, the insulated gate field effect transistors are connected in series and connected to a power supply via a precharging insulated gate field effect transistor, and in each column, the gate electrode of the insulated gate field effect transistor located therein is an address decoder circuit unit commonly connected by an input signal line, and a second group of insulated gate field effect transistors arranged in a matrix, a selected one of the transistors being a depletion type; The remaining ones are defined as enhancement type, and in each column, the second group of insulated gate field effect transistors are connected in series and connected to the power supply via a precharging insulated gate field effect transistor, and in each row, there is The gate electrodes of the second insulated gate field effect transistor group located therein are provided with a read-only memory circuit section commonly connected by an input signal line, and the outputs of each row of the address decoder circuit section are connected in common by an input signal line. A signal is input to each of the input signal lines of the read-only memory circuit section, and output signals of the series-connected circuits of each column of the read-only memory circuit section are taken out. Read-only memory circuit. 2. The read-only memory circuit according to claim 1, wherein the insulated gate field effect transistor for precharging of the read-only memory circuit section is commonly connected to a plurality of columns. . 3. The read-only memory circuit according to claim 2, further comprising a selection circuit for selectively extracting the output signals of the series-connected circuits in each column of the read-only memory circuit section.