JPS5831575A - Polycrystalline thin film transistor - Google Patents

Abstract

PURPOSE:To enable large area and long length of a thin film transistor and to obtain a semiconductor material having 1cm<2>/V.sec of mobility of carrier by forming the length of the region in which at least the carrier moves longer than ten times of the diameter of crysralline grain when forming a semiconductor device using a polycrystalline semiconductor film. CONSTITUTION:A silicon film 2 having approx. 2,000Angstrom of the diameter of crystalline grain and approx. 2cm<2>/V.sec of mobility of carrier is formed on a sbustrate 1. Then, an SiO2 film 3 is coated by a vapor growing method in a thickness of 5,000Angstrom . Subsequently, windows for the source and drain regions are formed in the film 3. The interval between the source region and the drain region is 20mum. Accordingly, the channel length becomes 20mum. Then, an n<+> type layer 4, a field oxidized film 5, an SiO2 film 6, a source electrode 7, a drain electrode 8 and a gate electrode 9 are sequentially formed. Thereafter, a heat treatment is performed in H2 atmosphere, thereby manufacturing a thin film MOS field effect transistor of the structure provided with the channel of 20mum long.

Description

DETAILED DESCRIPTION OF THE INVENTION The invention relates to a transistor consisting of a polycrystalline semiconductor thin film t-material formed on an insulating substrate.

The transistor of the present invention is useful, for example, when it is integrated into a display substrate of a flat display device using liquid crystal, ectoluminescence, etc., and utilized as a semiconductor device used for driving.

Conventionally, as a liquid crystal display device, for example, single crystal 81
A two-dimensional switching matrix of M08 transistors and a peripheral scanning circuit are integrated on the substrate to form a companion integrated circuit, and a liquid crystal is sealed between this single-crystal Bt integrated circuit element and a counter electrode.

A driving method using the single crystal 81 integrated circuit element is adopted. In this case, since the substrate is a single crystal,
Since there is a limit to the size of the substrate that can be manufactured, there is a limit to the screen size of the liquid crystal display device that can be manufactured. For example, since the maximum diameter of SI wafers currently manufactured is 5 inches, it is not possible to manufacture a screen with a size equivalent to a 5-inch or larger Blauwan tube. The inability to increase the area is a major drawback as an 11iI imaging device.

In order to eliminate this drawback, an amorphous semiconductor film or a polycrystalline semiconductor film is formed on an amorphous substrate, and the entire 16 element as described above is manufactured using the amorphous semiconductor or polycrystalline semiconductor as a material. Methods for forming and driving flat display devices have also been proposed.

In this case, since the YTFC conductor thin film is formed on the amorphous substrate using a method such as vacuum evaporation, it is possible to create a large area with a diameter of more than 5 inches. It becomes possible to enlarge the area.

However, when an amorphous semiconductor film is used, there is a drawback that the carrier mobility of the amorphous semiconductor thin film is extremely low, so that the characteristics of a transistor formed from the amorphous semiconductor thin film are poor. - When a polycrystalline semiconductor thin film is used, the carrier mobility is sufficiently high to be used as a display element. In some cases, the presence of grain boundaries causes variations in the characteristics of each fabricated device, which is a drawback. In other words, a current path in one element crosses a grain boundary, but a current path in another element does not cross a grain boundary, and carrier conduction depends on each element depending on the effect of grain boundaries. , there may be no receptivity. Therefore, depending on each element, the transistor characteristics 18, for example, the transfer conductance! The result is 4.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a thin film transistor with excellent transistor characteristics and uniform characteristics.

In the present invention, when a polycrystalline semiconductor film is formed on a predetermined substrate and a semiconductor device is formed using this polycrystalline semiconductor film,
At least the length of the area where carriers travel is the crystal grain size (
If the crystal grains are flat, the length should be at least 10 times the major axis. Note that in this specification, the crystal grain size refers to the average crystal grain size. In other words, the device characteristics depend on the number of grain boundaries encountered during carrier travel. Since there are a sufficiently large number of crystal grains in the area where the semiconductor device is formed, the carriers are affected by the large number of crystal grain boundaries, so when a large number of semiconductor devices are manufactured, the uniformity of their characteristics is good. From the viewpoint of characteristic variations, it is best if the length of the region in which the carriers travel is 50 times or more the length of the crystal grain, and the characteristic variations (tlt) can be well suppressed.

However, if the crystal grain size is too small, the properties of the conductor material (eg, carrier mobility) will deteriorate, so it is more preferable that the crystal grain size be at least 150 nm or more.

Of course, even if the crystal grain size is less than % grain size, there will be variations in device characteristics! Needless to say, the relationship between the length of the carrier traveling distribution area and the crystal grain size is useful in terms of reducing the carrier distribution area and making the device uniform.

In the circuit design of a semiconductor device, when the length of the carrier travel region □ (for example, in the case of a field effect transistor, this corresponds to the channel length) is constant, the polycrystalline grain size is adjusted. - If the size of crystal grains is restricted due to constraints on the conditions for forming polycrystalline thin films, it will be necessary to design elements and circuits accordingly.

Although there is no upper limit to the length of the carrier travel region in terms of design, it is probably 100 μm or less in practice. In addition, the lower limit of the particle size is particularly set at t, 11, but in practice, carrier mobility can be ensured at 100λ or more. Therefore, the practical upper limit of the ratio between the length of the carrier traveling area and the particle size will be 10,000 times s&.

As long as a channel is formed, the thickness of the semiconductor layer may be at least the minimum IQQ nm.

Furthermore, it is more preferable that it be soon m or more.

As the substrate, an amorphous or polycrystalline substrate such as a glass substrate or a ceramic substrate such as A401 is useful.

One reason is the cost, and glass substrates are especially inexpensive. Furthermore, a translucent substrate can be used as the substrate.

Note that a preferred method for depositing a polycrystalline semiconductor film is as follows.

The vacuum evaporation apparatus capable of achieving an ultra-high vacuum may be a evaporation apparatus having a normal ultra-high vacuum apparatus.

The degree of vacuum during vapor deposition is set to a high vacuum of less than lXl0-a Torr. Furthermore, since 01 in the residual gas during vapor deposition has an adverse effect on the characteristics, the oxygen partial pressure is set to lXl0-@'I'o.
less than rr.

The deposition rate is 1.00 OA/hour
Using 0,000 people zhour.

The particle size can be controlled to some extent by controlling the thickness of the deposited film, the substrate temperature, the deposition rate, and the vacuum ft. In Figure 1, the substrate temperature is 600C and the deposition rate is 5000 people/h.
FIG. 4 is a diagram showing the relationship between the thickness of a deposited film and the average crystal grain size under the condition of a vacuum degree of 8×10°@Torr during deposition. Film thickness can be measured using a crystal oscillator.

Further, depending on the case, the particle size may be controlled by means such as laser annealing.

To fabricate a semiconductor device using polycrystalline silicon/film T7F11, several steps must be taken.
The advantages of the present invention can be fully utilized by suppressing the heat treatment in these steps to a temperature lower than 820C, which is the softening point of ultra-hard glass. When using a glass substrate with a low softening point, the softening point is even lower, for example 5.
It is also possible to keep the temperature below 50C. In the following, an MO8 field effect transistor 11rIP11 will be explained as an example of a transistor.

Generally, a gate oxide film is obtained by thermal oxidation of a silicon substrate, but since thermal oxidation requires a high temperature of 1000 C or more, it is not convenient for the present purpose. In this example, the S amount H4 and Ox t-react at a temperature of 300t:' or more and 500C or less, or at a temperature of 400C or more.
8iH at a temperature below or.

The 8'0@ film was grown in a vapor phase by reacting with and NO, and the 810. The film is used as a gate oxide film.

Conventionally, in order to form a source region and a drain region, a method of forming 90 layers or 00 layers by thermal diffusion has been generally used. However, this method cannot be used for the present purpose because it requires a heat treatment of 1 isoc@v. In the present invention, a method of forming a p+l-1 or 0+ layer by ion implantation is used instead of thermal diffusion. After ion implantation, heat treatment is performed to activate electrically, but at this time, the heat treatment and temperature are
It is necessary to keep the temperature lower than the softening point of the substrate used.

Therefore, for example, ion implantation with high activation is performed by heat treatment at a low temperature of 550C'8 degrees.
Or, for example, B9 ion? 5 after driving, just before the reverse annealing effect occurs.
A method such as heat treatment at a temperature of about 00C to 600C is adopted. In the case of p+ ions, As+ ions, etc., the reverse annealing effect is not as pronounced in the case of 80 ions, but it can be sufficiently activated by heat treatment at about 500C to 600C. Therefore, it is possible to form both the 90 layer and the n+ layer of gold in a low temperature process of about 500C to 6007:'. When using a substrate having a softening point higher than 800 C, such as ultra-hard glass, it goes without saying that heat treatment may be performed at 5 oocoa degrees.

By using the manufacturing method as described above, it is possible to obtain a semiconductor material that can be produced in large amounts or in a long length and has a carrier mobility of 151/v@(6) or more.

Hereinafter, the invention will be explained in detail with reference to Examples.

An embodiment in which a channel is formed in the surface layer of a polycrystalline silicon film to fabricate a nine-structure n-channel MO8 field effect transistor will be described with reference to the process-explanatory cross-sectional diagram of FIG.

First, the substrate is placed in a vacuum evaporation device capable of achieving an ultra-high vacuum. The equipment may be of general type. On Corning 7059 glass substrate 1, substrate temperature 600C5 vacuum degree during deposition 8
X10""'I'orr, deposition rate 5000A/hou
A silicon film 2 i is formed by vacuum deposition under the conditions of r.
Deposit to a thickness of 1.5 μm.

(I11 Zuken)). The silicon film 2 formed is - slightly boron doped p! II polycrystalline silicon To
#), the crystal grain size is approximately 2000%, and the carrier mobility is approximately 1/V·(6).

Next, 8i0. The film is deposited to a thickness of 3t-500OA <m2 (Fig. Φ)). Next, as shown in Figure 142 (C), this sio.

A window is formed in the film for the source and drain regions, and the distance between the source and drain regions is 20 μm. Therefore, the channel length is 20 μm. Next, P0 ions with an energy of 100k15V are implanted at a dose of 1×10''/clIM'', and heat treatment is performed at 600C for 30 minutes in an N atmosphere to form an n0 layer 4 in the drain region.

Next, as shown in Figure %w42 (e), the field oxide film 5t is
-remain and remove gi□. A gate oxide film of 8i0. A film 6 is deposited to a thickness of 7,500 mm (Fig. 2 (January). Furthermore, holes for electrode contact are made as shown in No. 211Il (2) using a photoetch process, and after Alt is deposited on the entire surface, a film is deposited using a photoetch process. A
t is processed to form a source electrode 7, a drain electrode 8, and a gate electrode 9t. After this, 400C in H8 atmosphere
Heat treatment is performed for 30 minutes. Through the above steps, a thin film MO8 field effect transistor having an n9 structure in which a channel with a length of 20 μm was provided in the second layer of the polycrystalline silicon film was manufactured. This semiconductor device exhibits good and stable characteristics as a transistor.

Figure W2B shows an example of the characteristics of the prototype MOSFET at Xa. Determine the relationship between the drain voltage 1M I n and the drain voltage voiW using the gate voltage Vo't parameter.

In this example, for a channel length of 20 μm, the crystal grain size is approximately 2000 μm. Therefore, a sufficiently large number of crystal grains exist in the traveling direction of the carrier, the carrier is influenced by a large number of crystal grain boundaries, and the effects of this influence make the characteristics uniform when many devices are manufactured.

Note that although the above explanation uses a silicon film,
It goes without saying that the same idea can be applied to other semiconductor materials, such as germanium films.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the relationship between the thickness of the deposited film and the crystal grain size, 18
Figure 2 is a cross-sectional view showing the process of manufacturing MO8F'E'l' using a polycrystalline semiconductor film, and Figure 3 is an example MO8FE.
T+2)% sex diagram. l... Amorphous or polycrystalline substrate, 2... Polycrystalline silicon, 3...8 i 0. Film, 4... Impurity region, 5... Field oxide film, 6... Gate oxide film, ? , 8.9...electrode. Agent Patent Attorney Toshiyuki Usuda 1st Main Reed Membrane 4 (Hano ρ to zl) ”za to 56me Sρ (V)

Claims (1)

[Scope of Claims] 1. A polycrystalline semiconductor thin film is formed on a predetermined substrate, and at least a pair of electrode image areas for causing carriers to travel through the polycrystalline semiconductor thin film and means for controlling the carriers are provided. In the polycrystalline thin film transistor having a polycrystalline thin film transistor, the length of the region where the carrier gold travels is at least 10 times the size of the crystal grain in the substantial carrier traveling direction t-V.
A polycrystalline thin film transistor characterized by: 2. In the polycrystalline thin film transistor according to claim 1, the length of the region through which the carriers travel is 50 times or more the size of the crystal grain in the substantial carrier traveling direction. ! It is my honor. 3.4! In the polycrystalline thin film transistor according to claim 1 or 11!2, it is defined as t% mold that each crystal grain size in at least the region where carriers travel is 150 t1 m or more. 4.41 The polycrystalline thin film described in Claims 1 to W43 is characterized in that it is formed by a vacuum evaporation method under a high vacuum at a pressure of less than IXIG-'''fort.