JPS5831457A - デ−タ処理装置 - Google Patents
デ−タ処理装置Info
- Publication number
- JPS5831457A JPS5831457A JP56129105A JP12910581A JPS5831457A JP S5831457 A JPS5831457 A JP S5831457A JP 56129105 A JP56129105 A JP 56129105A JP 12910581 A JP12910581 A JP 12910581A JP S5831457 A JPS5831457 A JP S5831457A
- Authority
- JP
- Japan
- Prior art keywords
- shift
- logic
- flop
- flip
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56129105A JPS5831457A (ja) | 1981-08-17 | 1981-08-17 | デ−タ処理装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56129105A JPS5831457A (ja) | 1981-08-17 | 1981-08-17 | デ−タ処理装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5831457A true JPS5831457A (ja) | 1983-02-24 |
| JPS6141426B2 JPS6141426B2 (enExample) | 1986-09-16 |
Family
ID=15001188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56129105A Granted JPS5831457A (ja) | 1981-08-17 | 1981-08-17 | デ−タ処理装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5831457A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63123135A (ja) * | 1986-11-13 | 1988-05-26 | Nec Corp | シフトパス診断方式 |
| JPS63280342A (ja) * | 1987-05-13 | 1988-11-17 | Nec Corp | シフトパス故障診断装置 |
-
1981
- 1981-08-17 JP JP56129105A patent/JPS5831457A/ja active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63123135A (ja) * | 1986-11-13 | 1988-05-26 | Nec Corp | シフトパス診断方式 |
| JPS63280342A (ja) * | 1987-05-13 | 1988-11-17 | Nec Corp | シフトパス故障診断装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6141426B2 (enExample) | 1986-09-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Buneman et al. | Path constraints on semistructured and structured data | |
| Probst et al. | Using partial-order semantics to avoid the state explosion problem in asynchronous systems | |
| JPH1063707A (ja) | 論理回路検証装置および論理回路検証方法 | |
| Kohavi et al. | Variable-length distinguishing sequences and their application to the design of fault-detection experiments | |
| Clarke et al. | A unified approach for showing language containment and equivalence between various types of ω-automata | |
| US20090012771A1 (en) | Transaction-based system and method for abstraction of hardware designs | |
| Berger et al. | Fault detection in fanout-free combinational networks | |
| JPS5831457A (ja) | デ−タ処理装置 | |
| Kleijn et al. | Process semantics of P/T-Nets with inhibitor arcs | |
| JPS58151646A (ja) | 加算器用オ−バ−フロ−検出器 | |
| US6637009B2 (en) | Optimization of a logic circuit having a hierarchical structure | |
| Narasimhan et al. | Early comparison and decision strategies for datapaths that recover from transient faults | |
| Abdi et al. | Packing odd T‐joins with at most two terminals | |
| Rutten | A structural co-induction theorem | |
| US9292390B2 (en) | Pulsed-latch based razor with 1-cycle error recovery scheme | |
| Jarrow | An integrated axiomatic approach to the existence of ordinal and cardinal utility functions | |
| US2974309A (en) | Magnetic core logical circuits | |
| Johannes et al. | SLOCOP-II: A versatile timing verification system for MOSVLSI | |
| DesMarais et al. | Reliability analysis of logic circuits | |
| US20230080172A1 (en) | Transmitting node instructions | |
| SU1012268A2 (ru) | Модель ветви графа | |
| SU357563A1 (enExample) | ||
| Panangaden | A Proof System for Dataflow | |
| Moitra et al. | A Proof System for Dataflow Networks with Indeterminate Modules | |
| Mori et al. | On the power of self-testers and self-correctors |