JPS5830648B2 - doukishin gou gousei warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for synthesizing a data signal magnetically recorded on a magnetic tape and a synchronization signal (index pattern signal), and relates to a circuit configuration that reduces erroneous detection of an index pattern signal during playback. It is something.

Data signals recorded on magnetic tape generally include audio signals (recorded signals such as music), image signals, and data signals from measuring instruments.

Each modulation method is used for these carrier signals depending on the purpose.

In addition, in image signals, etc., in addition to image information, synchronization signals (frame, line synchronization signals), that is,
An index pattern signal must be inserted.

Figure 1 shows an example of a conventionally used synchronization signal synthesis circuit, in which PPM (Pulse PPM) is used for the carrier signal.
hase Modulation+) using a modulation signal,
This circuit inserts an index pattern signal into the synchronization signal.

In FIG. 1, 1 is an index pattern generation circuit;
2 is an input terminal for index insertion signal In, 3 is an index signal synthesis circuit, and 4 is an index pattern signal I.
5 is an input terminal for the PPM modulation signal, and 6 is an output terminal of the index signal synthesis circuit 3.

Since the data signal is a PPM modulated signal as shown in FIG. 2, the reference pulses 81, 82 . The amount of time TI) from... to the next data pulse]), l)2...... TD2. . . . corresponds to the data signal.

Assume that an index insertion signal In is added between the reference pulses 82 and 83 of this PPM modulation signal, and its index pattern is expressed as
1) I in FIG.
An encoded index pattern signal as shown in O is obtained.

That is, when this DIO signal is recorded on a magnetic tape and reproduced, the reproduced signal contains data signals as well as J", 'Xl".

It can be seen that if the patterns 1 and 0 are detected, an index pattern signal is detected.

The disadvantage of this method is the amount of data (TDl, TD2゜...
) by “O”, “0” or “l”.

The pulse interval of l is different, and some cases are narrow.

Therefore, if the area is narrow, it may cause false detection due to the recording density characteristics of recording and reproduction.

For example, if the maximum recording frequency component that can be recorded on a magnetic tape is fmax, the minimum pulse interval (data pulse D1 and reference pulse S2) rmin of the PPM modulated signal in FIG. 2 is -7 degrees.

On the other hand, in the PPM modulated signal D I O including the index pattern, since the data pulse D1 and the reference pulse S2 are continuously generated for 50"'X O",
The l wave number component Dt is fD,max-,=2fmax, which corresponds to recording a frequency twice the maximum recording density.

Therefore, if the pulse interval of the index pattern signal is limited to the minimum recordable interval, there is a drawback that the recording density of the PPM modulated signal becomes small.

SUMMARY OF THE INVENTION In view of the above problems and drawbacks, an object of the present invention is to provide a synchronization signal synthesis circuit in which the pulse interval of an index pattern signal does not reduce the recording density of a PPM modulated signal.

A feature of the present invention is that when a synchronization signal is inserted into a PPM modulation signal, the index pattern signal partially removes the reference pulse or data pulse depending on the type of synchronization signal, thereby changing the peak value of the reference pulse. One truth value, the peak value ■2 (\■1) of the data pulse, is used as the other truth value to construct a signal corresponding to the synchronization signal.

FIG. 3 shows an embodiment of the synchronization signal synthesis circuit of the present invention.

FIG. 4 shows the operation time sequence of FIG. 3 (the figure shows only the case where the index insertion signal LS corresponding to the synchronization signal indicating the line start is inserted).

In FIG. 3, 10 is P given from input terminal 11.
This is a separation circuit that separates the PM modulation signal into a reference pulse 8N (12 is its output terminal) and a data pulse 1)N (13 is its output terminal).

This separation circuit can be realized with a configuration as shown in FIG.

In FIG. 5, C1x C2 are capacitors, r1 to r
8 is a resistor, and Q1 to Q3 are transistors.

20 in FIG. 3 is an index insertion signal FS.

This is a pattern conversion circuit that generates pulse removal signals R1 to R8 corresponding to each index insertion signal from an output terminal 24 when LS and FE are applied from input terminals 21, 22 and 23, respectively.

This conversion circuit 20 can be realized with a configuration as shown in FIG.

In Fig. 6, C3 to C5 are capacitors % rg to r
15 is a resistor 1), and fl)2 is a diode.

30 in FIG. 3 is a 4-bit shift register shifted by the reference pulse SN applied to the clock terminal 33, and 31 is the pulse removal signal R1s R3s R5s.
The reset terminal of the shift register 30 receives R7 as an input, 32 is the input data terminal of the shift register 30 to which the "l" level is always added, and 34 is the shift register 30.
This is the positive output terminal of

40 is a 4-bit shift register shifted by the data pulse DN; 43 is its clock input terminal;
1 is the reset terminal of the shift register 40 which inputs the pulse removal signals R2s R4sR6, R8, 42 is the manual data terminal of the shift register 40 to which the "l" level is always added, and 44 is the positive output terminal of the shift register 40. be.

50 is a circuit obtained by the configuration shown in FIG. 7, which includes a pulse mixing circuit for synthesizing index pattern signals;
51 is a mixed pulse input terminal, and 52 is its output terminal.

In Figure 7, C6s and C7 are capacitors, R16s
rl□ is a resistor, and N1 to N3 are NAND logic elements.

The operation shown in FIG. 3 will be explained using the time sequence shown in FIG. 4.

A PPM modulated signal which is constantly generated and consists of a reference pulse having a peak value v1 and a data pulse having a peak value 2V\V, is separated by a separation circuit 10 into a reference pulse SN and a data pulse DN.

On the other hand, the 4-bit shift register 30 receives the reference pulse S
The shift register 40 is shifted by the data pulse DN.

Furthermore, since the data input terminals 32 and 42 of the shift registers 30 and 40 are always at 1 level, when the index insertion signals FS, LS, and FB are not applied, the shift registers 30 and 40
The outputs SNH and DN of the positive output terminals 34 and 44 of
H or always at XXl" level.

If an index insertion signal is added here (Fig. 3,
In FIGS. 4 and 6, three types of index insertion signals FS, LS and FE are shown (10 bits).
2 to 4 bit pulse SN, I from Sl less SN, DN
) It is possible to configure various index pattern signals by combinations of removing N. 3
1 and 41.

For example, the index pattern signal for the line synchronization signal LS is as shown in FIG. 4 (l, 0, 0, 10...
ljl, 0), it is necessary to remove the first reference pulse SN and the sixth data pulse DN.
It can be seen that signals need only be applied to R1 and R8 of the reset terminals 31 and 41 of the shift registers 30 and 40.

That is, when the shift register 30 is shifted by the reference pulse SN in this state, the positive output terminal 34
As shown in SNH shown in FIG. 4, after the index insertion signal LS is added, the level is 90'' from the first pulse to the third pulse.

When the shift register 40 is shifted by the data pulse DN, the index insertion signal LS is applied from the positive output terminal 47 as shown in FIG. up to 9
It can be seen that the level is 0".

In the mixing circuit 50, the output signals SNH, 1) NH of the shift registers 30.degree.

Here, the pulse mixing circuit 50 will be explained using a specific circuit example shown in FIG. 7 and an operation time sequence shown in FIG. 8.

When there is no index pattern signal, the positive outputs SNH2 of shift registers 30 and 40
It's N Hゝl''.

Therefore, the reference pulse SN passes through the NAND logic elements N1 and N3, an "l" level, that is, a pulse on the positive side appears at the point @ in FIG. 7, and the data pulse I)N passes through the NAND logic element N2, An 'XO' level, that is, a negative pulse appears at the point.

Therefore, when there is no index insertion signal, the input signal D - the output signal 1) IO.

On the other hand, when there is an index insertion signal, the positive outputs of shift registers 30 and 40 become 5NH-0 and 1)NHlo'', respectively, in response to the pulse removal signal.

Therefore, as can be seen from FIG. 8, the first reference pulse S after the index insertion signal LS is inserted
N is removed by NAND logic element N1, and the sixth data pulse DN is removed by NAND logic element N2.

That is, the index pattern signal is the reference pulse SN
Alternatively, since the data pulse DN is removed and configured, the pulse interval that occurs consecutively with 1.1 or 0"SS □" of the same phase (plus side or minus side pulse) when removed is manually PPM modulated. It can be seen that the pulse interval is not narrower than the pulse interval of signal 1).

Next, a circuit for detecting an index pattern signal from a PPM modulated signal having the above configuration will be described with reference to FIGS. 9 to 11.

Figure 9 shows the data signal 1) including the index signal.
10 is a block diagram for detecting (separating) only the index pattern signal from N, and FIG. 10 is a diagram showing the time sequence thereof.

100 in FIG. 9 is a circuit that separates the PPM modulation signal I) IN applied to the input terminal 101 into a negative pulse CP- and a positive pulse CP+, 103 is a negative pulse output terminal, and 102 is a positive pulse output. It is a terminal.

This separation circuit 100 has the same circuit configuration as shown in FIG. 5, and the reference numeral 11 is equivalent to 10L12 and 102, and 13 is equivalent to 103, respectively.

104 is a flip-flop circuit, 105 is a set terminal, 106 is a reset terminal, and 107 is a positive output terminal.

108 is the clock pulse C from the CP- and CP0 signals.
It is a NAND logic element that generates P.

110 is a shift register circuit having a 7-bit parallel output, 111 is a data input terminal, 112 is a clock pulse CP terminal, and 113 to 119 are shift register circuits 11.
0 parallel output terminal.

120 is a logic circuit that detects a synchronization signal from the index pattern of Q, A to G as shown in the table below;
1 to 128 are logic input terminals, and 129 is a logic output terminal.

FIG. 11 shows a specific configuration of this logic circuit 120.

The operation of the circuit shown in FIG. 9 will be explained with reference to the time sequence shown in FIG.

Incidentally, FIG. 10 shows an example in the case of the above-mentioned line synchronization signal LS.

The input PPM modulated signal DIN is separated into CP- and CP+ by the separation circuit 100.

Since CP- and CP+ are applied to the reset terminal 106 and the set terminal 105 of the flip-flop 104, the positive output 107 of the flip-flop has a waveform as shown at Q in FIG.

When this output Q is used as data input to the shift register 110 and shifted by the crop pulse CP, the parallel outputs A to G have waveforms sequentially shifted by l clocks.

Here, the logic circuit 120 has input terminal signals Q, A...
...G is (0, l, t.

o, t, o, o, t), a pulse is generated at LS of the output terminal 129.

Other index signals FS as shown in the table below.

Similarly, in the case of FB, it is configured to occur in each pattern.

With such a circuit, it is possible to detect an index pattern signal from a PPM modulated signal containing an index pattern created according to the present invention.

To show one example of the specific effects of the present invention, in the conventional index signal synthesis circuit shown in FIGS. 1 and 2, the reference pulse SN and data pulse DN of the PPM modulation signal are As mentioned above, the pulse is 0, O or 1.
．． 1, it must be possible to record at a density twice as high as the maximum recording density of the PPM modulation signal.

Therefore, even if the PPM modulation signal can be recorded and reproduced, the index pattern signal causes malfunctions due to high recording density.

Furthermore, if the maximum recording density on the magnetic tape is adjusted to the index pattern signal, there is a drawback that the recording density of the PPM modulation signal decreases.

On the other hand, the synchronization signal synthesis circuit according to the present invention shown in FIGS. 3 and 4 removes the pulse SN or DN when configuring the index pattern signal, so the frequency is lower than that of the PPM modulation signal. becomes a frequency component.

Therefore, the recording density of the PPM modulated signal is never higher than the maximum recording density, and even if the index pattern is inserted, this does not affect the recording density of the PPM modulated signal.

- Therefore, if the PPM modulation signal can be recorded and reproduced, the index pattern signal can be detected without malfunction, and the recording density on the magnetic tape will not decrease.

As can be seen from the above description, according to the present invention, it is possible to obtain a synchronization signal synthesis circuit that does not reduce the paris interval of the index pattern signal or the recording density of the PPM modulation signal when inserting the synchronization signal into the PPM modulation signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a conventional synchronization signal synthesis circuit, FIG. 2 is a time chart showing the operation time sequence of FIG. 1, and FIG. 3 is a block diagram showing an example of the configuration of a synchronization signal synthesis circuit according to the present invention. 4 is a time chart showing the operation time sequence of FIG. 3, FIG. 5 is a circuit diagram showing a specific example of the signal separation circuit of FIG. 3, and FIG. 6 is a specific example of the conversion circuit of FIG. 3. 7 is a circuit diagram showing a specific example of the pulse mixing circuit shown in FIG. 3, FIG. 8 is a time chart showing the operation time sequence of the pulse mixing circuit shown in FIG. 7, and FIG. 9 is a circuit diagram showing a specific example of the pulse mixing circuit shown in FIG. 3. 10 is a block diagram showing a circuit for detecting an index signal from a PPM modulated signal created by the circuit of FIG. 10 is a time chart explaining the operation of FIG.
FIG. 1 is a circuit diagram showing a specific example of the logic circuit shown in FIG. 9. Explanation of symbols, 10... Separation circuit, 11...
...Input terminal, 20...Conversion circuit, 21-23
...Index insertion signal, 24...
Pulse removal signal, 30°40...Shift register, 50...Pulse mixing circuit, 52...
・Mixed pulse output terminal.

Claims (1)

[Claims] 1 PPM consisting of a reference pulse that occurs steadily and has a peak value of ■1, and a data pulse that has a peak value of ■2←\■1)
In devices that magnetically record modulation (pulse phase modulation) signals on magnetic tape, the position and number of reference pulses or data pulses to be removed from the PPM modulation signal are determined depending on the type of synchronization signal, and thereby 1. A synchronization signal synthesis circuit characterized in that one truth value and (2) are set as the other truth value, and an index pattern signal corresponding to the synchronization signal is intercepted.