JPS5830281A - Horizontal afc circuit - Google Patents

Abstract

PURPOSE:To eliminate obstacles given by a vertical synchronizing pulse to a horizontal AFC circuit, by deriving the vertical synchronizing pulse from a composite synchronizing signal at the Miller integrating circuit, and by interrupting the operation of a phase comparactor with the vertical synchronizing pulse. CONSTITUTION:When a composite synchronizing signal (a) is inputted into an input terminal 9, the amplitude of the equalizing pulse and the horizontal synchronizing pulse is reduced by a Miller integrator composed of a resistance 10, a condenser 11, and an amplifier 12, and a pulse (b) is generated by taking out the vertical synchronizing pulse only. On the other hand, when the horizontal synchronizing pulse (c) is given to an input terminal 13, a phase comparator input transistor 14 conducts only in the period of the horizontal synchronizing pulse. Moreover, a reference DC voltage V16 is given to the base of a transistor 17, and a saw tooth wave in which fly-back pulse is integrated is given to the base of a transistor 18.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a horizontal AFC circuit for a television receiver, in which a vertical synchronization pulse derived from a composite synchronization signal selects whether to execute or stop circuit operation.

The horizontal AFC circuit of a television receiver has the function of preventing screen disturbances caused by external noise and the like and providing a stable screen.

FIG. 1 shows a block diagram around a conventional horizontal AFC circuit.

The configuration and operation will be briefly explained below. When a composite video signal is applied to the input terminal 1, the video signal and the composite sync signal are separated by the sync separation circuit 2, and only the composite sync signal is sent to the sync separation output terminal 3.

is output to. This composite synchronization signal is supplied to a horizontal AFC input terminal 6 via a capacitor 4.

Here, if the value of capacitor 4 is selected, one with a low frequency such as the vertical synchronization pulse should be selected for the horizontal AF.
It is possible to prevent this from occurring at the C input terminal 5. Therefore, the horizontal synchronization pulse and equalization pulse, which have a higher frequency than the vertical synchronization pulse, are transmitted to the horizontal AFC terminal via the capacitor 4.

The horizontal synchronizing pulse is a pulse that should also serve as a reference for the operation of the phase comparator 6, which is the main part of the horizontal AFC circuit, and is a sawtooth wave (
(sawtooth wave), frequency and phase comparisons are made. , 7 is the difference resulting from comparison of the frequency and phase between the horizontal synchronizing pulse and the sawtooth wave in the 3-phase comparator 6, which is the sawtooth wave input terminal of the horizontal AFC circuit to which the above sawtooth wave is supplied. Current or differential voltage is horizontal AF
It is output to the C output terminal 8. The difference current or voltage is
It has the function of controlling the horizontal oscillator connected to the next stage of the horizontal AFC output terminal 8, and controls the oscillation frequency and phase of the horizontal oscillator to match the horizontal synchronizing pulse.

It is clear that in the conventional horizontal AFC circuit shown in FIG. 1, in order to supply the horizontal synchronizing pulse to the phase comparator 6, a capacitor 4 having the role of a bypass filter must be provided.

Furthermore, the circuit shown in the block diagram of Fig. 1 is integrated into a semiconductor integrated circuit (
(hereinafter referred to as IC), the horizontal AFC input terminal 6
It is clear that this is not a good idea when promoting the use of ICs.

FIG. 2 shows the configuration of a horizontal AFC circuit in which a composite synchronization signal is directly supplied to the horizontal AFC circuit in order to eliminate the capacitor 4, which is an obstacle to IC implementation, as described above. As is obvious when compared with FIG. 1, it is a configuration that can reduce the capacitor 4 and the horizontal AFC input terminal 6, and is suitable for IC implementation. Since the vertical synchronizing pulse width is relatively wide, the horizontal AFC circuit's smoothing filter does not smooth the signal sufficiently, causing the problem that the upper part of the screen is curved.

It should be noted that if the smoothing is done sufficiently, a problem arises in that the response of the horizontal AFC circuit becomes slow.

Both of the horizontal AFC circuits shown in FIGS. 1 and 2 cannot perform normal operation as a horizontal AFC during the vertical synchronization pulse period. However, as described above, the former configuration is not affected by the vertical synchronizing pulse, but the latter has the inherent problem that the vertical synchronizing pulse adversely affects the normal operation of the horizontal AFC circuit.

The present invention has been made to overcome the above-mentioned disadvantages, and when converting a horizontal AFC circuit into an IC, a vertical synchronization pulse is derived from a composite synchronization signal using a Miller integration circuit. Phase comparator 6 due to vertical synchronization
This is to block the operation of the That is, the cutoff control of the phase comparator by the vertical synchronizing pulse is equivalent to blocking the coupling of the vertical synchronizing pulse to the phase comparator by the capacitor 4 in FIG. Furthermore, as in the configuration shown in FIG. 2, the composite synchronization signal can be directly supplied to the horizontal AFC circuit, and the effect of reducing the number of horizontal AFC input terminals 5 can also be obtained.

The circuit shown in FIG. 3 is a horizontal A
This is an FC circuit, and the waveforms of each part are also described.

The configuration and operation will be explained below.

When the composite synchronization signal shown in FIG. 3(a) is applied to the composite synchronization signal input terminal 9, the resistor 10. As shown in FIG. 3 (b), the Miller integrating circuit consisting of the capacitor 11 and the amplifier 12 outputs the following signals to the output terminal X of the Miller integrating circuit.
The amplitudes of the equalization pulse and the horizontal sync pulse are reduced, resulting in a pulse from which only the vertical sync pulse is derived. By the way, the product of the resistance R1° of the resistor 1o in the Miller integration circuit and the capacitance value C11 of the capacitor 11, that is, τ=R1o-C
The integration time constant τ shown in 11 is set to be sufficiently large for narrow pulse widths such as equalization pulses and horizontal synchronization pulses, and for relatively narrow pulse widths such as vertical synchronization pulses. It is known that if the curve is selected to be sufficiently small by /J% for a wide nose, the waveform shown in FIG. 3(b) can be obtained.

On the other hand, when a horizontal synchronization pulse shown as (/→ is applied to the horizontal synchronization pulse input terminal 13), the phase comparator input transistor 14 becomes conductive only during the horizontal synchronization pulse period.

A reference DC voltage V 1 is applied to the base of one transistor 170 of the differential amplifier connected to the reference voltage terminal 16 . The base of the transistor 18 whose base is connected to the sawtooth wave terminal 196 has a sawtooth wave curve obtained by integrating the flyback noise ζ, and if the DC voltage is set equal to the above-mentioned 16, then Six sawtooth waves shown in FIG. 3) are superimposed on the pace of the transistor 18, centering on .

Under the following conditions, the horizontal synchronization/curse shown in (c) and the frequency and phase force of the sawtooth wave shown in (b) are compared, and the resulting difference current or voltage is
It is led out to the C circuit output terminal 8. The horizontal synchronization pulse input terminal 13 is supplied with a composite synchronization signal whose polarity is inverted, that is, the composite synchronization signal shown in FIG. Since it is in the same state as the block diagram, the same problems will exist.

Note that the pulse waveform shown in FIG. 3(c) shows only the horizontal synchronization pulse portion of the composite synchronization signal.

As shown in FIG. 3, the amplitudes of the equalization pulse and the horizontal synchronization pulse are reduced, and the pulse shown in (b) is connected to the common emitter point of transistors 7 and 18 and the collector of transistor 4 at point X. is given to. Here, if the amplitude of the vertical synchronizing pulse is higher than v16 and exceeds the forward bias condition between the bases and emitters of transistors 7 and 18, it is natural that transistors 7 and 18 is cut off, and the operation of the horizontal AFC circuit is stopped.

Transistors 2o and 21. Diode 22° Resistor 2
3 and 24 are elements constituting the phase comparator 6.

As shown in Figure 3 (b), the equalization pulse and the horizontal synchronization pulse generated at the output point X of the Miller integration circuit are different in amplitude. This is caused by the spike-like integral waveform being approximately half that of the horizontal synchronizing pulse.

As described above, the horizontal AFC circuit of the present invention interrupts the operation of the horizontal AFC circuit during the vertical synchronization pulse period, and even if the composite synchronization signal is applied as the reference input to the horizontal AFC circuit, the Since the capacitor 4 has the same effect as the capacitor 4 shown in FIG. 1, it is possible to prevent the vertical synchronization pulse from causing harmful effects on the horizontal AFC circuit. In addition, since the composite synchronization signal can be directly connected to the horizontal AFC circuit, there is no need to provide the horizontal AFC input terminal 5 as in the circuit shown in FIG. 1, and a horizontal AFC circuit suitable for IC implementation can be provided.

Although the horizontal AFC circuit of the present invention must include a circuit for deriving the vertical synchronization pulse as an essential component, the vertical synchronization pulse can also be used as a trigger force to synchronize the vertical oscillator.

If the above-mentioned utilization method is used, a secondary effect can be obtained that the capacitors and resistors used to configure the vertical integration circuit, which were impossible to incorporate into a single semiconductor substrate when integrated into an IC, are no longer required. It has great industrial value.

[Brief explanation of the drawing]

FIGS. 1 and 2 are diagrams illustrating a conventional horizontal AFC circuit. 9...Composite synchronization signal input terminal, 1o...
- Miller integration resistor, 11... Miller integration capacitor, 12... amplifier, 13...
Horizontal synchronization (Russ input terminal, 14... phase comparator input transistor, 16... reference voltage terminal,
17, 18-... Φ differential amplifier transistor, 19.
・0: Sawtooth wave input terminal. -1 kaku□

Claims (1)

[Claims] A horizontal AFC circuit characterized in that a composite sync signal is used as a reference input, a sawtooth wave derived from a flybank pulse is used as a comparison input, and circuit operation is cut off during a vertical sync pulse of the composite sync signal.