JPS5830137A - Manufacture of wafer - Google Patents

Manufacture of wafer

Info

Publication number
JPS5830137A
JPS5830137A JP12902381A JP12902381A JPS5830137A JP S5830137 A JPS5830137 A JP S5830137A JP 12902381 A JP12902381 A JP 12902381A JP 12902381 A JP12902381 A JP 12902381A JP S5830137 A JPS5830137 A JP S5830137A
Authority
JP
Japan
Prior art keywords
wafer
heat treatment
single crystal
uniform
specific resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12902381A
Other languages
Japanese (ja)
Inventor
Koji Ogawa
浩二 小川
Kiyoshi Hisatomi
久富 清志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12902381A priority Critical patent/JPS5830137A/en
Publication of JPS5830137A publication Critical patent/JPS5830137A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To obtain a wafer with uniform specific resistance by donor-killer heat treatment of a single crystal containing O more than 1.0X10<18>/cm<3> which is obtained by the CZ method, thereafter treating it at 550 deg.C-1,000 deg.C for more than 1hr. CONSTITUTION:A wafer is made from a single crystal Si containing 0 more than 1.0X10<18>/cm<3>, which is obtained by a CZ method, undergoes heat treatment at the temperature of 650 deg.C for 30-40min to eliminate donors. Then it is subject to another heat treatment at the temperature 550-1,000 deg.C to get a uniform specific resistance. The wafer is completed with chemical abrasion and mirror grinding. After this, uniform specific resistance distribution is maintained even after heating for a long time at about 1,250 deg.C. This phenomenon is specific to the wafer obtained by the CZ method: oxygen content contributes to this phenomenon. Heat lower than 550 deg.C is inappropriate because donors come into the wafer and the temperature higher than 1,000 deg.C may cause a lattice defect. Heat treatment for uniform specific resistance is effective only when it is carried out with a single crystal containing O more than 1.0X10<18>/cm<3> for more than 1hr.

Description

【発明の詳細な説明】 この発明はチ璽りラルスキ法(C2法)により得られた
単結晶からウェーハを製造するウェーハの製造方法に関
す石。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wafer manufacturing method for manufacturing wafers from single crystals obtained by the Chiral Ralski method (C2 method).

現在、半導体工業で使用されているシリコン材料にはチ
!クラルスキ法(CZ法)と70−ティングゾーン法(
FZ法)Kよる零種類がある。しかしながら、これらの
方法によるシリコン材料には、引上時の対流や回転(シ
ード、ルツー)等の影響により結晶内に不純物の不均一
分布(以下ストリエーシ璽ンという)が生じる・そのた
め、C2法により引上げられたシリコン単結晶から作ら
れたP型で結晶方位(100)で比抵抗40〜60麺の
ウェーハには、第1図に示すようにウェー測定法による
拡が)抵抗値を示し、単位は(Ω)である。また、横軸
はウェーハの直径方向における基準位置からの距離を示
し、単位は(■)である。
Currently, the silicon materials used in the semiconductor industry have CHI! Kralski method (CZ method) and 70-ting zone method (
FZ method) There are zero types depending on K. However, in the silicon materials produced by these methods, non-uniform distribution of impurities (hereinafter referred to as striations) occurs within the crystal due to the influence of convection and rotation (seeding, rooting) during pulling. A P-type wafer made from a pulled silicon single crystal with a crystal orientation (100) and a resistivity of 40 to 60 has a resistance value measured by the wafer measurement method, as shown in Figure 1, with a unit of is (Ω). Further, the horizontal axis indicates the distance from the reference position in the diametrical direction of the wafer, and the unit is (■).

このような比抵抗分布のバラツキのあるウェーハを用い
ることは、デバイスの微細化がサブミクロンに到達しよ
うとしている現在、しきい値電圧の変動等、製造歩留ま
シを低下させる原因となってしまう。
Nowadays, as device miniaturization approaches sub-micron dimensions, using wafers with such variations in resistivity distribution causes fluctuations in threshold voltage and other factors that reduce manufacturing yields. Put it away.

この発明は上記のような事情に鑑みてなされたもので、
C2法により得られた単結晶からストリエーシ冒ンの無
い均一な比抵抗分布を持ったウェーハを製造することが
できるウェーハの製造方法を提供することを目的とする
This invention was made in view of the above circumstances,
It is an object of the present invention to provide a wafer manufacturing method capable of manufacturing a wafer having a uniform resistivity distribution free from striations from a single crystal obtained by the C2 method.

以下、図面を参照してこの発明の一実施例を説明す本。Hereinafter, an embodiment of the present invention will be explained with reference to the drawings.

まず、第2図(A)に示すようなcz法により引上げら
れた〔O1〕ユ1.0XIO肩以上で〔C1〕ユ2 X
 10” ys−”のシリコン単結晶1をスライスし、
う、ピングして第2図03)に示すようなウェーハ2に
する0次K、このウェーハ2の酸素ドナー消去のための
熱処理(ドナーキラー熱処理)を650℃で30〜60
分行なう・この時の熱処理時間に対する酸素ドナーの消
滅する様子を第3図のグラフ図に示す・この図から、6
50℃で15分以上の熱処理で酸素ドナーが消滅してい
ることが分かる。
First, [C1] Yu2
Slice a 10"ys-" silicon single crystal 1,
Then, the wafer 2 was heated to 0-order K as shown in Figure 2 (03), and the wafer 2 was subjected to heat treatment (donor killer heat treatment) for eliminating oxygen donors at 650°C for 30 to 60 minutes.
・The disappearance of oxygen donors with respect to the heat treatment time is shown in the graph of Figure 3. ・From this figure, 6
It can be seen that oxygen donors are eliminated by heat treatment at 50° C. for 15 minutes or more.

なお、第3図のデータを得るのに用いた試料は、P型で
結晶方位が(100)で比抵抗が4501のものである
The sample used to obtain the data shown in FIG. 3 is of P type, has a crystal orientation of (100), and a resistivity of 4501.

このような通常のドナーキラー熱処理後、本願の特徴で
ある比抵抗分布を均一にする(ストリエーシ嘗ンを無く
す)ための熱処理を行なう0この熱処理は、550℃〜
1000℃で1時間以上行なうものである・この比抵抗
分布を均一にするための熱処理を行なった後、化学的研
磨および鐘面研磨を行ないウェーハが完成すゐ〇 このよう圧して作られたウェーハで、上記比抵抗分布を
均一にするための熱処理を650℃で1時間行なった場
合のウェーハの拡がシ抵抗測定法による比抵抗分布は第
4図■に示すようKなった。また、上記比抵抗分布を均
一にするための熱処理を650℃で2時間、5時間、1
0時間行なった場合のウェーハの比抵抗の分布は、それ
ぞれ第4図(B) 、第4図初、第4図0)に示すよう
罠なうた。なお、第4図(転)〜[F])の縦軸および
横軸は第1図におけるものと同様である。この第4図η
)〜の)から、通常のドナーキラー熱処理後、比抵抗分
布を均一にするための熱処理を行なうと、比抵抗分布が
均一化されていく様子が分かる。
After such normal donor killer heat treatment, heat treatment is performed to make the resistivity distribution uniform (eliminating striations), which is a feature of the present application.
The process is carried out at 1000℃ for over 1 hour. After heat treatment to make the specific resistance distribution uniform, chemical polishing and surface polishing are performed to complete the wafer. When heat treatment was carried out at 650° C. for 1 hour to make the resistivity distribution uniform, the resistivity distribution as measured by the resistance measurement method after the wafer spread became K as shown in FIG. In addition, heat treatment was performed at 650°C for 2 hours, 5 hours, and 1 hour to make the resistivity distribution uniform.
The distribution of resistivity of the wafer when the test was carried out for 0 hours is as shown in FIG. 4(B), FIG. Note that the vertical and horizontal axes in FIGS. 4 (roll) to [F]) are the same as those in FIG. 1. This figure 4 η
From ) to ), it can be seen that when heat treatment is performed to make the resistivity distribution uniform after the normal donor killer heat treatment, the resistivity distribution becomes uniform.

上記比抵抗分布を均一にするための熱処理を650℃で
10時間行なったウェーハに、1200℃〜1250℃
で30時間の高温熱処理を施しても、第5図に示すよう
に均一化された比抵抗分布は維持されていることがわか
る0 このような通常のドナーキラー熱処理後、比抵抗分布を
均一化するためあ熱処理をFZ法によ抄得られたウェー
−に行なっても、比i抗分布は均一化されないことから
、C2法により得られ九りエーハ特有の現象であること
が分かる。
The wafer was heat-treated at 650°C for 10 hours to make the resistivity distribution uniform.
As shown in Figure 5, even after 30 hours of high-temperature heat treatment, the uniform resistivity distribution is maintained. Therefore, even if heat treatment is performed on a wafer obtained by the FZ method, the specific i resistance distribution is not made uniform, which indicates that this is a phenomenon peculiar to wafers obtained by the C2 method.

そこで、C2法によや得られたウェーハに含有されてい
る酸素rO3〕がこの現象に関与していることが推察さ
れる。
Therefore, it is inferred that oxygen rO3] contained in the wafer obtained by the C2 method is involved in this phenomenon.

なお、上記比抵抗分布を均一化するための熱処理は、5
50℃未満であるとドナーが入抄込む温度であるので不
適であり、1000℃を越える温度であると、ウェーハ
和格子欠陥が発生する可能性がある。また、上記比抵抗
分布を均一化するための熱処理の時間は、第4図(kJ
〜(ロ)からも分かるように、1時間以上でないとその
効果がほとんど現われていない、さらに、C2法により
引上げられた単結晶における酸素の含有量が1゜0XI
O”/−以上でないと上記比抵抗分布を均一化するため
の熱処理を行表っても、比抵抗分布が均一化されるとい
う効果は上記実施例はどはっきり現われなかっ九・そこ
で、この発明の実施例では、CZ法により引上げられた
1、0×101s/−以上の酸素を含有する単結晶に、
上記比抵抗分布を均一化するための熱処理として。
Note that the heat treatment for making the resistivity distribution uniform is as follows:
If it is less than 50°C, it is unsuitable because it is the temperature at which donors are deposited, and if it exceeds 1000°C, wafer sum lattice defects may occur. In addition, the heat treatment time for making the resistivity distribution uniform is shown in Figure 4 (kJ
As can be seen from ~(b), the effect is hardly visible unless the time is longer than 1 hour.Furthermore, the oxygen content in the single crystal pulled by the C2 method is 1゜0XI.
O''/- or more, even if heat treatment is performed to make the resistivity distribution uniform, the effect of making the resistivity distribution uniform will not clearly appear in the above embodiment.9 Therefore, the present invention In the example, a single crystal containing oxygen of 1,0 x 101 s/- or more pulled by the CZ method,
As a heat treatment to make the resistivity distribution uniform.

550℃〜1000℃で1時間行なうようにしたもので
ある。
The test was carried out at 550°C to 1000°C for 1 hour.

以上述べたようにこの発明によれば、C2法により得ら
れた単結晶からストリエーシ田ンの無い均一な比抵抗分
布を持ったウェーハを製造することができるウェーハの
製造方法を提供するJことができる。
As described above, according to the present invention, it is possible to provide a wafer manufacturing method capable of manufacturing a wafer having a uniform resistivity distribution free of striations from a single crystal obtained by the C2 method. can.

【図面の簡単な説明】[Brief explanation of the drawing]

@1図は従来の方法により得られたC2法によるウェー
ハの比抵抗の分布を示すグラフ図、第2図(A)はCZ
法により引上げられたシリコン単結晶を示す図、第2図
CB)は上記シリコン単結晶をスライスしたウェーハを
示す図、第3図はドナーギラーの熱処理を行なった場合
の時間に対するその効果を示すグツ°7図、第4図(4
)〜(6)および第5図はこの発明の製造方法により得
られ九ウェーへの特性を示すグラフ図である。 1−シリコン単結晶、2−ウェー八〇
@Figure 1 is a graph showing the distribution of resistivity of a wafer obtained by the C2 method obtained by the conventional method, and Figure 2 (A) is a graph showing the distribution of resistivity of a wafer obtained by the C2 method obtained by the conventional method.
Figure 2 (CB) is a diagram showing a wafer obtained by slicing the silicon single crystal, and Figure 3 is a graph showing the effect of donor-Giller heat treatment on time. Figure 7, Figure 4 (4
) to (6) and FIG. 5 are graphs showing nine-way characteristics obtained by the manufacturing method of the present invention. 1-Silicon single crystal, 2-Way 80

Claims (3)

【特許請求の範囲】[Claims] (1)CZ法により得られた単結晶にドナーキラー熱処
理を行なう工程と、このドナーキラー熱処理後比抵抗を
均一化するための熱処理を行なう工程とを真備したこと
を特徴とするウェーハの製造方法・
(1) A method for manufacturing a wafer, which comprises a step of performing donor killer heat treatment on a single crystal obtained by the CZ method, and a step of performing heat treatment to make the resistivity uniform after the donor killer heat treatment.・
(2)上記CZ法によ〕得られた単結晶は1.0X10
  /d以上の酸素を含有しているシリコン単結晶であ
る特許請求の範囲#I1項記載のウェーハの製造方法◎
(2) The single crystal obtained by the above CZ method is 1.0×10
The method for manufacturing a wafer according to claim #I1, which is a silicon single crystal containing oxygen of /d or more◎
(3)  上記比抵抗を均一化するための熱処理は、5
50℃〜1000℃の温度における1時間以上の熱処理
である特許請求の範囲第1項記載のウェーハの製造方法
(3) The heat treatment to make the resistivity uniform is 5
The method for manufacturing a wafer according to claim 1, wherein the heat treatment is performed at a temperature of 50°C to 1000°C for 1 hour or more.
JP12902381A 1981-08-18 1981-08-18 Manufacture of wafer Pending JPS5830137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12902381A JPS5830137A (en) 1981-08-18 1981-08-18 Manufacture of wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12902381A JPS5830137A (en) 1981-08-18 1981-08-18 Manufacture of wafer

Publications (1)

Publication Number Publication Date
JPS5830137A true JPS5830137A (en) 1983-02-22

Family

ID=14999232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12902381A Pending JPS5830137A (en) 1981-08-18 1981-08-18 Manufacture of wafer

Country Status (1)

Country Link
JP (1) JPS5830137A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005579A1 (en) * 1990-09-21 1992-04-02 Komatsu Electronic Metals Co., Ltd. Semiconductor wafer heat treatment method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992005579A1 (en) * 1990-09-21 1992-04-02 Komatsu Electronic Metals Co., Ltd. Semiconductor wafer heat treatment method
US5385115A (en) * 1990-09-21 1995-01-31 Komatsu Electronic Metals Co., Ltd. Semiconductor wafer heat treatment method

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