JPS5829054A - Logical operation parity forecasting circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for double check for logical product and sum circuits, by forming the parity of logical product and sum from the result of logical product and sum and the parity of exclusive logical sum. CONSTITUTION:Input data a0-a7 and b0-b7 are inputted to a logical operation circuit in parallel, then logical operation is made respectively in a logical product circuit 1, a logical sum circuit 2 and an exclusive logical sum circuit 3 and the desired result of operation is selected at a selection circuit 4 for output. On the other hand, parities ap and bp for the data a0-a7 and b0-b7 are logically operated at an exclusive logical sum circuit 7 and inverted 10 to be a parity 15 of exclusive logical sum. Further, the exclusive OR of the parity 15 and the output of the circuits 1 and 2 is formed at circuits 11 and 12 to be a parity 13 of logical sum and a parity 14 of logical product. The parity of logical operation corresponding to the output of the circuit 4 is selected at a selection circuit 16 out of the parities 13-15 for output. The output of the circuit 16 is checked at a parity check circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logical operation parity prediction circuit, and more particularly to a circuit that predicts the parity of a logical operation from input data and its parity.

Conventionally, when checking logic operation circuits such as AND and OR, two identical logic operation circuits are provided and comparison checks are performed by duplication.

When creating parity for the result of a logical operation, it is generated using the result of a logical operation. Therefore, duplicate logic operation circuits, comparison circuits for the outputs of these circuits, and circuits for checking the comparison circuits are required, and the number of gates is considerably larger than in an operation circuit that does not generate or check parity. It has become.

FIG. 1 is a block diagram of a conventional logic operation parity generation circuit and check circuit.

Bit string a constituting one byte...a, and b00.
・When b7 is input in parallel to the logic operation circuits 5 and 6', the respective logic product circuits 1. The logical sum circuit 2 and exclusive OR circuit 3 perform logical operations on corresponding bits, and the selection circuit 2 selects and outputs a desired logical operation result.

The logic operation circuit 6' is duplicated, and the internal circuits of both are exactly the same. Further, the output of the logic operation circuit 5 is separated into three parts, one of which is input to the parity generation circuit 8 to generate logic operation parity. The other output is given as the result of the ttabm operation, and the remaining one is input to the comparison circuit 7. The comparator circuit 7 is used to perform a comparison check between the logic operation circuits 6 and 6', and one input thereof receives the output of the selection circuit 6. 6 selection circuits,
Depending on the diagnostic mode or the normal mode, one of the result data of the logical operation circuit δ' and other input data is selected and output. That is, when the diagnostic mode signal is logic ``0'', the selection circuit 6 converts the output of logic operation circuit b' into its IT ratio output, and when the diagnosis mode signal is logic ``1'', it selects the logic operation circuit @5. Select and output other input data other than the output of '.In other words, when the diagnostic mode signal is logic "1", the correct output value of the logic operation circuit 6' is determined by other inputs. By inputting data to the comparison circuit 7, the comparison circuit 7 converts the comparison result mismatch signal to logic "1".
” Check whether or not.

In FIG. 1, logical operation parity is created by a parity generation circuit 8 from the logical operation results.

ing. Friend, the combination of the circuit shown in Figure 1 with three-man AND/OR gates with bipolar outputs requires approximately 210 gates.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic operation parity prediction circuit that can generate logic operation parity and check a logic operation circuit with a small number of gates and stages, in order to eliminate such conventional drawbacks.

The logical operation parity prediction circuit of the present invention focuses on the fact that the parity of the result of the exclusive OR of two manually-powered data can be easily created as the negation of the exclusive-OR of the parities of two inputs. Create the parity of the result of the arithmetic doubling by the negative output of the exclusive OR of The feature is that the parity of the result of the logical product is created by the exclusive logical sum of the logical product.

Hereinafter, embodiments of the present invention will be explained with reference to Fig. 2.
In the logical operation parity prediction circuit shown in the figure, as in the conventional case, the bit string 1 . . . a constituting one byte is
Mato. By inputting . Logical operation results are selected and output. The logic operation circuits are not duplicated, and each has one
Each group is provided.

In FIG. 2, in addition to a set of logic operation circuits 1 and 2.3, there is also a circuit 9.3 that creates the exclusive OR negation of the parity ap*bp of input data. lO1 Exclusive OR of the output of AND circuit l and the output of circuit 10 @Route 11. A circuit 12 that takes the exclusive OR of the output of the OR circuit 2 and the output of the circuit 10, a parity selection/folding circuit 16, and a parity selection/folding circuit 16.
It consists of a check circuit 17.

The respective parities ap and b of input data 1 .

The parity of the exclusive OR becomes -5. Also, this parity-5 and theory NM! An exclusive OR of the outputs of the 111 circuit 1 is created by the circuit 11, and the output of this circuit 11 becomes parity -3 of the OR. Furthermore, an exclusive OR of the parity 16 and the output of the OR circuit 2 is created by the 1 DEG circuit 12, and the output of this circuit 12 becomes the AND parity -4.

Since a common selection control signal is input to the selection circuit 4 and the selection circuit 16, the parity of the logic operation corresponding to the appearance of the selection circuit cow is selected from the selection circuit 1 from parity -3 to 15.
6 and is selected by w.

The output of the selection circuit 16 is parity checked by a parity check circuit 17. This check can be performed by setting either parity a or b of the input data to be parity.

In this way, in the circuit shown in FIG.
There is no need to check the comparison by overlapping, and the 3rd generation of bipolar output
Approximately 14 when configured by manual AND/OR gate
This can be achieved with a small number of 0 gates.

Next, the logical behavior of each circuit in FIG. 2 will be explained.

First, the parity of the input data a...'t+bo...b is set to ap 1 bp, and the parity of the AND, OR, and EXCLUSIVE OR is n p e Op, respectively.
+・.

Then, these are expressed by the following equation.

-ILp691), ...O
), ., 10, and e are symbols indicating logical product, logical sum, and exclusive disjunct, respectively, and 1 is a symbol indicating negation of a.

Here, by transforming the above equation α), the value remains unchanged even if p is exclusively ORed twice, so let's create the following equation.

5-(ri1 Iku ``2'' I7 chosuei3 @peeP...
←).

Substituting the above equation C) into one of the equations (A) above, we get
It is shaped like this:

−((a, ・bo)e (ao ebo) ) (
9...69 ((at ・by)e(ay
eb)e8p-0e) Here, the following equation generally holds true.

(a-b) 69 (aeb) -a・b-a-b + a
Number b-h-b++ (a-b) N a-b+
(a-b) -a ・ b-a +b...
(6) Because, in the above formula (6), (a-b) −
h-b-.

(a-b)・a-b-a-b Therefore, the above equation (6) holds true as follows.

(&-b)■(&69b)-a-b+a-b+a-b-
a −b+aT (b+b) −a −b+m= (a
+a) -(b+a) -a+b Therefore, the above (6
) expression is converted as follows.

np-(NO+bo)e...e(ay+by)
eap, ,, 7) Equation (7) above is the arithmetic expression of the exclusive OR circuit 12 in FIG. It has also been mathematically proven that it is calculated by exclusive OR with (ap69bp-e11').

Next, in exactly the same way, the parity op of the logical sum in equation 3) can also be transformed using the following general equation.

(a + b) e (a (9b) = Ca + b) ・h − b (a + b) ・ a − b + (
a ten b) -a-b+(a-)-b) -a -b-a-
b ”・e)-C(al) 10b o)e(a
o■bo))e・-・α(&? ten sui■(ay eb
, ) ) 69 @,.

-C(ao-bo)...e(a,・17))eep
...0) Equation e) above is an arithmetic expression of the exclusive OR circuit 11 in FIG. ,, Ayu-
It has been mathematically proven that it is calculated by exclusive OR with @, ).

The parity check circuit 17 shown in FIG.
...0. ) and predicted parity (Op) are selected and output, these are taken in and fO0e01
(2)...eC, ) (EIOp) By performing the operation, it is checked whether the predicted parity Op is equal to the parity of the logical operation result.

As explained above, according to the present invention, the parity of logical product and logical sum is created from the parity of exclusive logical sum and the result of logical sum and logical product. Since there is no need for 2-city processing, and the parity of logical operations is predicted from human data and its parity, checking of the Validity/Chetsuta circuit can be easily performed by simply manipulating the data storage. Furthermore, the entire logic can be configured with a smaller number of gates compared to the duplex check.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional logic operation result and its check circuit, and 2114 is a block diagram of a thil-hori operation parity pre-circuit showing an embodiment of the present invention. 1: AND circuit, 2! OR circuit, 3.11.12: Exclusive OR circuit, 6. IQ! Selection circuit, 6°6'
:Logic operation circuit, 7! Comparison circuit, 8! Parity generation circuit, 9: Input data parity exclusive OR circuit, 10
! Inverter, 13! OR parity; 14: AND parity; 15: Exclusive OR parity; 17: Parity check circuit. Figure 1

Claims (1)

[Claims] In a logic operation circuit such as AND and OR, calculate the exclusive OR of the negative output of the exclusive OR of the parity of two people to the logic operation circuit and the result output of the above AND, and then means for obtaining the parity of the result of the logical product, and means for calculating the exclusive logical sum of the negative output of the exclusive logical sum of the parities of the two operators and the resultant output of the logical sum, and obtaining the parity of the result of the logical product. A logical operation parity prediction circuit having the following characteristics.