JPS5827436A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To make the operation of an interface circuit stable, by supplying a current applied to an output stage transistor (TR) of an I<2>L circuit from a current mirror circuit in response to the base current. CONSTITUTION:Currents supplied from an injector power supply 1 are equal when current sources 4 and 10 are of the same fro the constant current source 10 and an NPN TR11 constitute a current mirror circuit. When multicollectors 14 and 15 of the TR11 are of the same form, since the same current flows to both the collectors, 2/3 of the collector current of the TR11 flows to the collector of a TR5 via a current mirror circuit consisting of PNP TRs. Since the base current of the TR5 is the injector current of the source 4, the collector current to base current ratio of the TR5 is always unchanged to the fluctuation in the power supply voltage and the dispersion in components.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor circuit equipped with an output interface circuit used in a logic circuit that operates with a constant current source as a load.
(Integrate resistance Inje-ctlon Lo
The present invention relates to a circuit constructed using a gEC (integrated injection logic circuit).

Engineering! L has a switching transistor and a surrounding switching transistor in a single island-like region formed on the same semiconductor substrate, and a constant current source for injecting carriers into the switching transistor, and the collector output of the switching transistor is controlled by the base input of the switching transistor. It is something to control.

Figure 1 shows a basic interface circuit between I''L and peripheral circuits that has been proposed in the past, and connects the constant current source 4Fil end, which is made up of a horizontal PNP (horizontal PNP) transistor whose base is grounded, to the power supply terminal. 7 and the other end is connected to a vertical NPN (vertical NPN) range meter 50 pace whose emitter is grounded to form an I''L circuit 3t. The collector of the vertical NPN transistor 5 constitutes the interface circuit,
The base and one end of Rungis I6 are connected to the resistor 8 connected to the power supply terminal 1tC. The other end of the resistor 9 connected to the power supply terminal II/c is connected to the collector of the NPN transistor.

The operation of the conventional example shown in FIG. 1 is as follows.

That is, in FIG. 1, I2L is
The constant current source 4 of h□6. The resistance values of resistors 8 and 90 are B s and b , respectively.

The voltage between power supplies 1 and 2 is t-Vt, and transistors 5 and 6
, and the collector saturation voltage are respectively bar.

and VO16, the following equations (1) and (2) hold true.

That is, when transistor 5 is in a conductive state, transistor 5
Collector current flow to the current. 5Fi,,Ios=(Vl-
Vom5)/R8-=・-・-(1) IO! i"'IB
5・hFMS “”””’ (2).

As is well known, the relationship between the collector and emitter is reversed compared to the normal NPN) run raster, and it is generally called an inverted transistor, but the current amplification factor of such an inverted transistor is usually It is very small compared to the NPN) Runcistor, and even the one improved to I2L is ranked 2nd to 10th at a practical level.

In equations (1) and (2), h,,s:3 IB=
Assuming 20μA, I O,=50μA, Vl=5
If V vo15=o-tV, R11=81.7
To realize such a resistor on a semiconductor integrated circuit, a very wide i-term product is required, and at the same time, the accuracy of the absolute value of the resistance value R1 of the resistor 8 becomes very poor, and the interface with %I2L becomes Ω. It is unsuitable as a circuit.

In addition, since the constant current supplied to I2L changes regardless of the value of the resistor 8, the base current of the transistor 6 cannot be fully drawn by all the transistors 5, and the transistor 6
As the interface circuit becomes sufficiently non-conductive, it cannot be expected to operate stably as an interface circuit.

SUMMARY OF THE INVENTION An object of the present invention is to propose a semiconductor integrated circuit including an interface circuit that is useful and operates stably.

That is, according to the present invention, the l! an L circuit, a first vertical transistor having first and second collectors, the first collector being connected to the pace, and a current mirror circuit to the second collector of the first vertical transistor; A semiconductor circuit including a second vertical transistor whose collector is connected is obtained.

Next, the present invention will be explained in more detail with reference to the drawings.

Figure 1s2 is an interface showing an embodiment of the present invention.

- This is an example of an integrated circuit, and the same parts as in FIG.

In Figure 2, the pace is grounded and the nine-horizontal PNP)
The constant current sources 4 and 10 constituted by Runsistors are connected to one end of the tube power supply terminal 7 and the other end of the iv terminal is grounded.
PN) 9y Jis is connected to the pace of 15 and 11 respectively. 411 of the collectors of the vertical NPN) run transistors 11 are assigned to the pace, and at least one of the remaining collectors is output as a constant current output to the NPN ) The collector and emitter of Runcistor 5 are grounded and 9N
PN) I can relate to the pace of Run Sister 6.

The collector of the transistor (NPN) is connected to the power supply l via a resistor 9.

The operation of the interface circuit having such a configuration will be described next.

The basic operation of the embodiment of the present invention shown in FIG. 2 is the same as that of the conventional example shown in FIG. 1, and detailed explanation will be omitted. The same symbols used in the explanation of FIG. 81 are also used in FIG. 3.

The current (injector current) supplied by the same injector power supply 1 is equal if the current sources 4 and 10 have the same shape, and the constant current source 10 and the NPN) run transistor 11 constitute a current mirror.

Here, assuming that the multi-collectors 14 and 15 of the NPN) run transistor 11 have the same shape, %hF111=3! :
L, injector current Ijyu. =20μA, II 1G=IB11 +3IB11 --” (
3) 20μA=4IB11.1111=5J1 person Therefore, Io, 1=15μ input. Since the same current flows through the collectors 14 and 15 of the transistor 11, the collector current of the transistor 5 is 2/3 of %l0II, ie, lQm, through the current formed by the PNP transistors 12 and 13.

Furthermore, the base current of the transistor 5 is the injector current 1j4 of the constant current source 4, and assuming that the constant current sources 4 and 10 have the same shape, Ij4=Ij 1o=20μperson−hFllll=3(=h
F111) NPN) Runsista 5 is engineering j4Xh,
! Current can flow through the collector up to I=60μ.

Ij4×hymi>Iat, ・・・・・・・・・
...(4) If all the conditions are satisfied, it is sure to be NPN) The transistor becomes non-conductive. In addition, the constant current sources 4 and 10 are constant current sources of the same shape connected to the same power supply 7, and are injector current sources of I"L, so the relative fluctuation is very small and in any case I It is considered that j 1o=I j 4 holds true.

Therefore, the collector current to pace current ratio of NPN) Runsistor 5 always takes a constant value regardless of power supply voltage fluctuations, element variations, etc., making it an extremely stable process! An L interface circuit is obtained.

NPN) Ranjistaro current amplification factor hB6 Ir1sN
PN) Current amplification factor of Lancistor 5, 8. hF16>hFIB compared to
...(5), and ■. 11 (NPN) can be enough base current to cause transistor conduction.

As is clear from the above explanation, if the interface circuit illustrated in Fig. 2 is used, not only can the connection between I2L and peripheral circuits be made very stable, but it can also be used for practical purposes even against fluctuations in the injector current used for I2L. Possible interfaces are configurable, in addition to I2L and PNP
) Since it is a combination of Run Sisters and does not use high resistance, it is very suitable for semiconductor integrated circuits and can propose the following interface circuit.

Note that the present invention is not limited to the above embodiments, and the present invention is not limited to the above embodiments.
PN) It is also possible to vary the output current by changing the collector 14゜150 area ratio of the Lancistor 11, and
PN) by changing the ratio to the collector area of Runcistor 5
(PN) It is also possible to vary the drive ratio of the run transistor 5.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram illustrating a conventional interface circuit between I2L and peripheral circuits. FIG. 2 is a circuit diagram illustrating an interface circuit according to an embodiment of the present invention. 1...First power supply terminal, 2...Ground terminal, 3...-I2L circuit% 4.10...Constant current source composed of horizontal PNP transistors, 5,10
... Reverse direction trace transistor, 6 ... Forward direction NPN) run transistor, 7 ... Injector power supply terminal, 8.9 ... Resistor, 12.13・・・
...PNP) Runcissta, 14.15...
(reverse direction NPN) collector section of a run sister. Figure 1 Figure 2

Claims (1)

[Claims] horizontal PNP) run sister with a grounded base, and
An I"1 circuit composed of a vertical NPN (vertical NPN) run transistor whose transistor is grounded, and a first vertical transistor having first and second collectors, the first collector being connected to its base, 1 - A semiconductor circuit characterized in that the second collector of the first vertical transistor comprises a second vertical transistor connected to the collector via a current collector circuit.